CN114759080B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
- Publication number
- CN114759080B CN114759080B CN202210659098.6A CN202210659098A CN114759080B CN 114759080 B CN114759080 B CN 114759080B CN 202210659098 A CN202210659098 A CN 202210659098A CN 114759080 B CN114759080 B CN 114759080B
- Authority
- CN
- China
- Prior art keywords
- doped layer
- layer
- type
- heavily doped
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 22
- 229910002601 GaN Inorganic materials 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 41
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. And the energy band is adjusted by virtue of the higher doping concentration of the P-type heavily doped layer to reduce the concentration of two-dimensional electron gas at the channel below the grid, and the depletion region below the grid is enlarged, so that the electric field peak value below the grid is relieved, and the withstand voltage of the device is improved. The extension part of the first P-type lightly doped layer at least covers the side surface of the P-type heavily doped layer, so that the electric field on the side surface of the gate can be effectively modulated by the extension part, the electric field intensity or the electric field peak value on the side surface of the gate is reduced, and the voltage resistance of the device is improved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Due to the limitations of the first and second generation semiconductor materials represented by Si and GaAs, the third generation wide bandgap semiconductor materials have been rapidly developed because of their excellent properties. GaN material is one of the cores of the third generation semiconductor material, and is characterized by its polarization effect compared to Si, GaAs and SiC. By utilizing the particularity, AlGaN/GaN high electron mobility transistors have been developed, and AlGaN/GaN HEMTs are GaN-based microelectronic devices fabricated on the basis of AlGaN/GaN heterojunction materials. The AlGaN/GaN heterojunction forms a high-density two-dimensional electron gas (2 DEG) at a heterojunction interface through spontaneous polarization and piezoelectric polarization effects, and the two-dimensional electron gas has high mobility, so that the AlGaN/GaN HEMTs have low on-resistance.
In the conventional GaN device, a P-type layer under a gate is often introduced to improve the performance of the device, but when the doping concentration of the P-type layer is too low, the threshold value of the device is often low, and when the doping concentration of the P-type layer is too high, an interface electric field of a Schottky structure formed by gate metal and the P-type layer under the forward bias of the gate is very high, so that the forward withstand voltage of the gate is limited, and the reliability of the device is influenced by the gate leakage current of the gate of the device.
Disclosure of Invention
The present application aims to overcome the above-mentioned deficiencies in the prior art, and provide a semiconductor device and a method for manufacturing the same, so that the semiconductor device can improve the gate threshold, reduce the gate leakage current, and effectively improve the electric field modulation effect of the side surface of the gate.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in one aspect of the embodiments of the present application, a semiconductor device is provided, including a substrate and a semiconductor layer disposed on the substrate, where the semiconductor layer includes a source region, a drain region and a gate region, a stacked P-type heavily doped layer and a first P-type lightly doped layer are sequentially disposed in the gate region of the semiconductor layer, the first P-type lightly doped layer includes a continuous body portion and an extension portion, the body portion is located on a top surface of the P-type heavily doped layer, the extension portion at least covers a side surface of the P-type heavily doped layer, a source metal and a drain metal are disposed in the source region and the drain region of the semiconductor layer, respectively, and a gate metal is disposed on the body portion.
Optionally, the extension portion includes a first modulation portion and a second modulation portion, the first modulation portion covers a side surface of the P-type heavily doped layer, and the second modulation portion is located on a surface of the semiconductor layer and extends toward the source region and/or the drain region.
Optionally, a groove corresponding to the second modulation part is formed in the surface of the semiconductor layer, the groove is located on one side of the P-type heavily doped layer close to the source region and/or the drain region, and at least part of the second modulation part is located in the groove correspondingly.
Optionally, the second modulation portion includes a first sub-portion and a second sub-portion, which are continuously disposed in a direction away from the P-type heavily doped layer, the first sub-portion is located in the groove, and the second sub-portion is located outside the groove.
Optionally, a second P-type lightly doped layer is further disposed between the P-type heavily doped layer and the semiconductor layer.
Optionally, the extension portion covers at least a side surface of the P-type heavily doped layer and a side surface of the second P-type lightly doped layer.
Optionally, the first P-type lightly doped layer, the second P-type lightly doped layer, and the P-type heavily doped layer are all P-type gallium nitride layers.
In another aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is provided, where the method includes: forming a semiconductor layer on a substrate, the semiconductor layer including a source region, a drain region and a gate region; sequentially forming a stacked P-type heavily doped layer and a first P-type lightly doped layer in a gate region of the semiconductor layer, wherein the first P-type lightly doped layer comprises a continuous body part and an extension part, the body part is positioned on the top surface of the P-type heavily doped layer, and the extension part at least covers the side surface of the P-type heavily doped layer; forming a source metal and a drain metal in a source region and a drain region of the semiconductor layer, respectively; a gate metal is formed on the body portion.
Optionally, the extension portion includes a first modulation portion and a second modulation portion, the first modulation portion covers a side surface of the P-type heavily doped layer, and the second modulation portion is located on a surface of the semiconductor layer and extends toward the source region and/or the drain region.
Optionally, the sequentially forming a stacked P-type heavily doped layer and a stacked first P-type lightly doped layer in the gate region of the semiconductor layer includes: forming a P-type heavily doped layer in a gate region of the semiconductor layer; etching the semiconductor layer on one side of the P-type heavily doped layer close to the source region and/or the drain region to form a groove; and a first P-type lightly doped layer is formed on the P-type heavily doped layer, wherein at least part of the second modulation part is correspondingly positioned in the groove.
The beneficial effect of this application includes:
the semiconductor device comprises a substrate and a semiconductor layer arranged on the substrate, wherein a grid comprises a P-type heavily doped layer, a first P-type lightly doped layer and grid metal which are sequentially stacked in a grid region of the semiconductor layer, the grid metal and the first P-type lightly doped layer form Schottky contact, and as the doping concentration of the first P-type lightly doped layer is low, a Schottky barrier can be increased, the Schottky electric field intensity is reduced, so that the forward withstand voltage of the grid is improved, and meanwhile, the grid leakage current is reduced. In addition, in order to consume the two-dimensional electron gas (2 DEG) at the channel below the grid electrode and reduce the concentration of the 2DEG at the channel below the grid electrode, the energy band can be adjusted by means of the higher doping concentration of the P-type heavily doped layer, and therefore the depletion region below the grid electrode can be enlarged due to the arrangement of the P-type heavily doped layer, the electric field peak value below the grid electrode is relieved, and the withstand voltage of the device is improved. The first P-type lightly doped layer comprises a continuous body part and an extension part, the body part covers the top surface of the P-type heavily doped layer to facilitate Schottky contact with the gate metal, and the extension part at least covers the side surface of the P-type heavily doped layer, so that an electric field on the side surface of the gate can be effectively modulated by the extension part, the electric field intensity or the electric field peak value on the side surface of the gate is reduced, and the withstand voltage of the device is improved.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a second schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 4 is a third schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 5 is a fourth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 9 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
An icon: 100-a substrate; 110-a semiconductor layer; a 120-P type heavily doped layer; 130-a groove; 140-a first P-type lightly doped layer; 141-a body portion; 142-an extension; 143-a first modulation section; 144-a second modulation section; 145-the first sub-portion; 146-a second subsection; 150-a second P-type lightly doped layer; 160-a passivation layer; 170-a dielectric layer; 180-source metal; 190-drain metal; 200-gate metal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In one aspect of the embodiments of the present application, as shown in fig. 7 to 9, a semiconductor device is provided, which includes a substrate 100 and a semiconductor layer 110 disposed on the substrate 100, the semiconductor layer 110 includes a source region, a drain region and a gate region, a source metal 180 disposed in the source region and in ohmic contact with the semiconductor layer 110, a drain metal 190 disposed in the drain region and in ohmic contact with the semiconductor layer 110, and a gate correspondingly disposed in the gate region, so that a transistor device is formed by the source metal 180 and the drain metal 190 in cooperation with the gate.
With reference to fig. 7 to 9, the gate includes a P-type heavily doped layer 120, a first P-type lightly doped layer 140, and a gate metal 200 sequentially stacked on the gate region of the semiconductor layer 110, wherein the gate metal 200 forms a schottky contact with the first P-type lightly doped layer 140, and the doping concentration of the first P-type lightly doped layer 140 is low, so that the schottky barrier can be increased, the schottky electric field intensity can be reduced, the forward breakdown voltage of the gate can be increased, and the gate leakage current can be reduced. In order to consume the two-dimensional electron gas (2 DEG) at the channel below the gate electrode and reduce the concentration of the 2DEG at the channel below the gate electrode, the energy band can be adjusted by means of the higher doping concentration of the P-type heavily doped layer 120, and due to the arrangement of the P-type heavily doped layer 120, the depletion region below the gate electrode can be enlarged, so that the electric field peak value below the gate electrode is relieved, and the withstand voltage of the device is improved.
As shown in fig. 6 to 9, the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, the body portion 141 covers the top surface of the P-type heavily doped layer 120 to facilitate schottky contact with the gate metal 200, and the extension portion 142 at least covers the side surface of the P-type heavily doped layer 120, so that the electric field at the side surface of the gate can be effectively modulated by the extension portion 142, thereby reducing the electric field intensity or electric field peak value at the side surface of the gate, and contributing to improving the withstand voltage of the device.
In some embodiments, the substrate 100 may be a silicon carbide substrate 100, a gallium nitride substrate 100, a silicon substrate 100, a sapphire substrate 100, a diamond substrate 100, or the like, which is not limited in the present application and may be reasonably selected according to actual requirements.
In some embodiments, the semiconductor layer 110 is formed on the substrate 100 by epitaxial growth, the semiconductor layer 110 may include a plurality of active semiconductor layers 110, and a two-dimensional electron gas (2 DEG) can be formed at an interface of at least two active semiconductor layers 110 of the plurality of active semiconductor layers 110 to serve as a current channel between the source metal 180 and the drain metal 190 when the transistor device is turned on.
For convenience of description, embodiments of the present application will be described below with reference to fig. 6 to 9 according to different coverage ranges of the extension portion 142 and corresponding electric field modulation capable of achieving different effects.
In one embodiment, referring to fig. 7, a stacked P-type heavily doped layer 120, a first P-type lightly doped layer 140 and a gate metal 200 are sequentially disposed in a gate region of a semiconductor layer 110, for the first P-type lightly doped layer 140, the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, the body portion 141 covers the top surface of the P-type heavily doped layer 120 to facilitate schottky contact with the gate metal 200, the extension portion 142 covers one side surface of the P-type heavily doped layer 120 near the source region and the other side surface of the P-type heavily doped layer 120 near the drain region, thereby, the electric field at the side of the gate near the source and drain regions can be effectively modulated by the extension 142, therefore, the electric field intensity or the electric field peak value of the grid close to the side surfaces of the source electrode region and the drain electrode region is reduced, and the voltage resistance of the device is improved. In addition, when the extension portion 142 covers a side surface of the P-type heavily doped layer 120 close to the source region, the electric field of the side surface is correspondingly modulated; when the extension portion 142 covers a side of the P-type heavily doped layer 120 close to the drain region, the electric field of the side is correspondingly modulated.
In an embodiment, referring to fig. 8, a stacked P-type heavily doped layer 120, a first P-type lightly doped layer 140 and a gate metal 200 are sequentially disposed in a gate region of a semiconductor layer 110, wherein for the first P-type lightly doped layer 140, the first P-type lightly doped layer 140 includes a continuous body portion 141 and extension portions 142, the body portion 141 covers a top surface of the P-type heavily doped layer 120 to facilitate schottky contact with the gate metal 200, the extension portions 142 are two sets, each set of the extension portions 142 includes a first modulation portion 143 continuous with the body portion 141 and a second modulation portion 144 continuous with the first modulation portion 143, and for one set of the extension portions 142: the first modulation part 143 covers the side surface of the P-type heavily doped layer 120 close to the source region, the second modulation part 144 is continuous with the first modulation part 143, and the second modulation part 144 extends from the surface of the semiconductor layer 110 to the source region by a certain length; for the other set of extensions 142: the first modulation part 143 covers the side surface of the P-type heavily doped layer 120 close to the drain region, the second modulation part 144 is continuous with the first modulation part 143, and the second modulation part 144 extends from the surface of the semiconductor layer 110 to the drain region by a certain length, so that the peak value of the electric field on the side surface of the gate can be relieved by the first modulation parts 143 in the two groups, and the electric field in a certain distance around the gate can be further effectively modulated by the second modulation parts 144 in the two groups extending outwards by a certain length, thereby expanding the range of electric field modulation.
In addition, when the first modulation part 143 and the second modulation part 144 of the extension part 142 are located on the side of the P-type heavily doped layer 120 close to the source region, the electric field on the side is correspondingly modulated; when the first modulation part 143 and the second modulation part 144 of the extension part 142 are located on the side of the P-type heavily doped layer 120 close to the drain region, the electric field on the side is correspondingly modulated.
In an embodiment, referring to fig. 3, by etching the semiconductor layer 110 on two opposite sides of the P-type heavily doped layer 120, the groove 130 is formed on the P-type heavily doped layer 120 and the semiconductor layer 110 between the source region and the P-type heavily doped layer 120 and the drain region, and the groove 130 is close to the P-type heavily doped layer 120, so that the barrier layers on two sides of the gate are thinned by etching a certain depth to form the groove 130, thereby reducing the concentration of 2DEG at the channel below the groove 130 and assisting to realize the electric field modulation on two sides of the gate. In addition, the groove 130 may be formed on only one side of the gate by etching, so as to correspondingly realize the modulation of the electric field on the side.
In an embodiment, referring to fig. 3 and fig. 8 in combination, a stacked P-type heavily doped layer 120, a first P-type lightly doped layer 140 and a gate metal 200 are sequentially disposed in a gate region of a semiconductor layer 110, wherein for an extension portion 142 of the first P-type lightly doped layer 140, each set of extension portions 142 includes a first modulation portion 143 continuous with a body portion 141 and a second modulation portion 144 continuous with the first modulation portion 143, and for the second modulation portion 144 of one set of extension portions 142: the second modulation part 144 is continuous with the first modulation part 143, and the second modulation part 144 is filled in the groove 130 on the surface of the semiconductor layer 110 near the source region; for the second modulating portion 144 of the other set of extensions 142: the second modulation part 144 is continuous with the first modulation part 143, and the second modulation part 144 is filled in the groove 130 on the surface of the semiconductor layer 110 near the drain region, so that the peak value of the electric field on the side surface of the gate is relieved by the first modulation part 143 in the two groups, and the electric field around the gate can be modulated more effectively by the second modulation part 144 in the two groups in combination with the groove 130. In addition, the groove 130 may be combined with the second modulation part 144 only at one side of the gate, so as to correspondingly modulate the electric field at the side.
In an embodiment, referring to fig. 3, fig. 5 and fig. 6 in combination, a stacked P-type heavily doped layer 120, a first P-type lightly doped layer 140 and a gate metal 200 are sequentially disposed in a gate region of a semiconductor layer 110, wherein for an extension portion 142 of the first P-type lightly doped layer 140, each set of the extension portion 142 includes a first modulation portion 143 continuous with a body portion 141 and a second modulation portion 144 continuous with the first modulation portion 143, the second modulation portion 144 in each set includes a first sub-portion 145 continuous with the first modulation portion 143 and a second sub-portion 146 continuous with the first sub-portion 145, and for one set of the second modulation portions 144: the first sub-portion 145 is filled in the recess 130 near the source region on the surface of the semiconductor layer 110, and the second sub-portion 146 is located outside the recess 130 and extends a certain length toward the source region; for the other set of second modulation sections 144: the first sub-portion 145 is filled in the groove 130 near the drain region on the surface of the semiconductor layer 110, and the second sub-portion 146 is located outside the groove 130 and extends a certain length toward the drain region; thus, on the basis of the mitigation of the electric field peak at the side of the gate by the first modulation portion 143 in the two sets, the consumption of the 2DEG around the gate by the first sub-portion 145 in the two sets in combination with the groove 130 (first step) and the second sub-portion 146 (second step) is also changed in two steps, that is, the first step closer to the gate realizes more consumption, and the second step slightly farther from the gate realizes slightly lower consumption, so that the concentration of the 2DEG is gradually increased from the gate toward both the source region and the drain region, thereby avoiding a new electric field peak possibly introduced by the sudden increase of the electric field at the edge of the first P-type lightly doped layer 140. In addition, similarly, the first sub-portion 145 and the second sub-portion 146 may be disposed on only one side of the gate, so as to correspondingly modulate the electric field on the side.
In one embodiment, please refer to fig. 3 and fig. 9 in combination, which is different from the previous embodiment in that: a second P-type lightly doped layer 150 is further disposed between the P-type heavily doped layer 120 and the semiconductor layer 110, and the first modulator 143 covers the side surface of the second P-type lightly doped layer 150 as well as the side surface of the P-type heavily doped layer 120. The gate fringe electric field is increased under a large voltage, and the electric field intensity can be reduced through the low doping concentration of the second P-type lightly doped layer 150, so that avalanche breakdown is not easy to occur at corners, and the gate withstand voltage can be increased.
In some embodiments, the first P-type lightly doped layer 140, the second P-type lightly doped layer 150, and the P-type heavily doped layer 120 are all P-type gallium nitride layers.
In addition, as shown in fig. 6 to 9, a passivation layer 160 and a dielectric layer 170 may be further disposed between the gate and source metals 180 and between the gate and drain metals 190, which are sequentially stacked.
In another aspect of the embodiments of the present application, there is provided a method for manufacturing a semiconductor device, as shown in fig. 1, the method including:
s010: a semiconductor layer 110 is formed on the substrate 100, and the semiconductor layer 110 includes a source region, a drain region, and a gate region.
As shown in fig. 2, a semiconductor layer 110 is first deposited on a substrate 100 by a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), or an Atomic Layer Deposition (ALD), and the semiconductor layer 110 includes a source region, a drain region, and a gate region, it should be understood that the source region, the drain region, and the gate region are respectively regions corresponding to a source metal 180, a drain metal 190, and a gate which are subsequently formed, and belong to a pre-divided virtual region, the three regions are spaced apart from each other, and the gate region is located between the source region and the drain region.
S020: a stacked P-type heavily doped layer 120 and a first P-type lightly doped layer 140 are sequentially formed in a gate region of the semiconductor layer 110, wherein the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, the body portion 141 is located on a top surface of the P-type heavily doped layer 120, and the extension portion 142 at least covers a side surface of the P-type heavily doped layer 120.
As shown in fig. 2, an entire P-type layer is epitaxially grown in the gate region of the semiconductor layer 110, and then only a portion of the P-type layer remains in the gate region as a P-type heavily doped layer 120 by etching.
As shown in fig. 4 and fig. 5, a portion of the P-type layer is remained in the gate region as the first P-type lightly doped layer 140 by etching through the epitaxial whole P-type layer, the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, the body portion 141 is located on the top surface of the P-type heavily doped layer 120, and the extension portion 142 at least covers the side surface of the P-type heavily doped layer 120. Therefore, the extension portion 142 can effectively modulate the electric field on the side surface of the gate, thereby reducing the electric field intensity or the electric field peak value on the side surface of the gate and contributing to improving the withstand voltage of the device.
S030: a source metal 180 and a drain metal 190 are formed in the source region and the drain region of the semiconductor layer 110, respectively.
As shown in fig. 6, the source metal 180 and the drain metal 190 are formed on the semiconductor layer 110, and both can be formed in the same step, for example: a photoresist layer is coated on the surface of the semiconductor layer 110, and a first window and a second window are formed on the photoresist layer through processes such as exposure, development and the like, wherein the first window is located in the source region, and the second window is located in the drain region. Source metal 180 and drain metal 190 are then formed in the source and drain regions, respectively, by a process of metal evaporation, metal lift-off, or the like.
S040: a gate metal 200 is formed on the body portion 141.
A gate metal 200 is formed in the gate region of the semiconductor layer 110, and the gate metal 200 makes schottky contact with the first P-type lightly doped layer 140. Similarly, the gate metal 200 may also be formed by photolithography, evaporation, metal lift-off, or other processes.
As shown in fig. 4 to 6, the extension portion 142 includes a continuous first modulation portion 143 and a second modulation portion 144, the first modulation portion 143 covers a side surface of the P-type heavily doped layer 120, and the second modulation portion 144 is located on a surface of the semiconductor layer 110 and extends toward the source region and/or the drain region.
As shown in fig. 3, after the P-type heavily doped layer 120 is formed on the semiconductor layer 110, the groove 130 may be formed by etching on both sides of the P-type heavily doped layer 120, and then the first P-type lightly doped layer 140 may be formed on the P-type heavily doped layer 120, so that the second modulation part 144 extending on the semiconductor layer 110 may be at least partially filled in the groove 130. Correspondingly, for example, as shown in fig. 8, the second modulation part 144 is completely filled in the groove 130; for example, as shown in fig. 5, the first sub-portion 145 of the second modulation part 144 is filled in the groove 130, and the second sub-portion 146 of the second modulation part 144 is located outside the groove 130.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. The semiconductor device is characterized by comprising a substrate and a semiconductor layer arranged on the substrate, wherein the semiconductor layer comprises a source region, a drain region and a gate region, a stacked P-type heavy doping layer and a first P-type light doping layer are sequentially arranged in the gate region of the semiconductor layer, the first P-type light doping layer comprises a continuous body part and an extension part, the body part is positioned on the top surface of the P-type heavy doping layer, the extension part at least covers the side surface of the P-type heavy doping layer, a source metal and a drain metal are respectively arranged in the source region and the drain region of the semiconductor layer, and a gate metal is arranged on the body part.
2. The semiconductor device according to claim 1, wherein the extension portion comprises a first modulation portion and a second modulation portion which are continuous, the first modulation portion covers a side surface of the P-type heavily doped layer, and the second modulation portion is located on the surface of the semiconductor layer and extends toward the source region and/or the drain region.
3. The semiconductor device according to claim 2, wherein a groove corresponding to the second modulation part is formed in the surface of the semiconductor layer, the groove is located on a side of the P-type heavily doped layer close to the source region and/or the drain region, and the second modulation part is at least partially located in the groove.
4. The semiconductor device according to claim 3, wherein the second modulation section includes a first sub-section and a second sub-section which are successively arranged in a direction away from the P-type heavily doped layer, the first sub-section being located inside the groove, the second sub-section being located outside the groove.
5. The semiconductor device according to any one of claims 1 to 4, wherein a second P-type lightly doped layer is further provided between the P-type heavily doped layer and the semiconductor layer.
6. The semiconductor device of claim 5, wherein the extension covers at least a side of the P-type heavily doped layer and a side of the second P-type lightly doped layer.
7. The semiconductor device of claim 1, wherein the first P-type lightly doped layer, the second P-type lightly doped layer, and the P-type heavily doped layer are all P-type gallium nitride layers.
8. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor layer on a substrate, the semiconductor layer including a source region, a drain region and a gate region;
sequentially forming a stacked P-type heavily doped layer and a first P-type lightly doped layer in a gate region of the semiconductor layer, wherein the first P-type lightly doped layer comprises a continuous body part and an extension part, the body part is positioned on the top surface of the P-type heavily doped layer, and the extension part at least covers the side surface of the P-type heavily doped layer;
forming a source metal and a drain metal in a source region and a drain region of the semiconductor layer, respectively;
a gate metal is formed on the body portion.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the extension portion comprises a first modulation portion and a second modulation portion which are continuous, the first modulation portion covers a side surface of the P-type heavily doped layer, and the second modulation portion is located on the surface of the semiconductor layer and extends toward the source region and/or the drain region.
10. The method for manufacturing a semiconductor device according to claim 9, wherein the sequentially forming the stacked P-type heavily doped layer and the first P-type lightly doped layer in the gate region of the semiconductor layer comprises:
forming a P-type heavily doped layer in the gate region of the semiconductor layer;
etching the semiconductor layer on one side of the P-type heavily doped layer close to the source region and/or the drain region to form a groove;
and a first P-type lightly doped layer is formed on the P-type heavily doped layer, wherein at least part of the second modulation part is correspondingly positioned in the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210659098.6A CN114759080B (en) | 2022-06-13 | 2022-06-13 | Semiconductor device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210659098.6A CN114759080B (en) | 2022-06-13 | 2022-06-13 | Semiconductor device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114759080A CN114759080A (en) | 2022-07-15 |
| CN114759080B true CN114759080B (en) | 2022-09-09 |
Family
ID=82336483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210659098.6A Active CN114759080B (en) | 2022-06-13 | 2022-06-13 | Semiconductor device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114759080B (en) |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7274083B1 (en) * | 2006-05-02 | 2007-09-25 | Semisouth Laboratories, Inc. | Semiconductor device with surge current protection and method of making the same |
| JP5032965B2 (en) * | 2007-12-10 | 2012-09-26 | パナソニック株式会社 | Nitride semiconductor transistor and manufacturing method thereof |
| US8785944B2 (en) * | 2011-12-07 | 2014-07-22 | Samsung Electronics Co., Ltd. | High electron mobility transistor |
| JP6119215B2 (en) * | 2012-12-03 | 2017-04-26 | 日亜化学工業株式会社 | Field effect transistor |
| WO2015008430A1 (en) * | 2013-07-16 | 2015-01-22 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| JP2015177063A (en) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | semiconductor device |
| TWI649873B (en) * | 2017-07-26 | 2019-02-01 | 財團法人工業技術研究院 | Iii-nitride based semiconductor structure |
| CN111048576B (en) * | 2018-10-15 | 2024-02-02 | 苏州捷芯威半导体有限公司 | Semiconductor device and preparation method thereof |
| CN110676318A (en) * | 2019-11-14 | 2020-01-10 | 广东致能科技有限公司 | Semiconductor device and manufacturing method thereof |
| US11799268B2 (en) * | 2020-08-24 | 2023-10-24 | Geoff W. Taylor | Semiconductor integrated circuit and methodology for making same |
| US20220130988A1 (en) * | 2020-10-27 | 2022-04-28 | Texas Instruments Incorporated | Electronic device with enhancement mode gallium nitride transistor, and method of making same |
| TWI780513B (en) * | 2020-11-13 | 2022-10-11 | 國立中山大學 | P-GaN HIGH ELECTRON MOBILITY TRANSISTOR |
| CN113851522B (en) * | 2021-08-30 | 2023-07-28 | 湖南三安半导体有限责任公司 | Gallium nitride enhanced device and preparation method thereof |
| CN113594038B (en) * | 2021-09-27 | 2022-03-04 | 深圳市时代速信科技有限公司 | Semiconductor device preparation method |
| CN113793806A (en) * | 2021-11-16 | 2021-12-14 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method |
| CN114496789A (en) * | 2021-12-24 | 2022-05-13 | 西安电子科技大学芜湖研究院 | Preparation method of enhancement type transistor and enhancement type transistor |
-
2022
- 2022-06-13 CN CN202210659098.6A patent/CN114759080B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114759080A (en) | 2022-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10103219B2 (en) | Power semiconductor device and method for manufacturing the same | |
| US20210320199A1 (en) | Enhancement-mode semiconductor device and preparation method therefor | |
| US9385225B2 (en) | Method of making a circuit structure having islands between source and drain | |
| KR101285598B1 (en) | Nitride baced heterostructure semiconductor device and manufacturing method thereof | |
| US8698202B2 (en) | Semiconductor device | |
| US10998435B2 (en) | Enhancement-mode device and method for manufacturing the same | |
| JP2013172152A (en) | Power transistor having segmented gate | |
| US20130313613A1 (en) | Selectively Area Regrown III-Nitride High Electron Mobility Transistor | |
| WO2022116915A1 (en) | Semiconductor device, and application and manufacturing methods therefor | |
| CN107958939A (en) | One kind nitridation Gallium base heterojunction Schottky diode structures | |
| CN117253917A (en) | GaN MIS HEMT shielded by surface trap and preparation method thereof | |
| WO2021035946A1 (en) | Transistor having high withstand voltage and high electron mobility and preparation method therefor | |
| CN114759080B (en) | Semiconductor device and preparation method thereof | |
| TWI732813B (en) | Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device | |
| CN113363319B (en) | Normally-off gallium oxide based MIS-HFET device | |
| WO2022062281A1 (en) | High threshold power semiconductor device and manufacturing method therefor | |
| JP2008227432A (en) | Nitride compound semiconductor element and its production process | |
| CN113871478A (en) | Novel semiconductor device with P-type channel characteristic based on double gates | |
| CN107958930A (en) | One kind nitridation Gallium radical heterojunction field effect transistor structures | |
| CN109817711B (en) | Gallium nitride transverse transistor with AlGaN/GaN heterojunction and manufacturing method thereof | |
| CN107958931A (en) | One kind nitridation Gallium base heterojunctions field-effect transistor structure of resistance to breakdown | |
| KR102067596B1 (en) | Nitride semiconductor and method thereof | |
| CN113380877A (en) | Power device of double-junction field plate | |
| CN107170820B (en) | Current aperture heterojunction device of arc-shaped gate-drain composite field plate | |
| US20230387284A1 (en) | Enhancement mode switching devices and manufacturing methods thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |