CN113594038B - Semiconductor device preparation method - Google Patents
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- CN113594038B CN113594038B CN202111132602.9A CN202111132602A CN113594038B CN 113594038 B CN113594038 B CN 113594038B CN 202111132602 A CN202111132602 A CN 202111132602A CN 113594038 B CN113594038 B CN 113594038B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000002360 preparation method Methods 0.000 title abstract description 5
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- 239000002184 metal Substances 0.000 claims abstract description 314
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application provides a semiconductor device preparation method, which relates to the technical field of semiconductors and comprises the following steps: forming a semiconductor stack on a substrate; forming source ohmic metal in a source region and drain ohmic metal in a drain region of the semiconductor stack; forming a gate metal in contact with the semiconductor stack between the source region and the drain region; forming a first dielectric layer on the grid metal; the first dielectric layer coated on the surface of the gate metal is etched, so that the gradient of the first dielectric layer on the side wall of the gate metal is reduced, the continuity of the field plate metal on the first dielectric layer on the side wall of the gate metal is better when the field plate metal is manufactured on the first dielectric layer, and the performance of the device can be effectively improved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device manufacturing method.
Background
With the high integration of semiconductor devices, efforts have been made to improve the yield of semiconductor devices. In the semiconductor preparation process, in order to reduce the gate resistance and the gate length, a T-shaped gate is generally adopted and is limited by the process, and two side walls of a gate cap of the T-shaped gate are generally provided with larger inclination angles.
Disclosure of Invention
The present application is directed to provide a method for manufacturing a semiconductor device, which improves continuity of field plate metal by reducing a slope.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in one aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is provided, where the method includes: forming a semiconductor lamination layer on a substrate, wherein the semiconductor lamination layer comprises a source electrode region and a drain electrode region which are arranged at intervals; forming source ohmic metal in a source region and drain ohmic metal in a drain region of the semiconductor stack; forming a gate metal in contact with the semiconductor stack between the source region and the drain region; forming a first dielectric layer on the gate metal, wherein the thickness ratio of the first dielectric layer at the top corner of the gate metal to the first dielectric layer at the bottom corner of the gate metal is a first thickness ratio; etching the first dielectric layer coated on the surface of the gate metal, wherein the thickness ratio of the first dielectric layer at the top corner of the gate metal after etching to the first dielectric layer at the bottom corner of the gate metal after etching is a second thickness ratio, and the second thickness ratio is smaller than the first thickness ratio; and forming field plate metal on the first dielectric layer.
Optionally, the second thickness ratio is 0.6 to 1.5.
Optionally, forming a gate metal in contact with the semiconductor stack between the source region and the drain region includes: forming a passivation layer on the source ohmic metal and the drain ohmic metal; and etching the passivation layer to form a gate groove between the source ohmic metal and the drain ohmic metal, and forming a gate metal in contact with the semiconductor stacked layer in the gate groove.
Optionally, after the first dielectric layer is formed on the gate metal, the method further includes: sequentially etching the first dielectric layer and the passivation layer to form a first window above the source ohmic metal and the drain ohmic metal respectively; and forming first metal laminated layers in the first windows respectively, wherein the first metal laminated layers comprise Ti/Au which are formed in sequence.
Optionally, after forming the first metal stacks in the first windows respectively, the method further includes: forming a second metal lamination layer on the first metal lamination layer above the source electrode ohmic metal and the drain electrode ohmic metal respectively, wherein the second metal lamination layer at least comprises Ni; forming a second dielectric layer on the second metal lamination; etching the second dielectric layer to form second windows on the second metal lamination layer above the source electrode ohmic metal and the drain electrode ohmic metal respectively; and forming a third metal lamination layer in the second windows respectively, wherein the third metal lamination layer at least comprises W.
Optionally, the second metal stack comprises Ti/Ni/Au, Ti/Ni/Ti/Au or Ti/Ni/Pt/Au formed in sequence.
Optionally, the third metal stack comprises sequentially formed Ti/W, with a composition ratio of Ti to W of 1:9 to 3: 7.
Optionally, the source ohmic metal includes a first source ohmic metal and a second source ohmic metal, and the first source ohmic metal and the second source ohmic metal are sequentially arranged in the source region at intervals along the gate length direction.
Optionally, a ratio of the width of the first source ohmic metal along the gate length direction to the width of the drain ohmic metal along the gate length direction is 1.2:1 to 1.5:1, and a ratio of the width of the second source ohmic metal along the gate length direction to the width of the drain ohmic metal along the gate length direction is 1.2:1 to 1.5: 1.
Optionally, the passivation layer, the first dielectric layer and the second dielectric layer are made of silicon nitride.
The beneficial effect of this application includes:
the application provides a semiconductor device preparation method, which comprises the following steps: forming a semiconductor lamination layer on a substrate, wherein the semiconductor lamination layer comprises a source electrode region and a drain electrode region which are arranged at intervals; forming source ohmic metal in a source region and drain ohmic metal in a drain region of the semiconductor stack; forming a gate metal in contact with the semiconductor stack between the source region and the drain region; forming a first dielectric layer on the gate metal, wherein the thickness ratio of the first dielectric layer at the top corner of the gate metal to the first dielectric layer at the bottom corner of the gate metal is a first thickness ratio; etching the first dielectric layer coated on the surface of the gate metal, wherein the thickness ratio of the first dielectric layer at the top corner of the gate metal after etching to the first dielectric layer at the bottom corner of the gate metal after etching is a second thickness ratio, and the second thickness ratio is smaller than the first thickness ratio; and forming field plate metal on the first dielectric layer. Because the first dielectric layer coated on the surface of the gate metal slows down the gradient through etching, the continuity of the field plate metal on the first dielectric layer positioned on the side wall of the gate metal is better, and the performance of the device can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a second schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 4 is a third schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 5 is a fourth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 6 is a fifth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 7 is a sixth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 8 is a seventh schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 9 is an eighth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present application;
fig. 10 is a ninth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 11 is a tenth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 12 is an eleventh schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present application;
fig. 13 is a twelfth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 14 is a thirteen schematic views of a manufacturing state of a semiconductor device according to an embodiment of the present disclosure.
Icon: 100-a substrate; 110-a semiconductor stack; 120-a passivation layer; 130-source ohmic metal; 131-a first source ohmic metal; 132-a second source ohmic metal; 140-drain ohmic metal; 150-gate metal; 160-a first dielectric layer; 170-source first metal stack; 180-drain first metal stack; 190-a photoresist layer; 200-field plate metal; 210-a source second metal stack; 220-drain second metal stack; 230-a second dielectric layer; 240-source third metal stack; 250-drain third metal stack.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate 100 is referred to as being "on" or "extending" onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate 100 is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In an aspect of an embodiment of the present application, there is provided a method for manufacturing a semiconductor device, as shown in fig. 1, the method including:
s010: a semiconductor stack 110 is formed on the substrate 100, and the semiconductor stack 110 includes a source region and a drain region that are spaced apart from each other.
As shown in fig. 2, a substrate 100 is first provided, and the substrate 100 may be a base material for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, and the like. And then depositing a semiconductor stack 110 on the substrate 100, where the deposition process is not limited in this application and may be reasonably selected according to actual requirements.
The semiconductor stack 110 may be one layer, two layers, or multiple layers, and should be reasonably selected according to the device type when being disposed, for example, according to an insulated gate field effect transistor (MIS FET), a High Electron Mobility Transistor (HEMT), and the like, which is not limited in this application, and is exemplified by a HEMT device: the semiconductor stack 110 includes at least a channel layer and a barrier layer, and of course, a nucleation layer, a buffer layer, an insertion layer, etc. may be further included on the basis thereof, so as to provide the semiconductor device with better performance.
The semiconductor stack 110 includes a source region and a drain region spaced apart from each other, where the source region serves as a location of a subsequent source, the drain region serves as a location of a subsequent drain, and the source region and the drain region are spaced apart from each other to serve as a location of a subsequent gate. As shown in fig. 13, the source and drain regions are spaced apart from each other on the upper surface of the semiconductor stack 110.
S020: a source ohmic metal 130 is formed in the source region and a drain ohmic metal 140 is formed in the drain region of the stack of semiconductor layers 110.
After S010, as shown in fig. 3, the source ohmic metal 130 and the drain ohmic metal 140 are formed on the semiconductor stacked layer 110, and the source ohmic metal 130 and the drain ohmic metal 140 may be formed in the same step.
In some embodiments, a photoresist layer is coated on the surface of the semiconductor stacked layer 110, windows are opened on the photoresist layer above the source region and the drain region respectively through exposure, development and the like, and a source ohmic metal 130 and a drain ohmic metal 140 are formed in the source region and the drain region respectively through a metal evaporation, metal stripping and the like.
In some embodiments, after the metal strip, the wafer may also be subjected to a high temperature heat treatment (typically a temperature greater than 500 ℃) to alloy the metal, which forms an ohmic contact with the underlying semiconductor stack 110.
S030: a gate metal 150 is formed between the source region and the drain region in contact with the semiconductor stack 110.
As shown in fig. 4, after the source ohmic metal 130 and the drain ohmic metal 140 are formed on the semiconductor stack 110, the gate metal 150 is formed between the source ohmic metal 130 and the drain ohmic metal 140. The gate metal 150 may be formed by photolithography, evaporation, metal lift-off, and the like. The gate metal 150 may form a schottky contact with the semiconductor stack 110. The gate metal 150 may be a stacked metal, such as sequentially formed Ni/Au.
As shown in fig. 4, in order to reduce the gate resistance, the gate metal 150 may be a T-shaped gate structure, and the two sidewalls of the T-shaped gate structure in the gate length direction generally have a larger slope due to the forming process thereof.
S040: a first dielectric layer 160 is formed on the gate metal 150, wherein a thickness ratio of the first dielectric layer 160 at the top corner of the gate metal 150 to the first dielectric layer 160 at the bottom corner of the gate metal 150 is a first thickness ratio.
As shown in fig. 5, after S030, a first dielectric layer 160 is formed on the gate metal 150, the first dielectric layer 160 may be formed by deposition, and the first dielectric layer 160 may also cover the source ohmic metal 130 and the drain ohmic metal 140, that is, the entire first dielectric layer 160 is formed on the gate metal 150, so that the first dielectric layer 160 can perform insulation isolation on the gate metal 150.
Because the side wall slope of the T-shaped gate structure is larger, the first dielectric layer 160 is easily formed into a larger convex hull at the top corner of the gate metal 150 in combination with the process limitation of forming the first dielectric layer 160, so that the slope of the first dielectric layer 160 covering the surface of the gate metal 150 at the two side walls of the gate metal 150 is larger, and if the field plate metal 200 is directly manufactured on the first dielectric layer 160 in the prior art, the field plate metal 200 has poor continuity at the position where the slope of the first dielectric layer 160 is larger, and is easily cracked, and the performance of the device is affected.
As shown in fig. 7, the thickness of the first dielectric layer 160 at the top corner of the gate metal 150 is D1 or D3, and the thickness of the first dielectric layer 160 at the bottom corner of the gate metal 150 is D2 or D4, wherein D1 and D2 are located at the same side, and D3 and D4 are located at the same side, so that the ratio of D1 to D2 or the ratio of D3 to D4 is the first thickness ratio.
S050: and etching the first dielectric layer 160 covering the surface of the gate metal 150, wherein the thickness ratio of the first dielectric layer 160 positioned at the top corner of the gate metal 150 after etching to the first dielectric layer 160 positioned at the bottom corner of the gate metal 150 after etching is a second thickness ratio, and the second thickness ratio is smaller than the first thickness ratio.
In order to reduce the slope of the first dielectric layer 160 at the two sidewalls of the gate metal 150, the first dielectric layer 160 covering the surface of the gate metal 150 may be subjected to a second treatment by etching. For example, as shown in fig. 8, a photoresist layer 190 is coated on the first dielectric layer 160, the first dielectric layer 160 covering the surface of the gate metal 150 is windowed through processes such as exposure and development, and the etching rate is controlled such that the etching rate of the first dielectric layer 160 at the top corner of the gate metal 150 is greater than the etching rate of the first dielectric layer 160 at the bottom corner of the gate metal 150, so as to reduce the convex hull, as shown in fig. 9, such that the second thickness ratio after etching is smaller than the first thickness ratio before etching. For example, as shown in fig. 10, after etching, the thickness of the first dielectric layer 160 at the top corner of the gate metal 150 is D5 or D7, and the thickness of the first dielectric layer 160 at the bottom corner of the gate metal 150 is D6 or D8, where D5 and D6 are located on the same side, D7 and D8 are located on the same side, and the ratio of D5 to D6 or the ratio of D7 to D8 is the second thickness ratio, so as to ensure that the second thickness ratio after etching is smaller than the first thickness ratio before etching, i.e., to reduce the slope of the first dielectric layer 160 covering both sidewalls of the gate metal 150.
In some embodiments, both D6 and D8 are the connection length between the recess of the first dielectric layer 160 and the gate metal gate pin after etching. The starting point of D5 is the gate metal top angle, parallel to D6. The starting point of D7 is the gate metal top angle, parallel to D8.
In some embodiments, the first dielectric layer 160 covering the surface of the gate metal 150 may be etched by F-based plasma.
S060: a field plate metal 200 is formed on the first dielectric layer 160.
As shown in fig. 11, a field plate metal 200 is formed on the first dielectric layer 160, and the field plate metal 200 may fully or half-wrap the gate metal 150, thereby forming better drain electric field isolation. The field plate metal 200 can be fabricated by photolithography, evaporation, metal lift-off, and the like. Because the first dielectric layer 160 covering the surface of the gate metal 150 is etched to reduce the gradient, the continuity of the field plate metal 200 on the first dielectric layer 160 on the sidewall of the gate metal 150 is better, and the performance of the device can be effectively improved.
Optionally, since the first dielectric layer 160 covering the outer surface of the gate metal 150 needs to perform the function of isolating the gate metal 150 from the field plate metal 200, when the first dielectric layer 160 is etched, the second thickness ratio should be 0.6 to 1.5, for example, greater than 0.8, so as to avoid the first dielectric layer 160 being too thin.
Alternatively, when the gate metal 150 contacting the semiconductor stack 110 is formed between the source region and the drain region, as shown in fig. 3, an entire passivation layer 120 may be deposited on the source ohmic metal 130 and the drain ohmic metal 140, i.e., the passivation layer 120 covers the upper surface of the device. Then, as shown in fig. 4, the passivation layer 120 is etched, a gate trench is formed on the passivation layer 120, the gate trench is located between the source ohmic metal 130 and the drain ohmic metal 140, and the bottom of the gate trench exposes the semiconductor stack 110 under the passivation layer 120, and then a gate metal 150 is formed in the gate trench by photolithography, evaporation or electroplating, metal stripping, and the like, and the gate metal 150 forms a schottky contact with the semiconductor stack 110. The gate metal 150, the source ohmic metal 130 and the drain ohmic metal 140 may be insulated and isolated by the passivation layer 120, thereby ensuring the normal operation of the device.
Optionally, after forming the first dielectric layer 160 on the gate metal 150, as shown in fig. 5, a passivation layer 120 and the first dielectric layer 160 are sequentially formed on the source ohmic metal 130 and the drain ohmic metal 140. As shown in fig. 6, by sequentially etching the first dielectric layer 160 and the passivation layer 120, first windows are respectively opened above the source ohmic metal 130 and the drain ohmic metal 140, and then first metal stacks are respectively formed in the first windows, wherein for convenience of distinction, the first metal stack above the source ohmic metal 130 is a source first metal stack 170, and the first metal stack above the drain ohmic metal 140 is a drain first metal stack 180. The source first metal stack 170 and the drain first metal stack 180 may be Ti/Au formed in sequence, so that the source ohmic metal 130 and the drain ohmic metal 140 can be protected by the source first metal stack 170 and the drain first metal stack 180, respectively, degradation in a process is prevented, and failure in a high temperature and high humidity environment is avoided.
Optionally, after forming the first metal stacks in the first windows, as shown in fig. 11, a second metal stack may be further formed on the first metal stack above the source ohmic metal 130 and the drain ohmic metal 140, respectively, for convenience of distinction, the second metal stack above the source first metal stack 170 is a source second metal stack 210, and the second metal stack above the drain first metal stack 180 is a drain second metal stack 220. The source second metal stack 210 and the drain second metal stack 220 each comprise at least Ni metal. In some embodiments, the second metal stack comprises sequentially formed Ti/Ni/Au, Ti/Ni/Ti/Au, or Ti/Ni/Pt/Au. In some embodiments, the second metal stack may be fabricated in a simultaneous step with the field plate metal 200.
As shown in fig. 12, an entire second dielectric layer 230 is then deposited on the source second metal stack 210 and the drain second metal stack 220. Forming a second window over the source second metal stack 210 and the drain second metal stack 220, respectively, by etching the second dielectric layer 230; a third metal stack is formed in the second window, and for the sake of convenience, the third metal stack above the source second metal stack 210 is a source third metal stack 240, and the third metal stack above the drain second metal stack 220 is a drain third metal stack 250. The source third metal stack 240 and the drain third metal stack 250 each include at least W metal. In this way, in combination with the aforementioned source second metal stack 210 and drain second metal stack 220 at least including Ni metal, when the device is at high temperature, the stress offset effect of W metal and Ni metal can be used to avoid metal bulging deformation, thereby effectively improving the reliability of the source structure and drain structure of the device.
In some embodiments, the third metal stack comprises sequentially formed Ti/W, and the composition ratio of Ti to W is 1:9 to 3:7, so that the stress offset effect of the third metal stack and the second metal stack can be effectively improved.
In some embodiments, the second metal stack is Ti/Ni/Au, wherein Ti is 50nm thick, Ni is 300nm thick, and Au is 250nm thick. The third metal lamination is Ti/W, wherein the sum of the thicknesses of Ti and W is 150nm, so that the stress offset effect of the third metal lamination and the second metal lamination can be effectively improved.
Optionally, the source ohmic metal 130 may or may not completely cover the source region, wherein when the source ohmic metal 130 does not completely cover the source region, as shown in fig. 13, the source ohmic metal 130 includes a first source ohmic metal 131 and a second source ohmic metal 132, wherein the first source ohmic metal 131 and the second source ohmic metal 132 are sequentially arranged at intervals in the gate length direction in the source region. In some embodiments, the first and second source ohmic metals 131 and 132 may be disposed near the edge of the source region, respectively, for example, the first source ohmic metal 131 is disposed near the left edge of the source region and the second source ohmic metal 132 is disposed near the right edge of the source region. Thus, after annealing, the first source ohmic metal 131, the second source ohmic metal 132 and the drain ohmic metal 140 have high consistency in morphology, that is, have good flatness.
In some embodiments, the ratio of the width C1 of the first source ohmic metal 131 in the gate length direction to the width C3 of the drain ohmic metal 140 in the gate length direction is 1.2:1 to 1.5:1, i.e., the width C1 of the first source ohmic metal 131 in the gate length direction is 20% to 50% wider than the width C3 of the drain ohmic metal 140 in the gate length direction; the ratio of the width C2 of the second source ohmic metal 132 in the gate length direction to the width C3 of the drain ohmic metal 140 in the gate length direction is 1.2:1 to 1.5:1, i.e., the width C2 of the second source ohmic metal 132 in the gate length direction is 20% to 50% wider than the width C3 of the drain ohmic metal 140 in the gate length direction; in this way, the uniformity of the shapes of the first source ohmic metal 131, the second source ohmic metal 132 and the drain ohmic metal 140 after annealing, that is, the flatness, can be further improved. In some embodiments, the widths C1 and C2 of the first and second source ohmic metals 131 and 132 in the gate length direction are both 15 μm, and the width C3 of the drain ohmic metal 140 in the gate length direction is 10 μm.
In some embodiments, when the source ohmic metal 130 does not completely cover the source region, when forming the source structure, a first source ohmic metal and a second source ohmic metal may be formed at both edges of the source region, as shown in fig. 13, respectively, as shown in fig. 14, and a passivation layer 120, a gate metal 150, and a first dielectric layer 160 may be formed according to fig. 3 to 5, the first dielectric layer 160 and the passivation layer 120 may be sequentially etched, a window may be opened above the source region, and a first metal stack and a second metal stack may be sequentially formed, the first metal stack covering the first source ohmic metal, the second source ohmic metal, and a region between the first source ohmic metal and the second source ohmic metal, the second metal stack may include two spaced portions of metal, the two portions of metal are respectively located right above the first source ohmic metal and the second source ohmic metal, and then a second dielectric layer 230 may be formed, and opening a window above the second metal lamination by etching to manufacture a third metal lamination, wherein the third metal lamination sequentially covers two parts of metal at the interval of the second metal lamination and the first metal lamination exposed between the two parts of metal at the interval of the second metal lamination.
In some embodiments, after the third metal stack is formed, a drain contact hole pattern and a source contact hole pattern may be formed by dry etching (CF 4 etching) or wet etching (etching solution H2O 2) (fig. 12 or fig. 14). It is also possible to use an evaporation method, a dual source co-evaporation method, keeping the composition ratio of Ti at 10% to 30%, and then forming a drain and source contact hole pattern using a lift-off process.
In some embodiments, the passivation layer 120 may be a SiN layer, SiO2One of the layers, the first dielectric layer 160 and the second dielectric layer 230 may be SiN layer or SiO layer2One or more of the layers, i.e., the first dielectric layer 160, the second dielectric layer 230, may be a single dielectric layer formed of one material, or a dielectric stack formed by stacking multiple dielectric layers formed of multiple materials.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (8)
1. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor lamination layer on a substrate, wherein the semiconductor lamination layer comprises a source electrode region and a drain electrode region which are arranged at intervals;
forming source ohmic metal in a source region and drain ohmic metal in a drain region of the semiconductor lamination layer;
forming a gate metal in contact with the semiconductor stack between the source region and the drain region;
forming a first dielectric layer on the gate metal, wherein the thickness ratio of the first dielectric layer at the top corner of the gate metal to the first dielectric layer at the bottom corner of the gate metal is a first thickness ratio;
etching the first dielectric layer coated on the surface of the gate metal, wherein the thickness ratio of the etched first dielectric layer positioned at the top corner of the gate metal to the etched first dielectric layer positioned at the bottom corner of the gate metal is a second thickness ratio, and the second thickness ratio is smaller than the first thickness ratio;
forming a field plate metal on the first dielectric layer;
the source ohmic metal comprises a first source ohmic metal and a second source ohmic metal, and the first source ohmic metal and the second source ohmic metal are sequentially arranged in the source region at intervals along the gate length direction; the first source ohmic metal and the second source ohmic metal are electrically connected;
the ratio of the width of the first source ohmic metal along the gate length direction to the width of the drain ohmic metal along the gate length direction is 1.2:1 to 1.5:1, and the ratio of the width of the second source ohmic metal along the gate length direction to the width of the drain ohmic metal along the gate length direction is 1.2:1 to 1.5: 1.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the second thickness ratio is 0.6 to 1.5.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a gate metal in contact with the semiconductor stack between the source region and the drain region comprises:
forming a passivation layer on the source ohmic metal and the drain ohmic metal;
and etching the passivation layer to form a grid groove between the source electrode ohmic metal and the drain electrode ohmic metal, and forming grid metal in contact with the semiconductor lamination in the grid groove.
4. The method of manufacturing a semiconductor device according to claim 3, wherein after forming a first dielectric layer on the gate metal, the method further comprises:
sequentially etching the first dielectric layer and the passivation layer to form a first window above the source ohmic metal and the drain ohmic metal respectively;
and forming first metal laminated layers in the first windows respectively, wherein the first metal laminated layers comprise Ti/Au which are formed in sequence.
5. The method for manufacturing a semiconductor device according to claim 4, wherein after the forming of the first metal stacks respectively in the first windows, the method further comprises:
forming a second metal lamination layer on the first metal lamination layer above the source electrode ohmic metal and the drain electrode ohmic metal respectively, wherein the second metal lamination layer at least comprises Ni;
forming a second dielectric layer on the second metal lamination;
etching the second dielectric layer to form second windows on the second metal lamination layer above the source electrode ohmic metal and the drain electrode ohmic metal respectively;
and forming third metal lamination layers in the second windows respectively, wherein the third metal lamination layers at least comprise W.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the second metal laminate layer comprises Ti/Ni/Au, Ti/Ni/Ti/Au or Ti/Ni/Pt/Au formed in this order.
7. The semiconductor device manufacturing method according to claim 5, wherein the third metal stack includes sequentially formed Ti/W, and a composition ratio of the Ti to the W is 1:9 to 3: 7.
8. The method for manufacturing a semiconductor device according to claim 5, wherein the passivation layer, the first dielectric layer, and the second dielectric layer are made of silicon nitride.
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