CN114725011A - Air-tight chip structure and preparation method thereof - Google Patents
Air-tight chip structure and preparation method thereof Download PDFInfo
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- CN114725011A CN114725011A CN202210272027.0A CN202210272027A CN114725011A CN 114725011 A CN114725011 A CN 114725011A CN 202210272027 A CN202210272027 A CN 202210272027A CN 114725011 A CN114725011 A CN 114725011A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
Abstract
The invention relates to an air-tight chip structure and a preparation method thereof. The method comprises the following steps: respectively electroplating at least one first copper ring and at least one first copper column on a top TSV chip provided with at least one first circuit area; respectively electroplating at least one second copper ring and at least one second copper column on the bottom chip provided with at least one second circuit area; inversely installing the electroplated top TSV chip on the electroplated bottom chip to form an inverted chip; and (4) planting balls on the top of the flip chip to form an airtight chip structure. The cavity structure with the built-in copper ring is formed based on the middle process and the bumping process, the 3D vertical interconnection among chips can be realized through the cavity structure with the built-in copper ring, the requirement on high air tightness is met, the chip packaging with high air tightness is realized, and the packaging cost is low; through chip stacking, the interconnection density among chips is improved, the requirements of high integration and miniaturization can be met, and the chip type selection is more flexible.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to an airtight chip structure and a preparation method thereof.
Background
Many chip structures require a high hermetic seal and a small volume package. The traditional airtight packaging is usually metal sealing or packaging after the packaging is finished, and the packaging cost is high; or the wafer is sealed by using organic materials such as polymers or dry films, and the air tightness is difficult to ensure.
At present, no technological method for realizing air-tight packaging before packaging is completed exists, and the requirements of high air tightness, miniaturization and low cost can be met at the same time.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is how to achieve the requirements of high air tightness, miniaturization and low cost before the chip packaging is completed.
In order to solve the technical problem, the invention provides a preparation method of an airtight chip structure, which comprises the following steps:
respectively electroplating at least one first copper ring and at least one first copper column on a top TSV chip provided with at least one first circuit area;
respectively electroplating at least one second copper ring and at least one second copper column on the bottom chip provided with at least one second circuit area;
inversely installing the electroplated top TSV chip on the electroplated bottom chip to form an inverted chip;
and planting balls on the top of the flip chip to form an airtight chip structure.
Preferably, the number of the first circuit areas is the same as that of the second circuit areas, and all the first circuit areas correspond to all the second circuit areas one to one;
the number of the first copper rings is the same as that of the first circuit areas, and all the first copper rings correspond to all the first circuit areas one by one; the number of the second copper rings is the same as that of the second line areas, and all the second copper rings correspond to all the second line areas one by one;
at least one first copper ring is electroplated on the top TSV chip provided with at least one first circuit area respectively, and the method comprises the following steps:
plating the corresponding first copper rings on the outer side of each first circuit area on the top TSV chip respectively;
at least one second copper ring is electroplated on the bottom chip provided with at least one second circuit area respectively, including:
and electroplating corresponding second copper rings outside each second circuit area on the bottom chip respectively.
Preferably, each of the first circuit regions includes at least one through silicon via;
the number of the through silicon vias, the number of the first copper pillars and the number of the second copper pillars are the same, all the through silicon vias correspond to all the first copper pillars one to one, and all the second copper pillars correspond to all the first copper pillars one to one;
the top TSV chip after being electroplated is inversely arranged on the bottom TSV chip after being electroplated to form an inverted chip, and the inverted chip comprises:
reversely buckling the electroplated top TSV chip on the electroplated bottom chip so that all the first copper columns on the top TSV chip are in one-to-one corresponding contact with all the second copper columns on the bottom chip, and all the first copper rings on the top TSV chip are in one-to-one corresponding contact with all the second copper rings on the bottom chip;
and welding each first copper column and each second copper column which is correspondingly contacted with the first copper column by adopting a welding flux, and welding each first copper ring and each second copper ring which is correspondingly contacted with the first copper column to form the flip chip.
Preferably, the electroplating at least one first copper pillar on the top TSV chip provided with at least one first line region respectively comprises:
and respectively electroplating corresponding first copper columns at each through silicon hole on the top TSV chip, so that each first copper column is in contact with the corresponding through silicon hole.
Preferably, the ball-planting is performed on the top of the flip chip to form an airtight chip structure, including:
grinding the top of the flip chip to expose all the through silicon vias in the flip chip;
and respectively planting balls on each silicon through hole exposed out of the head to form the airtight chip structure.
Preferably, when the number of the first circuit regions is greater than 1, after at least one first copper ring and at least one first copper pillar are respectively plated on the top TSV chip provided with at least one first circuit region, the method further includes:
and pre-cutting the electroplated top TSV chip according to a first preset scribing way on each first circuit area.
Preferably, the depth of each first preset scribing channel is greater than or equal to the depth of all the through silicon vias.
Preferably, after the ball mounting is performed on each of the exposed through-silicon vias, the method further includes:
and carrying out secondary cutting on the bottom of the flip chip after ball mounting according to a second preset scribing channel on each second circuit area to form the airtight flip chip.
Preferably, before electroplating at least one first copper ring and at least one first copper pillar on the top TSV chip provided with at least one first circuit region, the method further includes:
respectively etching at least one first circuit area on a first wafer substrate to form the top TSV chip;
before at least one second copper ring and at least one second copper post are electroplated on the bottom chip provided with at least one second circuit area respectively, still include:
and etching at least one second circuit area on a second wafer substrate to form the bottom chip.
In addition, the invention also provides an airtight chip structure which is prepared by the preparation method and comprises the following steps:
a bottom chip;
the top TSV chip is inversely arranged on the bottom chip; and
at least one solder ball soldered on the side of the top TSV chip facing away from the bottom chip;
the top TSV chip is provided with at least one first circuit area, and the side surface, facing the bottom chip, of the top TSV chip is plated with at least one first copper ring and at least one first copper column;
and at least one second circuit area is arranged on the bottom chip, and at least one second copper ring and at least one second copper column are plated on the side surface of the bottom chip facing the top TSV chip.
The technical scheme provided by the invention has the following advantages:
according to the airtight chip structure and the preparation method thereof, before packaging is completed, the first copper ring, the first copper pillar, the second copper ring and the second copper pillar are respectively electroplated between the top TSV chip and the bottom chip, the electroplated top TSV chip and the electroplated bottom chip are inverted, and finally balls are planted on the inverted chip; through chip stacking, the interconnection density among chips is improved, the requirements of high integration and miniaturization can be met, and the chip type selection is more flexible.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a method for fabricating a hermetic chip structure according to an embodiment of the present invention;
fig. 2-1 is a schematic top view of a TSV chip according to an embodiment of the invention;
fig. 2-2 is a schematic cross-sectional view of a top TSV chip according to an embodiment of the invention;
fig. 3-1 is a schematic top view of another TSV chip according to an embodiment of the invention;
fig. 3-2 is a schematic cross-sectional view of another top TSV chip according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view of a top TSV chip after being plated according to one embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a top TSV chip after pre-cutting in an embodiment of the invention;
FIG. 6 is a schematic cross-sectional view of a bottom chip according to an embodiment of the invention;
FIG. 7 is a cross-sectional view of a bottom chip after electroplating according to an embodiment of the present invention;
FIG. 8 is a schematic flow chart illustrating a process of forming a flip chip according to an embodiment of the invention;
FIG. 9 is a schematic cross-sectional view of a flip chip according to an embodiment of the invention;
FIG. 10 is a schematic flow chart illustrating a process for forming a hermetic chip structure according to a first embodiment of the present invention;
FIG. 11 is a cross-sectional view of a ground flip chip according to one embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of a flip chip after ball mounting according to an embodiment of the invention;
FIG. 13 is a full cross-sectional view of a hermetic chip structure according to an embodiment of the present invention;
fig. 14 is a full cross-sectional view of another hermetic chip structure according to one embodiment of the present invention.
Description of reference numerals:
100. the top TSV chip comprises 200 parts of a top TSV chip body, 300 parts of a bottom TSV chip body, 400 parts of a solder ball body, 110 parts of a first circuit area, 120 parts of a first copper ring body, 130 parts of a first copper column, 111 parts of a silicon through hole body, 112 parts of a first circuit board body, 210 parts of a second circuit area, 220 parts of a second copper ring body, 230 parts of a second copper column body.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In the present invention, unless specified to the contrary, use of the terms of orientation such as "upper, lower, top, bottom" or the like, generally refer to the orientation as shown in the drawings, or to the component itself in a vertical, perpendicular, or gravitational orientation; likewise, for ease of understanding and description, "inner and outer" refer to the inner and outer relative to the profile of the components themselves, but the above directional words are not intended to limit the invention.
In the traditional airtight packaging technology, metal sealing or wrapping is carried out after packaging is finished, so that the packaging cost is high; and the wafer is sealed by adopting organic materials such as polymer or dry film, and the air tightness is poor.
Example one
As shown in fig. 1, the present embodiment provides a method for manufacturing an airtight chip structure, including:
s110: respectively electroplating at least one first copper ring and at least one first copper column on a top TSV chip provided with at least one first circuit area;
s120: respectively electroplating at least one second copper ring and at least one second copper column on the bottom chip provided with at least one second circuit area;
s130: inversely installing the electroplated top TSV chip on the electroplated bottom chip to form an inverted chip;
s140: and (4) planting balls on the top of the flip chip to form an airtight chip structure.
According to the preparation method, before packaging is completed, the first copper ring, the first copper pillar, the second copper ring and the second copper pillar are electroplated between the top TSV chip and the bottom TSV chip respectively, the electroplated top TSV chip and the electroplated bottom chip are inverted, finally balls are planted on the inverted chip, a middle channel process and a bumping process are adopted, a cavity structure with the built-in copper ring is formed on the basis of the middle channel process and the bumping process, the cavity structure with the built-in copper ring can achieve 3D vertical interconnection among the chips, the requirement of high air tightness is met, the chip packaging with high air tightness is achieved, and the packaging cost is low; through chip stacking, the interconnection density among chips is improved, the requirements of high integration and miniaturization can be met, and the chip type selection is more flexible.
Wherein, the TSV refers to a Through Silicon Vias, and the TSV chip refers to a chip penetrating Through the Through Silicon Vias. The middle process is a process that employs a processing link between wafer fabrication and packaging. The bumping process refers to a process for forming copper-tin or gold bumps on the surface of the wafer. At present, no method for realizing air-tightness packaging (namely, completing the air-tightness requirement before the packaging is completed) by adopting the middle process is available; the chip-level stacking based on the middle process has flexible chip type selection, and meanwhile, the cavity structure with the built-in copper ring is also suitable for MEMS (micro electro mechanical Systems, micro mechanical and electrical system chips).
Preferably, the number of the first circuit areas is the same as that of the second circuit areas, and all the first circuit areas correspond to all the second circuit areas one to one;
the number of the first copper rings is the same as that of the first circuit areas, and all the first copper rings correspond to all the first circuit areas one by one; the number of the second copper rings is the same as that of the second line areas, and all the second copper rings correspond to all the second line areas one to one.
The first circuit district of top TSV chip is the same with the second circuit district quantity of bottom chip, the quantity of first copper ring is the same with the quantity correspondence in first circuit district, the quantity of second copper ring is the same with the quantity correspondence in second circuit district, can be convenient for realize the electric intercommunication between top TSV chip and the bottom chip, form the cavity structure of built-in copper ring, and then be convenient for follow-up piling up the chip at the wafer level, high gas tightness encapsulation has been realized on the one hand, on the other hand can also realize batch production, the productivity of production line is improved.
Preferably, each first line region includes at least one through silicon via;
the number of the silicon through holes, the number of the first copper columns and the number of the second copper columns are the same, all the silicon through holes are in one-to-one correspondence with all the first copper columns, and all the second copper columns are in one-to-one correspondence with all the first copper columns.
Through the first copper columns in one-to-one correspondence with the silicon through holes and the second copper columns in one-to-one correspondence with the first copper columns, electrical communication between the top TSV chip and the bottom TSV chip can be achieved based on the TSV technology.
Specifically, each first circuit area further comprises a first circuit board, and each second circuit area comprises a second circuit board; the size of the cross section of the first circuit board is the same as the size of the cross section of the second circuit board.
The first circuit board and the second circuit board are uniformly provided with circuits, the specific circuit design is determined according to the actual design condition of the chip, and the circuits on each circuit board can be the same or different.
It should be noted that the specific number of the through silicon vias in each first circuit area and the size of each through silicon via are determined by the actual design of the chip. Usually, a plurality of through silicon vias are disposed in a first circuit region, and when a first circuit region is disposed on the top TSV chip and the first circuit region has a plurality of through silicon vias (e.g., 2 through silicon vias), a top view structure diagram of the top TSV chip is shown in fig. 2-1, and a cross-sectional view structure diagram of the top TSV chip is shown in fig. 2-2; when a plurality of first circuit regions (e.g., 3 first circuit regions) are disposed on the top TSV chip and each first circuit region has a plurality of through silicon vias (e.g., 2 through silicon vias), a top view structure diagram of the top TSV chip is shown in fig. 3-1, and a cross-sectional view structure diagram of the top TSV chip is shown in fig. 3-2.
In the present embodiment, a TSV wafer is used as a top TSV chip, and the TSV wafer shown in fig. 3-1 and fig. 3-2 is used as a top TSV chip for illustration.
Preferably, in S110, at least one first copper ring is respectively plated on the top TSV chip provided with at least one first line region, including:
and respectively electroplating corresponding first copper rings on the outer side of each first circuit area on the TSV chip at the top.
Through the first copper rings electroplated on the outer sides of the first circuit areas, each first circuit area can be located in the corresponding first copper ring, and therefore a cavity structure with better air tightness can be formed when the subsequent first copper rings and the second copper rings are welded.
Specifically, in S110, at least one first copper pillar is respectively plated on the top TSV chip provided with at least one first line region, including:
and respectively electroplating corresponding first copper columns at each through silicon hole on the top TSV chip, so that each first copper column is in contact with the corresponding through silicon hole.
The first copper column is electroplated at each silicon through hole, so that the top TSV chip and the bottom TSV chip can be electrically communicated on the basis of the TSV technology, and good electrical performance among the chips is guaranteed. The specific operation method of electroplating in S110 and S120 is the prior art, and the details are not described herein.
The top TSV chip after plating in this embodiment is shown in fig. 4.
Preferably, when the number of the first line areas is greater than 1, after S110, the method further includes:
and pre-cutting the electroplated top TSV chip according to a first preset scribing way on each first circuit area.
Through precutting, be convenient for separate into the single-chip of a plurality of built-in copper ring cavity structures with the structure that piles up on the wafer level, realize batch production, improve production line productivity.
The number of the first line regions of the top TSV chip shown in fig. 4 is greater than 1, and the top TSV chip is precut based on the top TSV chip shown in fig. 4, so that the obtained chip structure is shown in fig. 5, where 140 in fig. 5 is a first preset scribing lane and corresponds to the first line region.
Specifically, the width of each first preset scribing way ranges from 80 to 400 μm.
Specifically, the depth of each first preset scribing channel is greater than or equal to the depth of all through silicon vias.
When the pre-cutting is carried out according to the first preset scribing channel with the depth, all through-silicon vias can be exposed through grinding after the subsequent flip-chip is carried out conveniently.
In the present embodiment, a conventional wafer is used as the bottom chip, as shown in fig. 6.
Preferably, in S120, at least one second copper ring is respectively plated on the bottom chip provided with the at least one second line area, including:
and plating corresponding second copper rings outside each second circuit area on the bottom chip respectively.
The electroplating of the corresponding second copper ring outside each second circuit area is similar to the electroplating of the first copper ring on the top TSV chip, and details are not repeated here.
In S120, the specific electroplating method for electroplating the second copper pillar on the bottom TSV chip is the same as that for electroplating the first copper pillar on the top TSV chip.
It should be noted that, since the first copper ring is located outside the corresponding first circuit region in S110, all the through silicon vias and all the first copper pillars in contact with the through silicon vias in the first circuit region are located inside the corresponding first copper ring; in order to facilitate that all the subsequent second copper pillars correspond to all the first copper pillars one to one, when the first copper pillars are electroplated in S120, each second copper pillar needs to be electroplated on the inner side of the corresponding second copper ring, so as to realize the subsequent flip-chip.
The bottom chip after plating in this embodiment is shown in fig. 7.
Preferably, as shown in fig. 8, S130 includes:
s131: reversely buckling the electroplated top TSV chip on the electroplated bottom chip, so that all first copper columns on the top TSV chip are in one-to-one corresponding contact with all second copper columns on the bottom chip, and all first copper rings on the top TSV chip are in one-to-one corresponding contact with all second copper rings on the bottom chip;
s132: and welding each first copper column with each second copper column of the corresponding contact by adopting a welding flux, and welding each first copper ring with each second copper ring of the corresponding contact to form the flip chip.
Through the flip chip and welding process, the flip chip and the chip stacking are realized, and based on the flip chip technology and the chip stacking technology, at least one cavity structure with a built-in copper ring can be formed between the TSV chip at the top and the TSV chip at the bottom, so that the requirements of high air tightness and low cost are met, the integration level of the chip is effectively improved, and the miniaturization of the chip is realized; because the cavity structure of built-in copper ring can form a plurality ofly, and every cavity structure corresponds with first circuit district and second circuit district, consequently can realize batch production. In S131, the copper pillars are interconnected to realize electrical connection, and the copper rings are interconnected to reinforce the chip structure, so as to form an airtight ring.
Specifically, in the present embodiment, the solder is selected from solder with a melting point higher than 260 ℃, such as AuSn solder.
The flip chip formed in this embodiment is shown in fig. 9.
Preferably, as shown in fig. 10, S140 includes:
s141: grinding the top of the flip chip to expose all through silicon vias in the flip chip;
s142: and (4) respectively planting balls on each silicon through hole exposed out of the head to form an airtight chip structure.
Can make flip chip's top (the top TSV chip of flip-chip) attenuate through grinding, and then make every through-silicon via hole outcrop, be convenient for follow-up through planting the electric intercommunication that the ball realized between the chip, through the gas tightness chip structure that obtains after planting the ball, can reach the chip package requirement of high gas tightness, high integration. In addition, when the depth of each first preset scribing channel is greater than or equal to all the silicon through holes, the tops of the flip chips are ground to expose all the silicon through holes, and the tops of the flip chips can be separated from each first preset scribing channel, so that the subsequent batch production is realized.
Specifically, the solder balls implanted in S142 of this embodiment are low temperature solder balls of 220-245 ℃, such as lead Sn63Pb37, or lead-free SAC305 and SAC 105; the number of the solder balls is determined according to the actual chip design condition, wherein the number of the solder balls is more than or equal to the number of the through silicon vias.
Specifically, in this embodiment, the structure of the flip chip after the grinding in S141 is shown in fig. 11, and the structure of the flip chip after the ball mounting in S142 is shown in fig. 12.
Preferably, in S142, after the ball mounting is performed on each of the exposed through-silicon vias, the method further includes:
and carrying out secondary cutting on the bottom of the flip chip after ball mounting according to a second preset scribing channel on each second circuit area to form the airtight flip chip.
When the quantity in first circuit district was greater than 1, the quantity in the second circuit district that corresponds also was greater than 1, predetermines the scribing way according to the second on the second circuit district and carries out the secondary cutting, can be on flip chip's top separation's basis for flip chip's bottom also realizes separating, realizes the batch production of multicore piece.
The structure of the resulting hermetically sealed flip chip after the second division of this example is shown in fig. 13.
It should be noted that, when the number of the first circuit areas is 1, the number of the corresponding second circuit areas is also 1, at this time, it is not necessary to pre-divide the plated top TSV chip according to the first preset scribe lane, and it is also not necessary to perform secondary division on the bottom of the flip chip according to the second preset scribe lane, and the formed airtight flip chip is a single chip, and its structure is shown in fig. 14.
In each of the block diagrams shown in fig. 2-1, 2-2, 3-1, 3-2, 4, 5, 6, 7, 9, 11, 12, 13 and 14, each reference numeral refers in detail to the description of the figure.
Example two
As shown in fig. 13 and 14, the present embodiment provides an airtight chip structure, which is prepared by the preparation method of the first embodiment, and includes:
a bottom chip 200;
a top TSV chip 100 flip-chip mounted on the bottom chip 200; and
at least one solder ball 300 soldered on a side of the top TSV chip 100 facing away from the bottom chip 200;
at least one first circuit region 110 is disposed on the top TSV chip 100, and at least one first copper ring 120 and at least one first copper pillar 130 are plated on the side of the top TSV chip 100 facing the bottom chip 200;
the bottom chip 200 is provided with at least one second circuit region 210, and the side of the bottom chip 200 facing the top TSV chip 100 is plated with at least one second copper ring 220 and at least one second copper pillar 230.
The airtight chip structure forms a cavity structure with a built-in copper ring based on a middle process and a bumping process, the cavity structure with the built-in copper ring can realize 3D vertical interconnection among chips, the requirement of high airtightness is met, chip packaging with high airtightness is realized, and packaging cost is low; through chip stacking, the interconnection density among chips is improved, the requirements of high integration and miniaturization can be met, and the chip type selection is more flexible.
The top TSV chip of this embodiment is a TSV wafer, and the bottom chip is a conventional wafer.
Preferably, the number of the first line areas 110 is the same as that of the second line areas 210, and all the first line areas 110 correspond to all the second line areas 210 one to one;
the number of the first copper rings 120 is the same as that of the first circuit regions 110, and all the first copper rings 120 correspond to all the first circuit regions 110 one to one; the number of the second copper rings 220 is the same as that of the second circuit regions 210, and all the second copper rings 220 correspond to all the second circuit regions 210 one to one.
Preferably, as shown in fig. 13 and 14, each of the first line regions 110 includes at least one through silicon via 111;
the number of the through silicon vias 111, the number of the first copper pillars 130, and the number of the second copper pillars 230 are the same, all the through silicon vias 111 are electrically connected to all the first copper pillars 130 in a one-to-one correspondence, and all the second copper pillars 230 are electrically connected to all the first copper pillars 130 in a one-to-one correspondence.
Specifically, as shown in fig. 13 and 14, each first circuit area 110 further includes one first circuit board 112, and each second circuit area 210 is specifically one second circuit board; the size of the cross section of the first wiring board 112 is the same as the size of the cross section of the second wiring board.
Preferably, each first copper ring 120 is located outside of a corresponding first line region 110 on the top TSV chip 100, and each second copper ring 220 is located outside of a corresponding second line region 210 on the bottom chip 200.
Preferably, each first copper pillar 130 is soldered to the corresponding second copper pillar 230 by solder 400, and each first copper ring 120 is soldered to the corresponding second copper ring 220 by solder 400.
The hermetic chip structure described in this embodiment is prepared by the preparation method described in the first embodiment, details of which are not described in detail in the first embodiment and detailed descriptions of fig. 1 to 14 are omitted here.
It is to be understood that the above-described embodiments are only a few, and not all, embodiments of the present invention. Based on the embodiments of the present invention, those skilled in the art may make other variations or modifications without creative efforts, and shall fall within the protection scope of the present invention.
Claims (10)
1. A method for fabricating a hermetic chip structure, comprising:
respectively electroplating at least one first copper ring and at least one first copper column on a top TSV chip provided with at least one first circuit area;
respectively electroplating at least one second copper ring and at least one second copper column on the bottom chip provided with at least one second circuit area;
inversely installing the electroplated top TSV chip on the electroplated bottom chip to form an inverted chip;
and planting balls on the top of the flip chip to form an airtight chip structure.
2. The method of claim 1, wherein the number of the first circuit areas is the same as the number of the second circuit areas, and all the first circuit areas correspond to all the second circuit areas one-to-one;
the number of the first copper rings is the same as that of the first circuit areas, and all the first copper rings correspond to all the first circuit areas one by one; the number of the second copper rings is the same as that of the second line areas, and all the second copper rings correspond to all the second line areas one by one;
at least one first copper ring is electroplated on the top TSV chip provided with at least one first circuit area respectively, and the method comprises the following steps:
plating the corresponding first copper rings on the outer side of each first circuit area on the top TSV chip respectively;
at least one second copper ring is electroplated on the bottom chip provided with at least one second circuit area respectively, including:
and electroplating corresponding second copper rings outside each second circuit area on the bottom chip respectively.
3. The method of fabricating a hermetic chip structure according to claim 2, wherein each of the first circuit regions comprises at least one through-silicon-via;
the number of the through silicon vias, the number of the first copper pillars and the number of the second copper pillars are the same, all the through silicon vias correspond to all the first copper pillars one to one, and all the second copper pillars correspond to all the first copper pillars one to one;
the top TSV chip after being electroplated is inversely arranged on the bottom TSV chip after being electroplated to form an inverted chip, and the inverted chip comprises:
reversely buckling the electroplated top TSV chip on the electroplated bottom chip so that all the first copper columns on the top TSV chip are in one-to-one corresponding contact with all the second copper columns on the bottom chip, and all the first copper rings on the top TSV chip are in one-to-one corresponding contact with all the second copper rings on the bottom chip;
and welding each first copper column and each second copper column which is correspondingly contacted with the first copper column by adopting a welding material, and welding each first copper ring and each second copper ring which is correspondingly contacted with the first copper column to form the flip chip.
4. The method for fabricating the hermetic chip structure according to claim 3, wherein the plating of the at least one first copper pillar on the top TSV chip having the at least one first circuit region, respectively, comprises:
and respectively electroplating corresponding first copper columns at each through silicon hole on the top TSV chip, so that each first copper column is in contact with the corresponding through silicon hole.
5. The method for fabricating the hermetic chip structure according to claim 3, wherein the ball-mounting on the top of the flip chip to form the hermetic chip structure comprises:
grinding the top of the flip chip to expose all the through silicon vias in the flip chip;
and respectively planting balls on each silicon through hole exposed out of the head to form the airtight chip structure.
6. The method for manufacturing the hermetic chip structure according to claim 5, wherein when the number of the first circuit regions is greater than 1, after the plating of the at least one first copper ring and the at least one first copper pillar on the top TSV chip provided with the at least one first circuit region, respectively, the method further comprises:
and pre-cutting the electroplated top TSV chip according to a first preset scribing way on each first circuit area.
7. The method of claim 6, wherein the depth of each of the first pre-scribe streets is greater than or equal to the depth of all of the through silicon vias.
8. The method of claim 7, further comprising, after the ball-mounting on each of the exposed through-silicon vias, respectively:
and carrying out secondary cutting on the bottom of the flip chip after ball mounting according to a second preset scribing channel on each second circuit area to form the airtight flip chip.
9. The method for fabricating the hermetic chip structure according to any one of claims 1 to 8, wherein before the step of respectively plating at least one first copper ring and at least one first copper pillar on the top TSV chip provided with the at least one first circuit region, the method further comprises:
respectively etching at least one first circuit area on a first wafer substrate to form the top TSV chip;
before at least one second copper ring and at least one second copper post are electroplated on the bottom chip provided with at least one second circuit area respectively, still include:
and etching at least one second circuit area on a second wafer substrate to form the bottom chip.
10. A hermetic chip structure prepared by the method of any one of claims 1 to 9, comprising:
a bottom chip (200);
a top TSV chip (100) flip-chip mounted on the bottom chip (200); and
at least one solder ball (300) soldered on a side of the top TSV chip (100) facing away from the bottom chip (200);
wherein at least one first circuit area (101) is arranged on the top TSV chip (100), and the side surface of the top TSV chip (100) facing the bottom chip (200) is plated with at least one first copper ring (102) and at least one first copper pillar (103);
at least one second circuit area (201) is arranged on the bottom chip (200), and at least one second copper ring (202) and at least one second copper column (203) are plated on the side surface of the bottom chip (200) facing the top TSV chip (100).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210272027.0A CN114725011A (en) | 2022-03-18 | 2022-03-18 | Air-tight chip structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210272027.0A CN114725011A (en) | 2022-03-18 | 2022-03-18 | Air-tight chip structure and preparation method thereof |
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|---|---|---|---|---|
| US20020056897A1 (en) * | 1999-06-02 | 2002-05-16 | Hiromi Yatsuda | Electronic component to be mounted on a circuit board having electronic circuit device sealed therein and method of manufacturing the same |
| US20060097335A1 (en) * | 2004-11-08 | 2006-05-11 | Deok-Hoon Kim | Electronic package for image sensor, and the packaging method thereof |
| US20070114620A1 (en) * | 2005-11-24 | 2007-05-24 | Mitsubishi Electric Corporation | Package and electronic apparatus using the same |
| US20090218669A1 (en) * | 2008-03-03 | 2009-09-03 | Advanced Semiconductor Engineering, Inc. | Multi-chip package structure and method of fabricating the same |
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