KR20010068512A - Chip scale stack package and manufacturing method thereof - Google Patents
Chip scale stack package and manufacturing method thereof Download PDFInfo
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
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Abstract
Description
본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 용량과 실장밀도의 향상을 위하여 복수의 반도체 칩이 내재되어 단일 패키지로 구성되는 칩 스케일(chip scale) 적층 패키지와 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package. More particularly, the present invention relates to a chip scale stacked package in which a plurality of semiconductor chips are embedded and configured as a single package for improving capacity and mounting density.
반도체 소자와 그에 대한 패키지 기술은 상호 부합되어 고밀도화, 고속도화, 소형화 및 박형화를 목표로 계속적인 발전을 거듭해 왔다. 패키지 구조에 있어서 핀 삽입형에서 표면실장형으로 급격히 진행되어 회로기판에 대한 실장밀도를 높여 왔으며, 최근에는 베어 칩(bare chip)의 특성을 그대로 패키지 상태에서 유지하면서도 취급이 용이하고 패키지 크기가 크게 줄어든 칩 크기 패키지(CSP; Chip Scale Package)가 여러 제조 회사에서 개발되어 있으며 계속적인 연구가 활발히 진행되고 있다. 또한, 용량과 실장밀도의 증가를 위하여 여러 개의 단위 반도체 소자 또는 단위 반도체 칩 패키지를 적층시킨 형태의 3차원 적층 기술도 주목을 받게 되었다. 3차원 적층 기술이 적용되는 대표적인 예가 적층 칩 패키지와 적층 패키지이다.Semiconductor devices and their packaging technologies have been matched to each other and have continued to develop with the goal of increasing density, high speed, miniaturization and thinning. The package structure has been rapidly advanced from the pin insertion type to the surface mount type, thereby increasing the mounting density of the circuit board. In recent years, the bare chip characteristics have been kept in the package state, while being easily handled and the package size has been greatly reduced. Chip Scale Packages (CSPs) have been developed by several manufacturing companies and are being actively researched. In addition, three-dimensional stacking technology in which a plurality of unit semiconductor devices or unit semiconductor chip packages are stacked in order to increase capacity and mounting density has also attracted attention. Representative examples of the three-dimensional lamination technology are laminated chip packages and stacked packages.
적층 칩 패키지는 패키징(packaging)되지 않은 반도체 소자가 여러 개 적층되어 단일 패키지로 구성되고, 적층 패키지는 개별적으로 조립공정이 완료된 단위 반도체 칩 패키지를 여러 개 적층하여 구성된다. 적층 칩 패키지의 예가 도 1에 도시되어 있고 적층 패키지의 예가 도 2에 도시되어 있다.The stacked chip package is formed by stacking a plurality of unpacked semiconductor devices into a single package, and the stacked package is formed by stacking several unit semiconductor chip packages in which an assembly process is completed. An example of a stacked chip package is shown in FIG. 1 and an example of a stacked package is shown in FIG.
도 1은 일반적인 적층 칩 패키지의 일 예를 나타낸 단면도이다.1 is a cross-sectional view illustrating an example of a general multilayer chip package.
도 1을 참조하면, 적층 칩 패키지(100)는 두 개의 반도체 칩(111,113)이 다이패드(115)의 밑면과 윗면에 접착수단(118,119)으로 각각 부착되고, 와이어 본딩(wire bonding)에 의해 전극패드(112,114)가 리드(116)의 내측 말단부의 밑면과 윗면에 도전성 금속선(117)으로 접합되어 전기적인 연결을 이루며, 외부환경으로부터의 보호를 위하여 에폭시 성형 수지(Epoxy Molding Compound)와 같은 플라스틱 봉지재로 봉지부(120)가 형성되는 구조이다.Referring to FIG. 1, in the stacked chip package 100, two semiconductor chips 111 and 113 are attached to the bottom and top surfaces of the die pad 115 by adhesive means 118 and 119, respectively, and the electrodes are formed by wire bonding. The pads 112 and 114 are bonded to the bottom and top of the inner end of the lid 116 by a conductive metal wire 117 to form an electrical connection. The encapsulation portion 120 is formed of ash.
도 2는 일반적인 적층 패키지의 일 예를 나타낸 단면도이다.2 is a cross-sectional view showing an example of a typical laminated package.
도 2를 참조하면, 이 적층 패키지(150)는 도 2에 도시된 바와 같이 단위 반도체 칩 패키지(151)가 적어도 2개 이상 수직으로 적층되어 각 단위 반도체 칩 패키지(151)들의 외부리드(157)가 서로 접합되어 전기적인 연결을 이루고 있는 구조이다. 각 단위 반도체 칩 패키지(151)들의 구조는 일반적인 리드프레임의 내부리드(155)에 반도체 칩(153)이 실장되고, 그 반도체 칩(153)의 전극패드(도시 안됨)와 내부리드(155)가 도전성 금속선(159)으로 와이어 본딩되어 전기적 접속을 이루며, 반도체 칩(153)을 포함하여 전기적인 접합 부위가 수지 봉지재로 형성된 봉지부(161)에 의해 봉지되어 있는 구조이다.Referring to FIG. 2, as shown in FIG. 2, at least two unit semiconductor chip packages 151 are stacked vertically as shown in FIG. 2, so that the external leads 157 of the unit semiconductor chip packages 151 are stacked. Are bonded to each other to form an electrical connection. Each unit semiconductor chip package 151 has a structure in which a semiconductor chip 153 is mounted on an inner lead 155 of a general lead frame, and an electrode pad (not shown) and an inner lead 155 of the semiconductor chip 153 are mounted. The wire is bonded to the conductive metal wire 159 to make an electrical connection, and the electrical bonding portion including the semiconductor chip 153 is sealed by the encapsulation portion 161 formed of a resin encapsulant.
그러나, 위에 소개한 것과 같은 구조를 갖는 종래의 반도체 칩 패키지들은 소형화와 박형화 및 경량화에 한계가 있다. 최근에 소위 칩 스케일 패키지(CSP; Chip Scale Package)라 불리는 단일 칩으로 구성되며 칩 수준의 크기를 갖는 형태의 반도체 칩 패키지가 개발되고 있는 실정에 있어서, 이에 대응할 수 있는 기술이요구되고 있는 실정이다. 즉, 크기가 작고 경량이면서 용량 및 실장밀도를 향상을 만족시킬 수 있는 새로운 형태의 패키지 조립 기술이 요구되고 있다.However, conventional semiconductor chip packages having a structure as described above have limitations in miniaturization, thinness, and light weight. Recently, in the development of a semiconductor chip package having a chip-level size, which is composed of a single chip called a chip scale package (CSP), a technology capable of coping with this is required. . In other words, there is a need for a new type of package assembly technology capable of satisfying small size, light weight, and improved capacity and mounting density.
본 발명의 목적은 웨이퍼 차원에서 조립이 완료되는 적층 패키지와 그 제조 방법을 제공하여 칩 수준의 크기를 가지면서 용량 및 실장밀도를 향상시킬 수 있도록 하는 데에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated package and a method of manufacturing the same, which are completed at the wafer level, to improve capacity and mounting density while having a chip-level size.
도 1은 일반적인 적층 칩 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a general stacked chip package;
도 2는 일반적인 적층 패키지의 일 예를 나타낸 단면도,Figure 2 is a cross-sectional view showing an example of a typical laminated package,
도 3은 본 발명에 따른 칩 스케일 적층 패키지의 일 실시예를 나타낸 단면도,3 is a cross-sectional view showing an embodiment of a chip scale stack package according to the present invention;
도 4a내지 도 11은 본 발명에 따른 칩 스케일 적층 패키지 제조 방법의 공정에 따른 단면도이다.4A to 11 are cross-sectional views of processes of a chip scale stack package manufacturing method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 웨이퍼 11; 반도체 칩10; Wafer 11; Semiconductor chip
13; 본딩패드 15; 스크라이브 영역(scribe lane)13; Bonding pads 15; Scribe lane
17; 소잉 영역(sawing lane) 19; 콘택 홀(contact hole)17; Sawing lane 19; Contact hole
21; 금속기둥(metal post)21; Metal post
23; 탭 테이프(Tape Automated Bonding tape)23; Tape Automated Bonding tape
25; 금속배선 27; 빔 리드(beam lead)25; Metallization 27; Beam lead
29; 탄성중합체(elastomer) 31,33; 봉지부29; Elastomer 31,33; Encapsulation
35; 범프(bump) 37; 접착 테이프35; Bump 37; Adhesive tape
39; 솔더 볼(solder ball) 50; 칩 스케일 적층 패키지39; Solder ball 50; Chip Scale Stacking Package
이와 같은 목적을 달성하기 위한 본 발명에 따른 칩 스케일 적층 패키지는, 집적회로가 형성된 활성면에 복수의 본딩패드가 형성되어 있고 회로 영역의 외측 가장자리를 관통하는 금속기둥(metal post)이 형성되어 있는 반도체 칩, 반도체 칩의 활성면에 부착되어 있고 본딩패드와 금속기둥에 각각 빔 리드가 접합되어 있는 탭 테이프를 포함하는 탭 테이프가 부착된 단위 반도체 칩을 일개소 단위로 하여 활성면의 반대면이 부착되도록 두 개의 반도체 칩이 부착되어 있고, 각 반도체 칩의 금속기둥이 전기적으로 연결되어 있는 것을 특징으로 한다.In the chip scale stack package according to the present invention for achieving the above object, a plurality of bonding pads are formed on the active surface in which the integrated circuit is formed and a metal post penetrating the outer edge of the circuit area is formed. The opposite side of the active surface is a unit of a semiconductor chip having a tab tape attached to the semiconductor chip and the active surface of the semiconductor chip, the tab tape including a tap tape bonded to a bonding pad and a metal pillar, respectively. Two semiconductor chips are attached to each other so that the metal pillars of each semiconductor chip are electrically connected to each other.
바람직하게는 반도체 칩들은 센터패드(center pad)형으로 하여 탭 테이프(Tape Automated Bonding)의 빔 리드(beam lead)와 접합이 용이하게 이루어지도록 하고, 빔 리드 및 그 접합 부위는 성형 수지로 봉지부를 형성하여 외부환경으로부터 보호되도록 한다. 또한, 반도체 칩들의 금속기둥은 범프로 접합되도록 하여 전기적으로 연결되도록 하고, 반도체 칩들 중에서 적어도 어느 하나의 탭 테이프에 외부 접속 단자로서 솔더 볼이 부착되도록 한다.Preferably, the semiconductor chips have a center pad shape so that the semiconductor chips can be easily bonded to the beam leads of the tape automated bonding, and the beam leads and the bonding portions are encapsulated with a molding resin. To protect from the external environment. In addition, the metal pillars of the semiconductor chips are bonded to the bumps to be electrically connected, and the solder balls are attached to the tab tape of at least one of the semiconductor chips as external connection terminals.
또한 상기 목적을 달성하기 위한 본 발명에 따른 칩 스케일 적층 패키지 제조 방법은, ⒜ 복수의 반도체 칩을 포함하는 웨이퍼의 스크라이브 영역(scribe lane) 내의 소잉 영역(sawing lane) 외측에 집적회로와 본딩패드가 형성된 활성면으로부터 소정 깊이로 콘택 홀(contact hole)을 형성하고, 그 콘택 홀에 금속기둥을 형성하는 단계, ⒝ 빔 리드가 형성된 탭 테이프를 각 반도체 칩의 활성면에 부착하고 빔 리드를 그에 대응되는 본딩패드와 금속기둥에 각각 접합시키는 단계, ⒞ 빔 리드 및 그 접합 부분을 봉지하는 단계, ⒟ 금속기둥이 노출되도록 웨이퍼의 뒷면을 일정 두께만큼 제거하는 단계, ⒠ 웨이퍼 뒷면에 노출된 금속기둥 상에 범프를 형성하는 단계, ⒡ 각 웨이퍼의 뒷면에 노출되는 금속기둥이 범프로 접합되도록 하여 두 장의 웨이퍼를 서로 부착시키는 단계, ⒢ 적어도 어느 하나의 웨이퍼에 부착된 탭 테이프에 외부 접속 수단을 형성하는 단계, 및 ⒣ 소잉 영역을 절단하여 단위 적층 패키지로 분리하는 단계를 포함하는 것을 특징으로 한다. 바람직하게는 ⒡ 단계의 적어도 어느 하나의 웨이퍼는 상기 ⒠ 단계 후에 웨이퍼 뒷면에 범프를 피하여 접착층을 형성하는 단계를 더 진행한 것으로 한다.In addition, the chip scale stack package manufacturing method according to the present invention for achieving the above object, the integrated circuit and the bonding pad outside the sawing lane (sawing lane) in the scribe lane of the wafer containing a plurality of semiconductor chips Forming a contact hole to a predetermined depth from the formed active surface, and forming a metal pillar in the contact hole, attaching a tab tape having a beam lead formed to the active surface of each semiconductor chip, and Bonding each of the bonding pads and metal pillars to each other, (b) encapsulating the beam lead and the joint portion thereof, (b) removing the backside of the wafer to a certain thickness so that the metal pillars are exposed, (b) the metal pillars exposed on the backside of the wafer Forming bumps on the wafer, whereby two wafers are attached to each other so that the metal pillars exposed on the back side of each wafer are bonded to the bumps. And (b) forming external connection means in the tab tape attached to the at least one wafer, and cutting the sawing region into separate unit stack packages. Preferably, at least one of the wafers in the thinning step is further processed to form an adhesive layer by avoiding bumps on the back surface of the wafer after the thinning step.
이하 첨부 도면을 참조하여 본 발명에 따른 적층 패키지와 그 제조 방법을 보다 상세하게 설명하고자 한다.Hereinafter, a laminate package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 칩 스케일 적층 패키지의 일 실시예를 나타낸 단면도이다.3 is a cross-sectional view showing an embodiment of a chip scale stack package according to the present invention.
도 3을 참조하면, 본 발명에 따른 실시예로서의 이 적층 패키지(50)는 가장자리를 관통하는 금속기둥(21)이 형성되어 있는 두 개의 반도체 칩(11a,11b)이 집적회로가 형성된 활성면의 반대면이 접착 테이프(37)에 의해 서로 부착되어 있으며 금속기둥(21)이 범프(35)에 의해 접합되어 있는 구조를 갖는다. 이때, 각각의 반도체 칩(11a,11b)의 활성면에 빔 리드(27)를 갖는 탭 테이프(23)가 부착되어 반도체 칩(11)의 본딩패드(13)와 금속기둥(21)이 탭 테이프(23)의 빔 리드(27)와 접합되어 있다. 그리고, 하부의 반도체 칩(10b)에 부착된 탭 테이프(23)에 외부 접속 단자로서 솔더 볼(39)이 부착되어 있다.Referring to FIG. 3, the stacked package 50 according to the embodiment of the present invention has two semiconductor chips 11a and 11b having metal pillars 21 penetrating their edges opposite to active surfaces on which integrated circuits are formed. The surfaces are attached to each other by the adhesive tape 37 and the metal columns 21 are joined by the bumps 35. At this time, the tab tape 23 having the beam leads 27 is attached to the active surfaces of the semiconductor chips 11a and 11b so that the bonding pads 13 and the metal columns 21 of the semiconductor chips 11 are tab tapes. It is joined to the beam lead 27 of (23). The solder ball 39 is attached to the tab tape 23 attached to the lower semiconductor chip 10b as an external connection terminal.
여기서, 각각의 반도체 칩(11a,11b)은 활성면의 중앙부에 본딩패드(13)가 배치되어 있는 센터패드형으로서 밑면으로부터 소정 두께가 연마되어 일반적인 반도체 칩보다 얇은 두께를 갖는다. 그리고, 반도체 칩(11a,111b)의 활성면에 탄성중합체(elastomer)로 부착되는 탭 테이프(23)는 내부에 금속배선(25)이 형성되어 있으며 외부로 빔 리드(27)가 노출되는 구조를 갖는다.Here, each of the semiconductor chips 11a and 11b is a center pad type in which the bonding pads 13 are disposed at the center of the active surface, and a predetermined thickness is polished from the bottom to have a thickness thinner than that of a general semiconductor chip. In addition, the tab tape 23 attached to the active surfaces of the semiconductor chips 11a and 111b as an elastomer has a structure in which a metal wiring 25 is formed inside and the beam lead 27 is exposed to the outside. Have
각각의 반도체 칩(11a,11b)은 집적회로가 형성된 영역의 외측에서 그 반도체 칩(10a,10b)을 관통하도록 전기전도성이 우수한 금속으로 금속기둥(21)이 형성된다. 탭 테이프(23)의 빔 리드(27)와 금속배선(25)에 의해 반도체 칩(11a,11b)의 본딩패드(13)가 금속기둥(21)과 전기적으로 연결되고, 이 금속기둥(21)이 범프(35)에 의해 접합되어 반도체 칩(11a,11b)간의 전기적인 연결이 이루어진다. 최종적으로 반도체 칩들(10a,10b)은 하부에 위치한 반도체 칩(11b)의 탭 테이프(23)에 부착된 솔더 볼(39)과 전기적으로 연결된다.Each of the semiconductor chips 11a and 11b is formed of a metal pillar 21 made of a metal having excellent electrical conductivity so as to penetrate the semiconductor chips 10a and 10b outside the region where the integrated circuit is formed. The bonding pads 13 of the semiconductor chips 11a and 11b are electrically connected to the metal pillars 21 by the beam leads 27 and the metal wires 25 of the tab tape 23. The bumps 35 are bonded to each other to make electrical connections between the semiconductor chips 11a and 11b. Finally, the semiconductor chips 10a and 10b are electrically connected to the solder balls 39 attached to the tab tape 23 of the semiconductor chip 11b located below.
한편, 이 적층 패키지(50)는 빔 리드(27)와 그 접합 부위가 에폭시 성형 수지 재질로 형성되는 봉지부(31,33)에 의해 봉지되어 외부환경으로부터 보호되고,각 반도체 칩(11a,11b)의 활성면은 그에 부착된 탭 테이프(23)에 의해 보호된다.On the other hand, the laminated package 50 is sealed by the encapsulation portions 31 and 33 formed of the epoxy molding resin material with the beam lead 27 and its bonding portion protected from the external environment, and each semiconductor chip 11a and 11b. Active surface is protected by a tab tape 23 attached thereto.
이와 같은 구조의 칩 스케일 적층 패키지는, 뒷면이 소정 두께만큼 연마된 두 개의 반도체 칩을 이용하고, 반도체 칩간의 전기적인 연결에 있어서 칩 가장자리를 관통하는 금속기둥을 이용하며, 이 금속기둥과 반도체 칩의 전기적인 연결에 탭 테이프를 이용하고, 반도체 칩의 활성면에 부착된 탭 테이프가 외부환경으로부터 보호되도록 하고 있다. 이에 의해 패키지 두께는 일반적인 반도체 칩의 두께보다 얇아진 두 개의 반도체 칩과 탭 테이프 및 부착에 사용된 접착 테이프와 솔더 볼 두께를 합한 정도가 된다. 그리고, 패키지 크기는 반도체 칩들간의 전기적인 연결에 금속기둥을 이용하고 있기 때문에 반도체 칩의 크기를 벗어나지 않는다. 따라서, 용량이 두 배이면서 전체적인 패키지 두께와 크기가 칩 수준으로 유지된다. 그리고, 본 발명의 칩 스케일 적층 패키지는 웨이퍼 상태에서 조립이 완료될 수 있다. 제조 공정을 설명하기로 한다.The chip scale stack package having such a structure uses two semiconductor chips whose back surface is polished to a predetermined thickness, and uses metal pillars penetrating the chip edges in electrical connection between the semiconductor chips. The tap tape is used for the electrical connection of the chip, and the tap tape attached to the active surface of the semiconductor chip is protected from the external environment. As a result, the package thickness is the sum of the thicknesses of the two semiconductor chips, the tab tape and the adhesive tape and the solder ball used for attachment, which are thinner than those of the general semiconductor chip. The package size does not exceed the size of the semiconductor chip because the metal pillar is used for the electrical connection between the semiconductor chips. Thus, while doubling capacity, the overall package thickness and size is maintained at the chip level. And, the chip scale stack package of the present invention can be completed assembly in the wafer state. The manufacturing process will be described.
도 4a내지 도 11은 본 발명에 따른 칩 스케일 적층 패키지 제조 방법의 공정에 따른 단면도이다.4A to 11 are cross-sectional views of processes of a chip scale stack package manufacturing method according to the present invention.
도 4a 내지 도 5b를 참조하면, 먼저 도 4a와 도 4b에 도시된 것과 같이 각각의 반도체 칩(11)에 본딩패드(13)의 형성이 완료된 웨이퍼(10)의 스크라이브 영역(15)에 콘택 홀(contact hole; 19)이 형성되고 그 콘택 홀(19)에 도 5a와 도 5b에 도시된 것과 같이 금속기둥(21)이 형성된다. 스크라이브 영역(15)은 웨이퍼(10)를 단위 반도체 칩(11)으로 분리할 때 절단하기 위해 마련되는 영역이다. 본 발명에 적용되는 웨이퍼(10)는 스크라이브 영역(15)이 일반적인 웨이퍼의스크라이브 영역보다 넓게 형성되어 있는 특징이 있다. 이에 따라, 실제로 절단되는 지점은 스크라이브 영역(15)의 한 가운데 부분이며, 이 부분을 소잉 영역(17)이라 하기로 한다. 콘택 홀(19)은 스크라이브 영역(15) 내의 소잉 영역(17)의 외측에 활성면으로부터 소정 깊이로 형성된다. 그리고, 콘택 홀(19)에 전기 전도성이 우수한 금속이 들어차 도 5a와 도 5b에서와 같이 금속기둥(21)이 형성된다. 이때, 웨이퍼(10)는 각 반도체 칩(11)이 집적회로가 형성된 활성면의 중앙부에 본딩패드가 배치되어 있는 것이다.Referring to FIGS. 4A through 5B, first, as shown in FIGS. 4A and 4B, contact holes are formed in the scribe region 15 of the wafer 10 in which the bonding pads 13 are formed on the respective semiconductor chips 11. (contact hole; 19) is formed, and metal pillars 21 are formed in the contact holes 19, as shown in Figs. 5A and 5B. The scribe area 15 is an area provided for cutting when the wafer 10 is separated into the unit semiconductor chip 11. The wafer 10 applied to the present invention is characterized in that the scribe region 15 is formed wider than the scribe region of a general wafer. Accordingly, the point actually cut is the middle portion of the scribe region 15, which will be referred to as sawing region 17. The contact hole 19 is formed outside the sawing area 17 in the scribe area 15 to a predetermined depth from the active surface. In addition, a metal pillar 21 is formed in the contact hole 19 as shown in FIGS. 5A and 5B. In this case, in the wafer 10, bonding pads are disposed at the center of an active surface where each semiconductor chip 11 is formed of an integrated circuit.
도 6을 참조하면, 다음에 도 6에 도시된 것과 같이 탭 테이프(23)가 반도체 칩(11)의 활성면에 부착되고 탭 테이프(23)의 빔 리드(27)가 본딩패드(13)와 금속기둥(21)에 각각 본딩된다. 탭 테이프(23)는 웨이퍼(10)의 구경 및 반도체 칩의 크기에 맞도록 금속배선(25)이 디자인 된 것으로서, 식각(etching) 공정 및 펀칭(punching) 공정에 의해 반도체 칩(11)의 중앙부에 배치되는 본딩패드(13)와 스크라이브 영역(15)에 형성되는 금속기둥(21)의 위치에 빔 리드(27)가 형성되며, 본딩패드(13)와 금속기둥(21)이 동일한 금속배선(25)으로 연결되어 있는 것이다.Referring to FIG. 6, the tab tape 23 is attached to the active surface of the semiconductor chip 11 as shown in FIG. 6, and the beam lead 27 of the tab tape 23 is bonded to the bonding pad 13. Bonded to the metal pillars 21, respectively. The tab tape 23 is a metal wiring 25 designed to fit the diameter of the wafer 10 and the size of the semiconductor chip. The tab tape 23 is formed at the center of the semiconductor chip 11 by an etching process and a punching process. The beam lead 27 is formed at the position of the bonding pad 13 and the metal pillar 21 formed in the scribing region 15, and the metal wires having the same bonding pad 13 and the metal pillar 21 ( 25).
이와 같은 탭 테이프(23)가 웨이퍼(10)에 탄성중합체(29)에 의해 반도체 칩(11)의 활성면에 부착되고, 빔 리드(27)와 본딩패드(13), 빔 리드(23)와 금속기둥(21)이 갱 본딩(gang bonding)법에 의해 한꺼번에 본딩된다. 탄성중합체(29)는 용이한 부착을 위하여 탭 테이프(23)의 일면에 미리 부착되어 있는 상태로 취급된다.The tab tape 23 is attached to the active surface of the semiconductor chip 11 by the elastomer 29 on the wafer 10, and the beam lead 27, the bonding pad 13, and the beam lead 23 are attached to the wafer 10. The metal columns 21 are bonded at one time by a gang bonding method. The elastomer 29 is handled in a state of being previously attached to one surface of the tab tape 23 for easy attachment.
도 7을 참조하면, 탭 테이프(23)의 부착이 완료되면 도 7에 도시된 것과 같이 빔 리드(27) 및 그 접합 부위가 성형 수지로 형성되는 봉지부(31,33)에 의해 봉지된다. 이때 사용되는 성형 수지는 에폭시 성형 수지(epoxy molding compound) 등이 사용될 수 있다. 이에 따라, 빔 리드(27)와 그 접합 부위가 봉지부(31,33)에 의해 외부 환경으로부터 보호된다. 한편, 반도체 칩(11)의 활성면은 탭 테이프(23)에 의해 보호된다.Referring to FIG. 7, when the attachment of the tab tape 23 is completed, as shown in FIG. 7, the beam lead 27 and the bonding portion thereof are sealed by the sealing parts 31 and 33 formed of a molding resin. In this case, the molding resin used may be an epoxy molding compound or the like. As a result, the beam lead 27 and its joint portion are protected from the external environment by the sealing portions 31 and 33. On the other hand, the active surface of the semiconductor chip 11 is protected by the tab tape 23.
도 8을 참조하면, 빔 리드(27)의 접합 부위에 대한 봉지가 완료되면 도 8에 도시된 것과 같이 활성면의 반대면인 웨이퍼(10)의 뒷면은 금속기둥(21)이 노출되도록 일정 두께가 제거된다. 일반적인 그라인딩(grinding) 설비를 이용하여 스크라이브 영역(15)에 형성된 금속기둥(21)이 드러날 때까지 연마하면 웨이퍼(10) 뒷면이 제거될 수 있다. 이 상태에서 소잉 영역(17)이 절단되어 단위 반도체 칩 패키지로 이용될 수도 있다. 그리고, 적층 패키지의 제조를 위하여 이 공정까지 완료된 상태의 웨이퍼가 필요하며, 다른 한 장의 웨이퍼에 대하여 이하 공정이 계속 진행된다.Referring to FIG. 8, when the sealing of the junction of the beam lead 27 is completed, the back surface of the wafer 10, which is the opposite surface of the active surface as shown in FIG. 8, has a predetermined thickness such that the metal pillars 21 are exposed. Is removed. The back surface of the wafer 10 may be removed by grinding until the metal pillars 21 formed in the scribe region 15 are exposed using a general grinding facility. In this state, the sawing region 17 may be cut and used as the unit semiconductor chip package. In order to manufacture the laminated package, a wafer having been completed up to this step is required, and the following process is continued for another wafer.
도 9를 참조하면, 다음으로 도 9에 도시된 것과 같이 웨이퍼(10) 뒷면에 노출된 금속기둥(21)에 범프(35)가 형성되고, 범프(35)의 안쪽 영역에 적층을 위한 접착 수단으로서 접착 테이프(37)가 부착된다. 범프(35)는 금 및 솔더 등 다양한 재질로 형성될 수 있으며 여러 형태로 형성될 수 있다. 여기에서는 솔더 재질이며 볼 형태의 범프(35)를 이용하고 있다. 그리고, 접착 테이프(37) 대신에 접착제가 사용될 수도 있다.Referring to FIG. 9, bumps 35 may be formed on the metal pillars 21 exposed on the back surface of the wafer 10, as shown in FIG. 9, and adhesive means for lamination on the inner regions of the bumps 35. As an adhesive tape 37 is attached. The bump 35 may be formed of various materials such as gold and solder, and may be formed in various forms. Here, the bump material 35 of the solder material is used. And instead of the adhesive tape 37, an adhesive may be used.
도 10을 참조하면, 범프(35)의 형성과 접착 테이프(37)의 부착이 완료되면도 8에 도시된 것과 같은 상태의 웨이퍼와 도 9에 도시된 것과 같은 상태의 웨이퍼를 위치 정렬한 상태에서 압착하여 각각의 금속기둥(21)이 범프(35)로 접합되도록 하여 한 쌍의 웨이퍼(10)들의 뒷면이 서로 부착된다. 이에 의해 반도체 칩(11)들간의 전기적인 연결이 가능해진다.Referring to FIG. 10, when the formation of the bump 35 and the attachment of the adhesive tape 37 are completed, the wafer in the state as shown in FIG. 8 and the wafer in the state as shown in FIG. 9 are aligned with each other. The back side of the pair of wafers 10 are attached to each other by pressing each metal column 21 to be bonded to the bump 35. This enables electrical connection between the semiconductor chips 11.
도 11을 참조하면, 한 쌍의 웨이퍼(10)의 부착이 완료되면 도 11에 도시된 것과 같이 하부에 위치한 웨이퍼(10)에 부착된 탭 테이프(23)에 외부 접속 수단으로서 솔더 볼(39)이 부착되고, 이 상태에서 한 쌍의 웨이퍼(10)가 한꺼번에 소잉 영역(17)이 절단되어 단위 적층 패키지로 분리된다.Referring to FIG. 11, when the attachment of the pair of wafers 10 is completed, the solder balls 39 are used as external connection means to the tab tape 23 attached to the wafer 10 located below, as shown in FIG. 11. In this state, the pair of wafers 10 are cut at once and the sawing area 17 is cut at once to be separated into a unit stack package.
이와 같은 본 발명의 칩 스케일 적층 패키지 제조 방법은 적층 패키지의 제조에 있어서 각각의 단위 공정이 모두 웨이퍼 상태에서 이루어진다. 따라서, 대량으로 작업이 가능하며 종래의 적층 패키지를 제조하기 위해 사용되는 많은 설비들을 필요로 하지 않는다.In the chip scale stacked package manufacturing method of the present invention, each unit process is performed in a wafer state in the manufacture of the stacked package. Thus, it is possible to work in large quantities and does not require many of the facilities used to manufacture conventional laminated packages.
한편, 본 발명에 따른 칩 스케일 적층 패키지와 그 제조 방법은 전술한 실시예에 한정되지 않고 본 발명의 기술적 중심사상을 벗어나지 않는 범위 내에서 다양하게 변형 실시가 될 수 있다.Meanwhile, the chip scale stack package and the method of manufacturing the same according to the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the technical spirit of the present invention.
이상과 같은 본 발명에 의한 칩 스케일 적층 패키지와 그 제조 방법에 따르면, 두 배의 용량이면서도 칩 수준의 크기와 두께를 갖는 적층 패키지의 구현이 가능하여 실장밀도를 향상시킬 수 있다. 그리고, 적층 패키지의 제조가 웨이퍼 상태에서 이루어지기 때문에 대량 작업이 가능하여 생산성이 향상된다. 또한, 종래보다많은 제조 설비가 필요하지 않기 때문에 생산비용을 절감할 수 있다.According to the chip scale stack package and the method of manufacturing the same according to the present invention as described above, it is possible to implement a stack package having a double capacity and chip size and thickness can improve the mounting density. In addition, since the manufacture of the laminated package is made in the wafer state, a large amount of work is possible, and the productivity is improved. In addition, production costs can be reduced because more manufacturing equipment is not required than in the prior art.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100388287B1 (en) * | 1999-06-07 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | back grinding method of wafer and semiconductor package thereof and its manufacturing method |
| KR100422343B1 (en) * | 2001-05-10 | 2004-03-10 | 주식회사 하이닉스반도체 | stack package and method of fabricating the same |
| KR100480909B1 (en) * | 2001-12-29 | 2005-04-07 | 주식회사 하이닉스반도체 | method for manufacturing stacked chip package |
| US7151009B2 (en) | 2004-06-18 | 2006-12-19 | Samsung Electronics Co., Ltd. | Method for manufacturing wafer level chip stack package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101501739B1 (en) | 2008-03-21 | 2015-03-11 | 삼성전자주식회사 | Method of Fabricating Semiconductor Packages |
| KR101011898B1 (en) * | 2010-05-24 | 2011-02-01 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982633A (en) * | 1997-08-20 | 1999-11-09 | Compaq Computer Corporation | Opposed ball grid array mounting |
| KR100487135B1 (en) * | 1997-12-31 | 2005-08-10 | 매그나칩 반도체 유한회사 | Ball Grid Array Package |
| KR19990069447A (en) * | 1998-02-09 | 1999-09-06 | 구본준 | Semiconductor package and manufacturing method |
| KR100618542B1 (en) * | 1999-07-27 | 2006-08-31 | 삼성전자주식회사 | Method for manufacturing stack package |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100388287B1 (en) * | 1999-06-07 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | back grinding method of wafer and semiconductor package thereof and its manufacturing method |
| KR100422343B1 (en) * | 2001-05-10 | 2004-03-10 | 주식회사 하이닉스반도체 | stack package and method of fabricating the same |
| KR100480909B1 (en) * | 2001-12-29 | 2005-04-07 | 주식회사 하이닉스반도체 | method for manufacturing stacked chip package |
| US7151009B2 (en) | 2004-06-18 | 2006-12-19 | Samsung Electronics Co., Ltd. | Method for manufacturing wafer level chip stack package |
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