CN115425001A - Packaging structure and forming method thereof - Google Patents

Packaging structure and forming method thereof Download PDF

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Publication number
CN115425001A
CN115425001A CN202211152719.8A CN202211152719A CN115425001A CN 115425001 A CN115425001 A CN 115425001A CN 202211152719 A CN202211152719 A CN 202211152719A CN 115425001 A CN115425001 A CN 115425001A
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China
Prior art keywords
layer
wafer
forming
rewiring
passivation
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CN202211152719.8A
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Chinese (zh)
Inventor
刘在福
曾昭孔
郭瑞亮
焦洁
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Suzhou Tongfu Chaowei Semiconductor Co ltd
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Suzhou Tongfu Chaowei Semiconductor Co ltd
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Priority to CN202211152719.8A priority Critical patent/CN115425001A/en
Publication of CN115425001A publication Critical patent/CN115425001A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Abstract

A package structure and a method of forming the same, the structure comprising: a first wafer having opposing first and second sides; the passivation layer is fixed on the surface of the side wall of the first wafer and provided with a third surface and a fourth surface which are opposite; a plurality of first connection layers positioned in the passivation layer, the first connection layers penetrating the passivation layer from the third surface to the fourth surface; the second connecting layers penetrate through the passivation layer from the first surface to the second surface; a first electrical connection structure on a fourth surface of the passivation layer, the first electrical connection structure being electrically connected to the first connection layer; and the second electric connection structure is positioned on the second surface of the first wafer and is electrically connected with the second connection layer. The packaging structure has high packaging flexibility and saves area.

Description

Packaging structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a package structure and a method for forming the same.
Background
In a semiconductor manufacturing process, packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip, which is a last ring for manufacturing the chip.
The packaging process comprises the following steps: the wafer from the previous wafer process is cut into small chips (Die) through a scribing process, then the cut chips are fixed on a lead frame, and the bonding pads of the chips are externally connected by utilizing superfine metal (gold tin copper aluminum) wires or conductive resin; the individual chips are then encapsulated and protected by a plastic housing.
However, the conventional packaging method is complicated in process, and the yield needs to be improved, so that the packaging process needs to be improved to improve the yield and simplify the process.
Disclosure of Invention
The invention provides a package structure and a forming method thereof to improve the package process and improve the yield and simplify the process.
In order to solve the above technical problem, a technical solution of the present invention provides a package structure, including: a first wafer having opposing first and second sides; the passivation layer is fixed on the surface of the side wall of the first wafer and provided with a third surface and a fourth surface which are opposite; a plurality of first connection layers positioned in the passivation layer, the first connection layers penetrating the passivation layer from the third surface to the fourth surface; the second connecting layers penetrate through the passivation layer from the first surface to the second surface; a first electrical connection structure on a fourth surface of the passivation layer, the first electrical connection structure being electrically connected to the first connection layer; and the second electric connection structure is positioned on the second surface of the first wafer and is electrically connected with the second connection layer.
Optionally, the first connection structure includes: a first rewiring layer and a first bonding layer on the first rewiring layer; the second connecting structure includes: a second redistribution layer and a second bonding layer on the second redistribution layer.
Optionally, the method further includes: and the first rewiring layer and the second rewiring layer are positioned in the insulating layer.
Optionally, the material of the passivation layer includes an organic material, and the organic material includes polyimide or poly-p-phenylene benzobisoxazole; the material of the first connection layer comprises a metal comprising copper; the material of the second connection layer comprises a metal comprising copper.
Correspondingly, the technical scheme of the invention also provides a forming method of the packaging structure, which comprises the following steps: providing a substrate; providing a first wafer, wherein the first wafer is provided with a first side and a second side which are opposite, and a first connecting layer is arranged in the first wafer and penetrates through the wafer from the first side to the second side of the wafer; fixing the first wafer on a substrate, wherein the second surface of the first wafer is fixed on the surface of the substrate; forming a passivation layer and a plurality of first connecting layers positioned in the passivation layer on the side wall of the first wafer, wherein the passivation layer is also positioned on the substrate and is provided with a third surface and a fourth surface which are opposite, the fourth surface of the passivation layer is fixed on the substrate, and the first connecting layers penetrate through the passivation layer from the third surface to the fourth surface; after the first connecting layer is formed, removing the substrate; after removing the substrate, forming a first electric connection structure on a fourth surface of the passivation layer, wherein the first electric connection structure is electrically connected with the first connection layer; and forming a second electric connection structure on the second surface of the first wafer, wherein the second electric connection structure is electrically connected with the second connection layer.
Optionally, the first electrical connection structure includes: a first redistribution layer and a first bonding layer on the first redistribution layer; the second connecting structure includes: a second rewiring layer and a second solder layer on the second rewiring layer.
Optionally, the first electrical connection structure and the second electrical connection structure are formed simultaneously; the method for forming the first and second electrical connection structures includes: forming a rewiring material layer on the first surface of the first wafer and the third surface of the passivation layer; forming a patterned layer on the rewiring material layer; etching the rewiring material layer by taking the graphical layer as a mask until the third surface of the passivation layer is exposed to form a first rewiring layer electrically connected with the first connecting layer and a second rewiring layer electrically connected with the second connecting layer; forming an insulating layer on the surface of the side wall of the first rewiring layer and the surface of the side wall of the second rewiring layer; forming a sacrificial layer on the insulating layer and on the first rewiring layer and on the second rewiring layer; forming a plurality of first grooves and second grooves in the sacrificial layer, wherein the first grooves expose the top surface of the first rewiring layer, and the second grooves expose the top surface of the second rewiring layer; forming initial welding layers in the first groove and the second groove; removing the sacrificial layer; and after removing the sacrificial layer, carrying out leveling treatment on the initial welding layer to form a first welding layer on the first rewiring layer and the insulating layer and a second welding layer on the second rewiring layer and the insulating layer.
Optionally, the method for forming the passivation layer and the first connection layers in the passivation layer on the sidewall of the wafer includes: forming a passivation material layer on the surface of a substrate and the surface of a wafer, wherein the thickness of the passivation material layer is larger than that of the wafer; etching the passivation material layer to form a passivation layer positioned on the side wall of the wafer, wherein the passivation layer is internally provided with a plurality of openings, and the bottom of each opening is exposed out of the surface of the substrate; forming a connecting material layer in the opening and on the surface of the passivation layer; and flattening the connecting material layer until the surface of the passivation layer is exposed to form the first connecting layer.
Optionally, the method for removing the substrate includes: providing a carrier plate; bonding the first surface of the first wafer and the third surface of the passivation layer on a carrier plate; and flattening the substrate until the second surface of the first wafer and the fourth surface of the passivation layer are exposed.
Optionally, after the first electrical connection structure and the second electrical connection structure are formed, the method further includes: and removing the carrier plate.
Optionally, the process of planarizing the substrate includes a chemical mechanical polishing process.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the first connecting layer is formed in the passivation layer, the second connecting layer is formed in the first wafer, the first electric connecting structure is formed on the fourth surface of the passivation layer, and the second electric connecting structure is formed on the second surface of the first wafer. The first and second electrical connection structures are used for subsequent electrical connection with other structures. The first electric connection structure and the second electric connection structure are located on the second surface of the first wafer on the fourth surface of the passivation layer respectively, so that the connection flexibility of the packaging structure is high, a plurality of semi-packaging structures can be stacked and connected together, the area of the packaging structure can be reduced, the number of the packaging structures in a unit area is increased, the stored energy of a single chip can be increased, and the working speed of the chip is increased.
Drawings
Fig. 1-3 are schematic diagrams illustrating a process of forming a package structure according to an embodiment;
fig. 4 to 8 are schematic diagrams illustrating a process of forming a package structure according to an embodiment of the invention.
Detailed Description
As described in the background art, the conventional packaging method has a complex process and a yield needs to be improved, and the packaging process needs to be improved to improve the yield and simplify the flow. The analysis will now be described with reference to specific examples.
Fig. 1 to 3 are schematic views illustrating a process of forming a package structure according to an embodiment.
Referring to fig. 1, a carrier 100 is provided; forming an adhesive layer 101 on the carrier 100; providing a wafer 102, wherein the wafer 102 comprises a functional side and a non-functional side; the functional side of the wafer 102 is fixed to the adhesive layer 101.
Referring to fig. 2, a molding layer 103 is formed on the carrier 100, and the molding layer 103 covers the sidewall surface and the non-functional surface of the wafer 102.
Referring to fig. 3, the carrier 100 and the adhesive layer 101 are removed to expose the functional surface of the wafer 102; forming a rewiring layer 104 on the functional surface of the wafer 102, forming an insulating layer 105 on the functional surface of the wafer 102 and the plastic package layer 103, wherein the rewiring layer 104 is electrically connected with the wafer 102, and the rewiring layer 104 is positioned in the insulating layer 105; solder balls 106 are formed on the insulating layer 105, and the solder balls 106 are electrically connected to the redistribution layer 104.
In the forming process of the packaging structure, the whole process from forming the plastic packaging layer 103 to forming the solder balls 106 is longer, so that the process time is longer, and the problem of yield rate is easy to occur in the process; secondly, the external connection mode of the packaging structure is single, and the packaging structure has great limitation in application.
In order to solve the above problems, an embodiment of the present invention provides a package structure and a method for forming the package structure, in which a first connection layer is formed in a passivation layer, a second connection layer is formed in a first wafer, a first electrical connection structure is formed on a fourth surface of the passivation layer, and a second electrical connection structure is formed on a second surface of the first wafer. The first and second electrical connection structures are used for subsequent electrical connection with other structures. The first electric connection structure and the second electric connection structure are located on the second surface of the first wafer on the fourth surface of the passivation layer respectively, so that the connection flexibility of the packaging structure is high, a plurality of semi-packaging structures can be stacked and connected together, the area of the packaging structure can be reduced, the number of the packaging structures in a unit area is increased, the stored energy of a single chip can be increased, and the working speed of the chip is increased.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 8 are schematic diagrams illustrating a process of forming a package structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided.
The material of the substrate 200 includes a semiconductor material or an inorganic material.
In this embodiment, the semiconductor material includes a silicon plate, and the inorganic material includes tempered glass.
With continued reference to fig. 4, a first wafer 202 is provided, the first wafer 202 having a first side and a second side opposite to each other.
In this embodiment, the first wafer 202 further has a second connection layer 203 therein, and the second connection layer 203 penetrates through the first wafer 202 from the first side to the second side of the first wafer 202.
The material of the second connection layer 203 comprises a metal, which comprises copper.
In other embodiments, the second connection layer may not be formed.
With reference to fig. 4, the first wafer 202 is fixed on the substrate 200, and the second surface of the first wafer 202 is fixed on the surface of the substrate 200.
The method of securing the first wafer 202 to a substrate includes: forming a first adhesive layer 201 on the substrate 200; the first wafer 202 is disposed on the first adhesive layer 201.
The first adhesive layer 201 is made of a material having a viscosity capable of adhering and fixing the second surface of the first wafer 202 to the substrate 200.
In this embodiment, the first adhesive layer 201 is a DAF film, and the DAF film is a resin adhesive with high thermal conductivity.
Next, a passivation layer and a plurality of first connection layers located in the passivation layer are formed on the sidewall of the first wafer 202, the passivation layer is also located on the substrate 200, the passivation layer has a third surface and a fourth surface opposite to each other, the fourth surface of the passivation layer is fixed on the substrate 200, and the first connection layers penetrate through the passivation layer from the third surface to the fourth surface. Please refer to fig. 5 and 6 for the process of forming the passivation layer and the first connection layer.
Referring to fig. 5, a passivation layer 204 is formed on the surface of the substrate 200 and the surface of the first wafer 202, wherein the passivation layer 204 has a thickness greater than that of the first wafer 202.
The material of the passivation layer 204 includes an organic material, and the organic material includes Polyimide (PI) or Poly-p-Phenylene Benzobisoxazole (PBO).
In this embodiment, after forming the passivation material layer 204, the method further includes: the passivation layer 204 is cured.
The process of curing the passivation material layer 204 includes: and (5) thermal curing treatment.
Referring to fig. 6, the passivation layer 204 is etched to form a passivation layer 205 on the sidewall of the first wafer 202, where the passivation layer 205 has a third surface and a fourth surface opposite to each other, and a plurality of openings (not shown) are formed in the passivation layer 205, and the bottom of the openings exposes the surface of the substrate 200.
With continued reference to fig. 6, a connecting material layer (not shown) is formed within the opening and on the surface of the passivation layer 205; and planarizing the connecting material layer until the surface of the passivation layer 205 is exposed to form the first connecting layer 206, wherein the first connecting layer 206 penetrates through the passivation layer 205 from the third surface to the fourth surface.
The material of the first connection layer 206 comprises a metal, which comprises copper.
Referring to fig. 7, the substrate 200 is removed.
The method of removing the substrate 200 includes: providing a carrier plate (not shown); bonding the third side of the passivation layer 205 and the first side of the first wafer 202 to a carrier; the substrate 200 is planarized until the second side of the first wafer 202 and the fourth side of the passivation layer 205 are exposed.
In the present embodiment, the process of planarizing the substrate 200 includes a chemical mechanical polishing process.
Referring to fig. 8, a first electrical connection structure is formed on a fourth surface of the passivation layer 205, and the first electrical connection structure is electrically connected to the first connection layer 206; a second electrical connection structure is formed on the second side of the first wafer 202, which is electrically connected to the second connection layer 203.
The first electrical connection structure includes: a first redistribution layer 207 and a first solder layer 210 on the first redistribution layer 207; the second connecting structure includes: a second re-wiring layer 209, and a second solder layer 211 on the second re-wiring layer 209.
In this embodiment, the first and second electrical connection structures are formed simultaneously.
The method for forming the first and second electrical connection structures includes: forming a rewiring material layer (not shown) on the first side of the first wafer 202 and on the third side of the passivation layer 205; forming a patterned layer (not shown) on the rewiring material layer; etching the rewiring material layer by using the patterning layer as a mask until the third surface of the passivation layer 205 is exposed, and forming a first rewiring layer 207 electrically connected with the first connecting layer 206 and a second rewiring layer 209 electrically connected with the second connecting layer 203; forming an insulating layer 208 on a sidewall surface of the first rewiring layer 207 and a sidewall surface of the second rewiring layer 209; forming a sacrificial layer (not shown) on the insulating layer 208 and on the first rewiring layer 207 and on the second rewiring layer 209; forming a plurality of first grooves (not shown) and second grooves (not shown) in the sacrificial layer, wherein the first grooves expose the top surface of the first redistribution layer 207, and the second grooves expose the top surface of the second redistribution layer 209; forming an initial weld layer (not shown) within the first recess and within the second recess; removing the sacrificial layer; after the sacrificial layer is removed, leveling processing is performed on the initial solder layer to form a first solder layer 210 on the first rewiring layer 207 and on the insulating layer 208 and a second solder layer 211 on the second rewiring layer 209 and on the insulating layer 208.
The material of the first redistribution layer 207 and the second redistribution layer 209 includes a metal, and in this embodiment, the metal includes copper.
The materials of the first soldering layer 210 and the second soldering layer 211 include soldering tin, tin-lead alloy soldering tin, antimony-added soldering tin, cadmium-added soldering tin, silver-added soldering tin or copper-added soldering tin.
The material of the sacrificial layer comprises an organic material comprising photoresist.
The material of the insulating layer 208 includes a dielectric material including silicon oxide.
In this embodiment, after removing the first and second electrical connection structures, the carrier board is removed.
To this end, the package structure is formed by forming the first connection layer 206 in the passivation layer 205, the second connection layer 203 in the first wafer 202, the first electrical connection structure on the fourth surface of the passivation layer 205, and the second electrical connection structure on the second surface of the first wafer 202. The first and second electrical connection structures are used for subsequent electrical connection with other structures. The first electrical connection structure and the second electrical connection structure are located on the second surface of the first wafer 202 on the fourth surface of the passivation layer 205 respectively, so that the connection flexibility of the packaging structure is high, and a plurality of semi-packaging structures can be stacked and connected together, so that the area of the packaging structure can be reduced, the number of the packaging structures in a unit area can be increased, the stored energy of a single chip can be increased, and the working speed of the chip can be increased.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (11)

1. A package structure, comprising:
a first wafer having opposing first and second sides;
the passivation layer is fixed on the side wall surface of the first wafer and provided with a third surface and a fourth surface which are opposite;
a plurality of first connection layers located within the passivation layer, the first connection layers penetrating the passivation layer from the third face to the fourth face;
the second connecting layers penetrate through the passivation layer from the first surface to the second surface;
a first electrical connection structure on a fourth surface of the passivation layer, the first electrical connection structure being electrically connected to the first connection layer;
and the second electric connection structure is positioned on the second surface of the first wafer and is electrically connected with the second connection layer.
2. The package structure of claim 1, wherein the first connection structure comprises: a first redistribution layer and a first bonding layer on the first redistribution layer; the second connecting structure includes: a second rewiring layer and a second solder layer on the second rewiring layer.
3. The package structure of claim 2, further comprising: and the insulating layer is positioned on the second surface of the first wafer and the fourth surface of the passivation layer, and the first rewiring layer and the second rewiring layer are positioned in the insulating layer.
4. The encapsulation structure of claim 1, wherein the material of the passivation layer comprises an organic material comprising polyimide or poly-p-phenylene benzobisoxazole; the material of the first connection layer comprises a metal comprising copper; the material of the second connection layer comprises a metal, and the metal comprises copper.
5. A method for forming a package structure, comprising:
providing a substrate;
providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite to each other, and the first wafer is internally provided with a first connecting layer which penetrates through the wafer from the first surface to the second surface of the wafer;
fixing the first wafer on a substrate, wherein the second surface of the first wafer is fixed on the surface of the substrate;
forming a passivation layer and a plurality of first connecting layers in the passivation layer on the side wall of the first wafer, wherein the passivation layer is also positioned on the substrate, the passivation layer is provided with a third surface and a fourth surface which are opposite, the fourth surface of the passivation layer is fixed on the substrate, and the first connecting layers penetrate through the passivation layer from the third surface to the fourth surface;
after the first connecting layer is formed, removing the substrate;
after removing the substrate, forming a first electric connection structure on a fourth surface of the passivation layer, wherein the first electric connection structure is electrically connected with the first connection layer;
and forming a second electric connection structure on the second surface of the first wafer, wherein the second electric connection structure is electrically connected with the second connection layer.
6. The method of forming the package structure of claim 5, wherein the first electrical connection structure comprises: a first redistribution layer and a first bonding layer on the first redistribution layer; the second connecting structure includes: a second rewiring layer and a second solder layer on the second rewiring layer.
7. The method of forming the package structure according to claim 6, wherein the first electrical connection structure and the second electrical connection structure are formed simultaneously; the method for forming the first and second electrical connection structures includes: forming a rewiring material layer on the first surface of the first wafer and the third surface of the passivation layer; forming a patterned layer on the rewiring material layer; etching the rewiring material layer by taking the graphical layer as a mask until the third surface of the passivation layer is exposed to form a first rewiring layer electrically connected with the first connecting layer and a second rewiring layer electrically connected with the second connecting layer; forming an insulating layer on the surface of the side wall of the first rewiring layer and the surface of the side wall of the second rewiring layer; forming a sacrificial layer on the insulating layer and on the first rewiring layer and on the second rewiring layer; forming a plurality of first grooves and second grooves in the sacrificial layer, wherein the first grooves expose the top surface of the first rewiring layer, and the second grooves expose the top surface of the second rewiring layer; forming initial welding layers in the first groove and the second groove; removing the sacrificial layer; and after removing the sacrificial layer, carrying out leveling treatment on the initial welding layer to form a first welding layer on the first rewiring layer and the insulating layer and a second welding layer on the second rewiring layer and the insulating layer.
8. The method for forming a package structure according to claim 5, wherein the method for forming the passivation layer and the first connection layers in the passivation layer on the sidewall of the wafer comprises: forming a passivation material layer on the surface of a substrate and the surface of a wafer, wherein the thickness of the passivation material layer is larger than that of the wafer; etching the passivation material layer to form a passivation layer positioned on the side wall of the wafer, wherein the passivation layer is internally provided with a plurality of openings, and the bottom of each opening is exposed out of the surface of the substrate; forming a connecting material layer in the opening and on the surface of the passivation layer; and flattening the connecting material layer until the surface of the passivation layer is exposed to form the first connecting layer.
9. The method of forming the package structure of claim 8, wherein removing the substrate comprises: providing a carrier plate; bonding the first surface of the first wafer and the third surface of the passivation layer on a carrier plate; and flattening the substrate until the second surface of the first wafer and the fourth surface of the passivation layer are exposed.
10. The method of forming the package structure of claim 9, wherein after forming the first electrical connection structure and the second electrical connection structure, further comprising: and removing the carrier plate.
11. The method of claim 9, wherein the process of planarizing the substrate comprises a chemical mechanical polishing process.
CN202211152719.8A 2022-09-21 2022-09-21 Packaging structure and forming method thereof Pending CN115425001A (en)

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