CN114664230A - Display driving chip and LED display panel - Google Patents
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- CN114664230A CN114664230A CN202011528641.6A CN202011528641A CN114664230A CN 114664230 A CN114664230 A CN 114664230A CN 202011528641 A CN202011528641 A CN 202011528641A CN 114664230 A CN114664230 A CN 114664230A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Abstract
The embodiment of the invention discloses a display driving chip and an LED display panel. The display driving chip includes: a synchronous signal input interface; a gradation clock generating circuit; a drive control circuit connected to the gray scale clock generating circuit; the double-synchronous circuit is connected with the gray clock generating circuit, the driving control circuit and the synchronous signal input interface; and the constant current driving circuit is connected with the driving control circuit. According to the embodiment of the invention, the double synchronous circuits are added in the display driving chip, so that the display picture output by the display driving chip can achieve the synchronous effect, the working condition and the influence of the manufacture of the display driving chip are improved, and the display effect is improved.
Description
Technical Field
The invention relates to the technical field of display control, in particular to a display driving chip and an LED display panel.
Background
Currently, LED display devices are used in various fields due to their advantages such as low cost, low power consumption, high visibility, freedom of assembly, and the like. Meanwhile, with the popularization of the application of the LED display device, people have higher and higher requirements for the display quality of the LED display device, and therefore how to improve the display quality of the LED display device has become a research hotspot in the field. With the increasing application scenes of the LEDs, the synchronicity of the display screens of the LEDs is more and more concerned.
The LED display control card transmits the frame synchronization signal sent by the upper computer to the drive chip and controls the drive chip to output, so that the display frame of each frame can be synchronously displayed. However, the gray scale clock periods generated by different driving chips may be deviated due to manufacturing variations of the driving chips and operating conditions of the driving chips. Under the control of the gray scale clock, pulse width modulation signals and line feed signals generated by different driving chips can cause that the different driving chips cannot be synchronized, and finally, the displayed pictures are not synchronized, so that the display effect is deteriorated.
Disclosure of Invention
Therefore, to overcome at least some of the defects and shortcomings in the prior art, embodiments of the present invention provide a display driving chip and an LED display panel to improve the display effect.
In one aspect, a display driving chip provided in an embodiment of the present invention includes: a synchronous signal input interface; a gradation clock generating circuit; a drive control circuit connected to the gray scale clock generating circuit; the double-synchronous generating circuit is connected with the gray clock generating circuit, the driving control circuit and the synchronous signal input interface; the constant current driving circuit is connected with the driving control circuit; wherein, the gray clock generating circuit is used for generating a gray clock signal; the driving control circuit is used for receiving display data and configuration information and generating sub-synchronization information according to the configuration information and the gray clock signal; the double-synchronous circuit receives a frame synchronous signal through the synchronous signal input interface and generates a double-synchronous signal according to the gray clock signal, the frame synchronous signal and the sub-synchronous information; the drive control circuit generates a pulse width modulation signal according to the double synchronous signals, the configuration information and the display data and sends the pulse width modulation signal to the constant current drive circuit; and the constant current driving circuit generates and outputs driving current according to the pulse width modulation signal.
According to the technical scheme, the configuration information and the display data are received through the driving control circuit, then the sub-synchronization information is sent to the double-synchronization circuit through the driving control circuit, the double-synchronization circuit generates double-synchronization signals according to the sub-synchronization information, the frame synchronization signals and the gray scale clock signals, the double-synchronization signals are sent to the driving control circuit to generate pulse width modulation signals, and then the constant current driving circuit is controlled to generate constant current output, so that the output of the display driving chip is controlled, the synchronization times of the display driving chip are increased, and the problems of unsynchronized display pictures and poor display effect caused by the gray scale clock deviation of the driving chip are solved.
In one embodiment of the present invention, the display driving chip further includes: and the synchronous signal output interface is used for outputting the double synchronous signals generated by the double synchronous signal circuit to at least one cascaded next-stage display driving chip.
In one embodiment of the invention, the double synchronization circuit comprises: the frame synchronization detection circuit is connected with the synchronization signal input interface to receive the frame synchronization signal; the sub-synchronous signal generating circuit is connected with the driving control circuit; a double-synchronous signal generating circuit connected with the sub-synchronous signal generating circuit and the frame synchronous detecting circuit; the double-synchronous detection circuit is connected with the double-synchronous signal generation circuit and the synchronous signal input interface; the synchronous mode selection circuit is connected with the frame synchronous detection circuit, the double synchronous detection circuit and the drive control circuit; the sub-synchronous signal generating circuit is used for generating sub-synchronous signals according to the sub-synchronous information and the gray scale clock signals; the frame synchronization detection circuit is used for generating an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal; the double-synchronous signal generating circuit is used for carrying out superposition processing on the sub-synchronous signal and the internal frame synchronous signal to obtain a double-synchronous signal; the double synchronous detection circuit is used for detecting and identifying the double synchronous signals; the synchronous mode selection circuit is used for selecting the identified double synchronous signals or the internal frame synchronous signals according to the configuration information transmitted by the drive control circuit and sending the double synchronous signals or the internal frame synchronous signals to the drive control circuit.
In an embodiment of the present invention, the driving control circuit is further configured to determine a first operating mode of the display driving chip according to the configuration information; when the first working mode of the display driving chip is a frame synchronization mode, the synchronization mode selection circuit outputs the internal frame synchronization signal generated by the frame synchronization detection circuit to the driving control circuit; and when the first working mode of the display driving chip is a double-synchronous mode, the synchronous mode selection circuit outputs a double-synchronous signal identified by the double-synchronous detection circuit to the driving control circuit.
In an embodiment of the present invention, the driving control circuit is further configured to determine a second operating mode of the display driving chip according to the configuration information; when the second working mode of the display driving chip is a main driving mode, the double synchronous detection circuit identifies the double synchronous signals generated by the double synchronous signals and sends the double synchronous signals to the synchronous mode selection circuit, and the synchronous mode selection circuit outputs the double synchronous signals identified by the double synchronous detection circuit to at least one slave display driving chip cascaded with the main display driving chip through the synchronous signal output interface; when the second working mode of the display driving chip is a slave driving mode, the double synchronous detection circuit in the at least one slave display driving chip identifies the double synchronous signals output by the cascaded master display driving chip and then sends the double synchronous signals to the synchronous mode selection circuit in the at least one slave display driving chip, and the synchronous mode selection circuit in the at least one slave display driving chip outputs the double synchronous signals identified by the double synchronous detection circuit in the at least one slave display driving chip to the driving control circuit of the at least one slave display driving chip.
In one embodiment of the present invention, the drive control circuit is further configured to: and determining the sub-refreshing times of the display driving chip according to the gray scale clock signal and the configuration information, generating sub-synchronization information according to the sub-refreshing times, and sending the sub-synchronization information to the double-synchronization circuit.
In another aspect, an embodiment of the present invention provides an LED display panel, including: an LED pixel array comprising a plurality of LED pixel points and each of the LED pixel points comprising a plurality of LEDs; and a plurality of display driving chips as described in the previous embodiments, wherein the constant current driving circuit of the display driving chip is connected to the LED pixel array.
In one embodiment of the present invention, the plurality of display driving chips are cascaded through a synchronization signal output interface; the display driving chips comprise a main display driving chip and at least one auxiliary display driving chip, and a synchronous signal output interface of the main display driving chip is connected with a synchronous signal input interface of the at least one auxiliary display driving chip.
In one embodiment of the invention, the plurality of display driving chips are cascaded through a synchronous signal output interface; the display driving chips comprise a plurality of main display driving chips and a plurality of auxiliary display driving chips, and a synchronous signal output interface of each main display driving chip is connected with a synchronous signal input interface of at least one auxiliary display driving chip.
The technical scheme can have the following advantages or beneficial effects: the embodiment of the invention firstly receives configuration information and display data through the drive control circuit, then sends sub-synchronization information to the double-synchronization circuit through the drive control circuit, the double-synchronization circuit generates double-synchronization signals according to the sub-synchronization information, the internal frame synchronization signal and the gray scale clock signal, sends the double-synchronization signals to the drive control circuit to generate pulse width modulation signals, and further controls the constant current drive circuit to generate constant current output, thereby controlling the output of the display drive chip, increasing the synchronization times of the display drive chip, and improving the problems of asynchronous display pictures and poor display effect caused by the gray scale clock deviation of the drive chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A is a schematic circuit structure diagram of a display driver chip according to an embodiment of the present invention.
Fig. 1B is a schematic circuit structure diagram of another display driver chip according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a specific circuit structure of a dual synchronous generator according to an embodiment of the present invention.
Fig. 3A is a specific circuit diagram of a main display driving chip of a double synchronization generating circuit in a double synchronization mode according to an embodiment of the present invention.
Fig. 3B is a specific circuit diagram of a main display driving chip of a dual synchronization generating circuit in a frame synchronization mode according to an embodiment of the present invention.
Fig. 4 is a specific circuit diagram of a slave display driver chip in a dual synchronization mode of a dual synchronization generating circuit according to an embodiment of the present invention.
Fig. 5 is a specific circuit diagram of a slave display driver chip of a dual synchronization generating circuit in a frame synchronization mode according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a specific circuit structure of a display driver chip according to an embodiment of the present invention.
FIG. 7 is a timing diagram of the dual sync signal and the frame sync signal according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a partial structure of an LED display panel according to an embodiment of the present invention.
Fig. 9 is a schematic partial structure diagram of another LED display unit provided in the embodiment of the present application.
Fig. 10 is a schematic partial structure diagram of another LED display unit according to an embodiment of the present application.
Description of the drawings: 10: a display driving chip; 11: a gradation clock generating circuit; 12: a drive control circuit; 13: a double synchronization circuit; 14: constant current drive circuit: 15: a synchronous signal input interface; 16: a synchronous signal output interface; 20: scanning the chip; 111: a frequency multiplier circuit; 121: a command processing circuit; 122: a shift register circuit; 123: a cache circuit; 124: a counter; 125: a gradation break-up processing circuit; 126: a channel control circuit; 131: a frame synchronization detection circuit; 132: the subsynchronous signal generating circuit: 133: a double synchronization signal generating circuit; 134: a synchronous mode selection circuit; 135: a double synchronous detection circuit; 300: an LED display panel; 400: an LED display panel; 401: an array of LED pixels; 402, performing a chemical reaction; a main display driving chip; 403: the slave display driver chip.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
Fig. 1A is a schematic structural diagram of a display driver chip 10 according to an embodiment of the present invention. As shown in fig. 1A, the display driving chip 10 includes, for example: a gradation clock generating circuit 11, a drive control circuit 12, a double synchronizing circuit 13, a constant current driving circuit 14, and a synchronizing signal input interface 15.
Wherein, the drive control circuit 12 is connected with the gray clock generating circuit 11; the double-synchronous circuit 13 is connected with the gray scale clock generating circuit 11, the driving control circuit 12 and the synchronous signal input interface 15; the constant current driving circuit 14 is connected to the driving control circuit 12.
Wherein, the configuration information and the display data (as shown in DIN [ 2: 0] in FIG. 1A) can be received through other interfaces of the display driver chip, such as a data input interface; the configuration information and the display data may be sent through other chips connected to the data input interface, such as a front-end control card (also called a receiving card) or an upper computer, and the like, which is not limited herein.
The synchronization signal input interface 15 is configured to receive a frame synchronization signal, where the frame synchronization signal may be sent through another chip connected to the synchronization signal input interface 15, such as a front-end control card (also called a receiving card) or an upper computer, and the details of the frame synchronization signal are not limited herein. The synchronization signal input interface 15 may also receive other signals, such as a dual synchronization signal or an internal frame synchronization signal, and the signal received by the synchronization signal input interface 15 may be determined according to an actual connection state of the display driver chip, which is not limited herein.
Wherein the gray scale clock generating circuit 11 is configured to generate a gray scale clock signal and transmit the gray scale clock signal to the driving control circuit 12 and the double synchronization circuit 13; the gray scale clock generating circuit 11 may automatically generate a gray scale clock signal internally, or may receive the clock signal through the data input interface 15, which is not limited herein.
The drive control circuit 12 may obtain the display data DIN [ 2: 0] and configuration information, and generates sub-synchronization information based on the configuration information and a gray scale clock signal, and transmits the sub-synchronization information to the double synchronization circuit 13.
In other embodiments, the configuration information may further include, in the case of multiple display driver chips, other operating modes, such as a driving mode and the like, of the display driver chip, and the specific details are not limited herein; the configuration information may be sent by the main control circuit, or may be sent by a receiving card (also called a display control card) or an upper computer.
The double synchronization circuit 13 receives the frame synchronization signal and the sub-synchronization information sent by the driving control circuit 12 through the synchronization signal input interface 15, generates the double synchronization signal according to the gray clock signal, the frame synchronization signal and the sub-synchronization information, and sends the double synchronization signal to the driving control circuit 12.
The display driving chip 10 performs one complete refresh on the currently controlled display area in each frame or performs multiple complete refreshes on the LED display screen in each frame, each complete refresh is called sub-refresh, and the sub-synchronization information includes sub-refresh frequency information that the display driving chip completes one frame of complete display on the currently controlled display area and needs complete refresh; the configuration information further includes the number of times of sub-refresh, then the driving control circuit determines, according to the configuration information, that the number of times of sub-refresh, for example, the number of times of complete refresh required for completing one frame of complete display of the currently controlled display region, is 4 times, and then generates sub-synchronization information according to the number of times of sub-refresh, the display data, and the gray scale clock signal, for example, the sub-synchronization information is information that the display driving chip 10 completes one frame of complete display of the currently controlled display region, and is required for completing one frame of complete display of 4 times.
The driving control circuit 12 is further configured to generate a pulse width modulation signal according to the double synchronization signal, the display data, and the configuration information, and send the pulse width modulation signal to the constant current driving circuit 14;
the constant current driving circuit 14 is configured to receive the pulse width modulation signal, generate a driving current, and simultaneously drive a plurality of channels (e.g., DOUT shown in fig. 1A) to output the driving current.
The working principle of the embodiment is as follows: the display driving chip 10 is powered on, then the gray scale clock generating circuit 11 generates a gray scale clock signal and transmits the gray scale clock signal to the driving control circuit 12 and the double synchronous circuit 13; meanwhile, the driving control circuit 12 receives display data and configuration information, then the driving control circuit 12 generates sub-synchronization information according to the gray scale clock signal and the configuration information and sends the sub-synchronization information to the double synchronization circuit 13, and controls the double synchronization circuit 13 to receive a frame synchronization signal through a synchronization signal input interface 15 according to the configuration information, then the double synchronization circuit 13 generates a double synchronization signal according to the received sub-synchronization information and the frame synchronization signal and sends the double synchronization signal to the driving control circuit 12 according to the configuration information transmitted by the driving control circuit, when the display driving chip 10 determines that the first working mode is a double synchronization mode according to the configuration information, the driving control circuit 12 generates a pulse width modulation signal according to the double synchronization signal, the configuration information and the display data and sends the pulse width modulation signal to the constant current driving circuit 14, the constant current driving circuit 14 generates a driving current output according to the pulse width modulation signal.
According to the embodiment of the invention, the display driving chip 10 is designed, the configuration information and the display data are received through the driving control circuit 12, then the sub-synchronization information is sent to the double-synchronization circuit through the driving control circuit, the double-synchronization circuit generates the double-synchronization signal according to the sub-synchronization information, the frame synchronization signal and the gray scale clock signal and sends the double-synchronization signal to the driving control circuit 12, the driving control circuit 12 generates the pulse width modulation signal according to the double-synchronization signal, the configuration information and the display data, and then the constant current driving circuit 14 is controlled to generate the constant current output, so that the output of the display driving chip is controlled, the synchronization times of the display driving chip are increased, and the problems of asynchronous display pictures and poor display effect caused by the gray scale clock deviation of the driving chip are solved.
Further, as shown in fig. 1B, the display driving chip 10 further includes a synchronous signal output interface 16, configured to output the double synchronous signals generated by the double synchronous signal circuit 13 to at least one next-stage display driving chip in cascade connection.
Through setting up synchronous signal output interface 16 on display driver chip 10, can send the double synchronizing signal to the other display driver chips of the next level that are connected with current display driver chip, between the display driver chips of interconnect like this, when the double synchronizing signal that last level display driver chip output arrives, show the synchronization, when other synchronous signals pass through synchronous signal output interface output, also can make interconnect's display driver chip reach synchronous effect to the wiring has been reduced.
Further, as shown in fig. 6, the gradation clock generating circuit 11 includes: the frequency multiplier circuit 111 may obtain an input clock signal through the data input interface, or may internally generate a gray scale clock signal, which is not limited herein. And after acquiring the input clock signal from the data input interface, performing frequency multiplication on the data clock signal to obtain a gray level clock signal GCLK.
Further, as shown in fig. 6, the drive control circuit 12 includes: a command processing circuit 121, a shift register circuit 122, a buffer circuit 123, a counter 124, a gradation break-up processing circuit 125, and a channel control circuit 126.
The shift register circuit 122 is connected to the command processing circuit 121; the buffer circuit 123 is connected to the shift register circuit 122; the counter 124 is connected to the command processing circuit 121 and the gradation clock generating circuit 11; the gray scale scattering processing circuit 125 is connected to the command processing circuit 121 and the counter 124; the channel control circuit 126 is connected to the command processing circuit 121, the counter 124, the gradation dispersion processing circuit 125, the buffer circuit 123, and the double synchronization circuit 13.
The command processing circuit 121 is connected to the shift register circuit 122 and receives the control of the gray scale clock signal GCLK and the configuration information output by the shift register circuit 122.
The shift register circuit 122 is used for accessing display data DIN [ 2: 0] and configuration information. The shift register circuit 122 is configured to receive the display data and the configuration information and send the configuration information to the command processing circuit 121. For example, the Shift Register circuit 122 of the present embodiment includes a Shift Register (Shift Register) and circuit logic for command response and data transfer (such as DMA transfer). DMA is herein an abbreviation for Direct Memory Access, the name of which is Direct Memory Access.
The buffer circuit 123 is connected to the shift register circuit 122 to obtain and store the display data. For example, the cache circuit 123 of the present embodiment includes a Static Random Access Memory (SRAM) buffer Memory and a RAM Controller (RAM Controller).
The counter 124 is connected to the command processing circuit 121 and the frequency multiplier circuit 111, and is configured to receive a gray scale clock signal GCLK and generate a gray scale clock count value under the control of the gray scale clock signal GCLK.
The gray level scattering processing circuit 125 is connected to the command processing circuit 121 and the counter 124, and is configured to receive control of the command processing circuit 121, further control counting operation of the counter 124, and generate a gray level grouping control signal.
The channel control circuit 126 is connected to the command processing circuit 121, the counter 124, the buffer circuit 123, the constant current driving circuit 14, and the double synchronization circuit 13, and configured to generate a pulse width modulation signal according to the gray scale clock count value, the gray scale grouping control signal, the double synchronization signal, the display data acquired by the buffer circuit 123, and the configuration information, and send the pulse width modulation signal to the constant current driving circuit 14, where the constant current driving circuit 14 generates a driving current according to the pulse width modulation signal and outputs the driving current to a plurality of output channels (e.g., DOUT [95:0] shown in fig. 3). In this embodiment, the display driver chip 10 is an LED display driver chip, and has, for example, 96 output channels DOUT [95:0], so that 96 rows of LED lamp points can be carried; taking an example that three RGB LED light points constitute one LED pixel point, the LED pixel point can carry 32 rows of RGB full-color LED pixel points, that is, 96 output channels DOUT [95:0] are divided into 32 red (R) component output channels, 32 green (G) component output channels, and 32 blue (B) component output channels.
The channel control circuit 126 is further configured to generate sub-synchronization information according to the gray clock count value, the gray grouping control signal, and the configuration information stored in the buffer circuit 123, and send the sub-synchronization information to the double synchronization circuit 13.
Further, as shown in fig. 2, the double synchronization circuit 13 includes: a frame synchronization detecting circuit 131, a sub synchronization signal generating circuit 132, a double synchronization signal generating circuit 133, a synchronization mode selecting circuit 134, and a double synchronization detecting circuit 135.
Wherein the frame synchronization detecting circuit 131 is connected to the gray scale clock generating circuit 11 and the synchronization signal input interface 15 and receives a frame synchronization signal through the synchronization signal input interface 15; the sub-synchronizing signal generating circuit 132 is connected to the gradation clock generating circuit 11 and the drive control circuit 12; the double synchronizing signal generating circuit 133 is connected to the sub synchronizing signal generating circuit 132, the gradation clock generating circuit 11, the frame synchronization detecting circuit 131, and the double synchronizing detecting circuit 135; the synchronous mode selection circuit 134 is connected to the frame synchronization detection circuit 131, the double synchronization signal generation circuit 133, the gradation clock generation circuit 11, the drive control circuit 12, and the double synchronization detection circuit 135, which is connected to the synchronous signal input interface 15, the gradation clock generation circuit 11, the double synchronization generation circuit 133, and the synchronous mode selection circuit 134; it should be noted that fig. 1A and 1B show the connection relationship between the double synchronization circuit and the gray scale clock generation circuit 11, that is, the gray scale clock generation circuit 11 provides a gray scale clock signal to each block in the double synchronization circuit 13, and therefore fig. 2 does not show the connection relationship between each block in the double synchronization circuit 13 and the gray scale clock generation circuit, but does not represent that each block in the double synchronization circuit 13 is not connected to the gray scale clock generation circuit 11.
The frame synchronization detecting circuit 131 is configured to obtain a frame synchronization signal through the synchronization signal input interface 15, generate an internal frame synchronization signal according to the frame synchronization signal and gray scale clock information after detecting that the frame synchronization signal is input, and output the internal frame synchronization signal to the double synchronization signal generating circuit 133; the internal frame synchronization signal is a frame synchronization signal suitable for the current display driving chip, and the difference between the internal frame synchronization signal and the frame synchronization signal is only in the time sequence difference of the two or the pulse width difference of the two.
The sub-synchronization signal generating circuit 131 is configured to receive the sub-synchronization information sent by the driving control circuit 12 and the gray scale clock signal generated by the gray scale clock generating circuit 11, generate a sub-synchronization signal according to the sub-synchronization information and the gray scale clock signal, and output the sub-synchronization signal to the double synchronization signal generating circuit 133; the sub-synchronization information is, for example, information that the display driver chip needs to completely refresh 4 times to complete one-frame complete display of the currently controlled display area; the sub-sync signal generation circuit 131 then generates sub-sync signals, i.e., 4 sub-sync signals, based on the sub-sync information and the gray scale clock signal.
The double synchronization signal generating circuit 133 is configured to receive the internal frame synchronization signal and the sub synchronization signal, superimpose the internal frame synchronization signal and the sub synchronization signal to generate the double synchronization signal, and output the double synchronization signal to the synchronization mode selecting circuit 134;
the double-synchronization detection circuit 135 is configured to detect a double-synchronization signal sent by a double-synchronization generation circuit, identify an internal frame synchronization signal and a sub-synchronization signal in the double-synchronization signal, and send the identified double-synchronization signal to the synchronization mode selection circuit. As shown in fig. 5, the double sync signal includes an intra frame sync signal and a sub sync signal, and 2 intra frame sync signals and 4 sub sync signals are identified. The double synchronization detection circuit 135 may be further configured to receive a double synchronization signal through the synchronization signal input interface 15.
The double synchronization detection circuit 135 may also be configured to receive a double synchronization signal sent by a previous-stage display driver chip through the synchronization signal input interface 15, identify an internal frame synchronization signal and a sub synchronization signal in the double synchronization signal, and send the identified double synchronization signal to the synchronization mode selection circuit.
The synchronization mode selection circuit 134 is configured to receive the identified double synchronization signal or internal frame synchronization signal, and output the identified double synchronization signal or internal frame synchronization signal in the double synchronization signal to the driving control circuit 12.
The double synchronous signals are generated by superposing the sub synchronous signals and the internal frame synchronous signals, the display driving chip completes display synchronization when the frame synchronous signals arrive, and display synchronization can be carried out when the sub synchronous signals arrive. As shown in fig. 7, the double synchronization signal includes a frame synchronization signal and a plurality of sub synchronization signals between two frame synchronization signals, the period and number of the sub synchronization signals can be configured by the driving control circuit 12, that is, the user can set the configuration information by himself/herself and then set the configuration information, or the configuration information can be configured by himself/herself through the driving control circuit 12, which is not limited herein, the drive control circuit 12 then generates sub-synchronization information based on the configuration information and the gradation clock signal, the sub-synchronization signal generation circuit 131 then generates sub-synchronization signals from the sub-synchronization information and the gradation clock signal, for example, the sub-synchronization information is information that the display driver chip needs to completely refresh 4 times to complete a frame of complete display on the currently controlled display area, 4 sub-sync signals are generated based on the sub-sync information and the gray clock signal and transmitted to the double sync signal generating circuit 133. Then, the double synchronization signal generating circuit 133 superimposes the internal frame synchronization signal and the 4 sub-synchronization signals to generate the double synchronization signal, where the double synchronization signal is a signal obtained by superimposing 4 sub-synchronization signals between two frame synchronization signals (as shown in a timing chart of the double synchronization signal in fig. 7), and due to the difference caused by the difference of the working environment or the difference of the manufacturing process of the gray scale clock generating circuit 11 in the display driving chip 10, the generated accumulation error is cleared in time by refreshing and synchronizing the sub-synchronization signals for multiple times between two frame synchronization signals.
In order to more clearly understand the display drive control circuit 10 of the present embodiment, the operation principle thereof will be exemplified below with reference to fig. 1A, 1B, 2, 3A, 3B, 6, and 7.
After the display driver chip 10 starts to be powered on normally, the display driver chip 10 receives the configuration information and the display data through the combination command and sends the configuration information and the display data to the shift register circuit 122 inside the driving control circuit 12.
The frequency multiplier circuit 111 of the gray scale clock generating circuit 11 generates a gray scale clock signal by receiving a clock signal internally or externally, and transmits the gray scale clock signal to the counter 124 in the drive control circuit 12 and the double synchronization circuit 13.
The shift register circuit 122 receives configuration information and display data DIN [ 2: 0 ]; and sends the configuration information to the command processing circuit 121.
The counter 124 is configured to receive the gray scale clock signal and generate a gray scale clock count value under the control of the gray scale clock signal; the gradation break processing circuit 125 is then used to accept the control of the command processing circuit to control the counting operation of the counter 124 and to generate gradation grouping control signals; the channel control circuit 126 then obtains the configuration information, the gray clock count value and the gray grouping control signal from the shift register circuit 122, generates sub-synchronization information according to the configuration information, the gray clock count value and the gray grouping control signal, and sends the sub-synchronization information to the sub-synchronization signal generation circuit.
Then the sub-synchronization signal generating circuit 132 generates a sub-synchronization signal according to the sub-synchronization information and the gray scale clock signal and sends the sub-synchronization signal to the double-synchronization signal generating circuit 133, meanwhile, the frame synchronization detecting circuit 131 receives a frame synchronization signal through the synchronization signal input interface 15, generates an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal and sends the internal frame synchronization signal to the double-synchronization signal generating circuit 133, and the double-synchronization signal generating circuit 133 superimposes the sub-synchronization signal and the internal frame synchronization signal to obtain the double-synchronization signal and sends the double-synchronization signal to the double-synchronization detecting circuit 135; the double-synchronization detection circuit 135 detects and identifies the internal frame synchronization signal and the sub-synchronization signal in the double-synchronization signal, and sends the identified internal frame synchronization signal and the identified sub-synchronization signal to the synchronization mode selection circuit 134, when the display driver chip 10 determines that the first working mode is the double-synchronization mode according to the configuration information, the synchronization mode selection circuit 134 selects the identified double-synchronization signal (i.e., the identified internal frame synchronization signal and the identified sub-synchronization signal) according to the configuration information, sends the identified double-synchronization signal to the driver control circuit 12, and simultaneously outputs the double-synchronization signal to the next display driver chip cascaded with the current display driver chip 10 through the synchronization signal output interface 16.
Wherein, the timing chart of the double synchronous signals is shown in fig. 7, the double synchronous signals include frame synchronous signals, and a plurality of sub synchronous signals are added between two frame synchronous signals, the period of the sub synchronous signals can be flexibly set, the display driving chip 10 performs a complete refresh of the currently controlled display area once in each frame or performs a complete refresh of the LED display screen several times in each frame, each complete refresh is called a sub-refresh, the sub-synchronization information comprises sub-refresh frequency information which is required to be completely refreshed when the display driving chip completes one-frame complete display on the area which is currently controlled to be displayed, and then generates sub-synchronization information based on the number of sub-refreshes, the display data and the gray scale clock signal, for example, the sub-synchronization information is information that the display driver chip 10 needs to refresh 4 times to complete a frame of complete display on the currently controlled display area. A plurality of sub-refreshes can be implemented within one period of the frame synchronization signal. Then, the command processing circuit 111 receives the double synchronization signal and clears the gray scale clock count value of the counter 124 for counting the gray scale clock signal GCLK generated by the frequency multiplier circuit 111.
Then the buffer circuit 123 obtains and stores the display data from the shift register circuit 122, and then sends the display data to the channel control circuit 126;
at this time, the drive control circuit 12 has received the double synchronization signal, and then the channel control circuit 126 generates a pulse width modulation signal from the gradation clock count value, the gradation grouping control signal, the double synchronization signal, the display data, and the configuration information, and sends the pulse width modulation signal to the constant current drive circuit 14.
The constant current driving circuit 14 generates a driving current according to the pulse width modulation signal, and outputs the driving current through an output channel DOUT [95:0] output.
In addition, the first working mode further includes a frame synchronization mode, when the driving control circuit 12 determines that the first working mode is the frame synchronization mode according to the configuration information, the synchronization mode selection circuit 134 selects the internal frame synchronization signal according to the configuration information to input to the driving control circuit 12, and outputs the internal frame synchronization signal to a next-stage display driving chip cascaded with the current display driving chip through the synchronization signal output interface 16.
At this time, the drive control circuit 12 has received the internal frame synchronization signal, and then the channel control circuit 126 generates a target pulse width modulation signal from the gradation clock count value, the gradation grouping control signal, the internal frame synchronization signal, the display data, and the configuration information, and sends the target pulse width modulation signal to the constant current drive circuit 14.
The constant current driving circuit 14 generates a target driving current according to the target pulse width modulation signal, and outputs the target driving current through an output channel DOUT [95:0] output
In summary, in the embodiments of the present invention, the configuration information and the display data are received by the driving control circuit, and then the sub-synchronization information is sent to the double-synchronization circuit by the driving control circuit, the double-synchronization circuit generates the double-synchronization signal according to the sub-synchronization information and the gray scale clock signal, and sends the double-synchronization signal to the driving control circuit to generate the pulse width modulation signal, so as to control the constant current driving circuit to generate the constant current output, thereby controlling the output of the display driving chip, increasing the synchronization times of the display driving chip, and improving the problems of display frame asynchronization and display effect deterioration caused by the gray scale clock deviation of the driving chip.
[ second embodiment ]
Fig. 8 is a schematic diagram of a partial structure of an LED display panel 300 according to an embodiment of the present invention. As shown in fig. 8, the LED display panel 300 includes: a plurality of LED pixel arrays PA, a plurality of display driver chips 10 (illustrated as an example in the figure).
Wherein each LED pixel array PA comprises 32 columns of pixels P and each pixel P comprises a plurality of LEDs, such as R, G, B tricolor LED light points, such that the LED pixel array PA has 96 columns of LED light points. Each 96-column LED lamp point is connected to 96 output channels DOUT 0-DOUT 95 in each display driving chip 10, and the pixel P in each column is connected to three adjacent output channels of the constant current driving circuit 14. Furthermore, the pixel array PA includes 32 rows of pixels P, and the 32 rows of pixels P are respectively connected to the 32 output channels LINE 0-LINE 31 of the scan control chip 20.
The display driver chips are the display driver chips including the synchronization signal input interface 15 as shown in fig. 1A, and each display driver chip is connected between the display control card and the LED pixel array.
The scan control chip 20 of the present embodiment includes, for example, a line decoding chip, which can cooperate with the display driving chip 10 to sequentially generate 32 line scanning signals (or scanning driving signals) in each 32 scanning cycles. It should be noted that the number of output channels of the scan control chip 20 of the present embodiment is not limited to 32, and may be other numbers, such as 64, and the specific number may be determined according to the actual application requirement.
The display driver chip of the present embodiment receives display data DIN [ 2: 0], configuration information and frame synchronization signal.
[ third embodiment ]
Fig. 9 shows another LED display panel 400 according to an embodiment of the present invention, where the LED display panel 400 includes: a plurality of LED pixel arrays 401 and a plurality of display driving chips 10; the LED pixel arrays 401 are the LED pixel arrays PA described in the second embodiment, and details are not repeated here.
The constant current driving circuit in each display driving chip in the plurality of display driving chips is connected with each LED pixel array in the plurality of LED pixel arrays.
The display driver chips are the display driver chips shown in fig. 1B and include a synchronization signal input interface 15 and a synchronization signal output interface 16, and the display driver chips are cascaded through the synchronization signal output interface.
As shown in fig. 9, the display driver chips include a master display driver chip 402 and at least one slave display driver chip 403. The master display driver chip 402 and the slave display driver chip 403 may be determined by configuration information, the configuration information includes a second working mode, which is a different working state of the current display driving chip compared with other display driving chips, for example, the second working mode includes a master driving mode and a slave driving mode, then the current display driving chip determines that the display driving chip is the main display driving chip or the slave display driving chip according to the main driving death and the slave driving mode in the second working mode in the configuration information, for example, when the second working mode is the main driving mode, the current display driving chip determines itself to be the master display driving chip according to the configuration information, and when the second working mode is the slave driving mode, the current display driving chip determines itself to be the slave display driving chip according to the configuration information.
And the synchronous signal output interface of each main display driving chip is connected with the synchronous signal input interface of at least one slave display driving chip.
In order to more clearly understand the LED display panel 400 of the present embodiment, the operation thereof will be illustrated with reference to fig. 3A to 5 and 9.
The LED display panel 400 is powered on, and a plurality of display driving chips determine a main display driving chip 402 and at least one slave display driving chip 403 according to a second working mode in the configuration information, wherein a synchronous output interface of the main display driving chip is connected with a synchronous input interface of the at least one slave display driving chip; as shown in fig. 3A, 3B and 9, when the current display driving chip is determined as the main display driving chip according to the second operating mode, the driving control circuit in the main display driving chip generates sub-synchronization information according to the configuration information and the gray scale clock signal and sends the sub-synchronization information to the double synchronization circuit, the double synchronization circuit generates a double synchronization signal or an internal frame synchronization signal and sends the double synchronization signal or the internal frame synchronization signal to the driving control circuit in the main display driving chip, and simultaneously, the double synchronization signal or the internal frame synchronization signal is sent to the synchronization signal input interface of at least one slave display driving chip connected to the main display driving chip through the synchronization signal output interface. That is, the master display driving chip sends a double synchronization signal or an internal frame synchronization signal to the slave display driving chip connected to the master display driving chip, and when the slave display driving chip is not connected to the master display driving chip, the slave display driving chip does not receive the double synchronization signal or the internal frame synchronization signal.
As shown in fig. 4 and 9, when the current display driving chip is determined as the slave display driving chip according to the second operation mode, and the current slave display driving chip is determined as the double synchronization mode according to the configuration information, the double synchronization signal detection circuit 135 in the double synchronization circuit 13 in the current slave display driving chip receives the double synchronization signal, which is sent by the master display driving chip cascaded with the slave display driving chip through the synchronization signal output interface 16, through the synchronization signal input interface 15. As shown in fig. 5, the current slave display driver chip determines the frame synchronization mode according to the configuration information, and the frame synchronization signal detection circuit in the current slave display driver chip receives the internal frame synchronization signal through the synchronization signal input interface 16 to the synchronization signal output interface 15 of the upper-level master display driver chip cascaded with the slave display driver chip. That is, when the current display driving chip is the slave display driving chip, the signal received by the current display driving chip is sent through the upper level of the master display driving chip which is connected with the current display driving chip.
The working principle of the plurality of display driver chips determined as the frame synchronization mode or the double synchronization mode according to the first working mode is similar to the working principle of the display driver chip described in the first embodiment, and details are not repeated here.
Furthermore, as shown in fig. 10, the plurality of display driving chips are determined as a plurality of main display driving chips 402 and a plurality of slave display driving chips 403 according to the configuration information, the synchronization signal output interface of each main display driving chip 402 in the plurality of main display driving chips 402 is connected to the synchronization signal input interface of at least one slave display driving chip 403, that is, each main display driving chip is connected to at least one slave display driving chip, and outputs a double synchronization signal or an internal frame synchronization signal to at least one slave display driving chip of the main display driving chip cascade connection through the synchronization signal output interface of the main display driving chip.
Each of the plurality of main display driving chips 402 is connected to at least one slave display driving chip 403, and the working principle of the plurality of main display driving chips and the plurality of slave display driving chips is similar to that of the single main display driving chip and the at least one slave display driving chip connected to the single main display driving chip in fig. 9, and details are not repeated here.
The frame synchronization signal is issued through a display control card, for example; the display control card may be used to output display data, configuration information and frame synchronization signals, and for example, it uses a hardware structure similar to a receiving card, a scan card or a module controller in the mature LED display control technology Field, that is, a Programmable logic device such as an FPGA (Field Programmable Gate Array) device.
In addition, it should be understood that the foregoing embodiments are merely exemplary of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and used in combination without conflict between technical features and structures and without departing from the purpose of the present invention.
It should be noted that, in the foregoing embodiment of the present invention, a single display driving circuit is used as an example to implement the gray scale of multiple color components, but the embodiment of the present invention is not limited thereto, and a single display driving circuit may be designed to implement the gray scale of only a single color component, so that three different display driving circuits may be used to implement the gray scale data of R, G, B three color components.
In addition, it should be understood that the disclosed system, apparatus and method may be implemented in other ways in several embodiments provided by the present invention. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A display driver chip, comprising:
a synchronous signal input interface;
a gradation clock generating circuit;
a drive control circuit connected to the gray scale clock generating circuit;
the double-synchronous circuit is connected with the gray clock generating circuit, the driving control circuit and the synchronous signal input interface;
the constant current driving circuit is connected with the driving control circuit;
wherein, the gray clock generating circuit is used for generating a gray clock signal;
the driving control circuit is used for receiving display data and configuration information and generating sub-synchronization information according to the configuration information and the gray clock signal;
the double-synchronous circuit receives a frame synchronous signal through the synchronous signal input interface and generates a double-synchronous signal according to the gray clock signal, the frame synchronous signal and the sub-synchronous information;
the drive control circuit generates a pulse width modulation signal according to the double synchronous signal, the configuration information and the display data and sends the pulse width modulation signal to the constant current drive circuit;
and the constant current driving circuit generates a driving current according to the pulse width modulation signal.
2. The display driver chip of claim 1, further comprising:
and the synchronous signal output interface is used for outputting the double synchronous signals generated by the double synchronous signal circuit to at least one cascaded next-stage display driving chip.
3. The display driver chip of claim 2, wherein the double synchronization circuit comprises:
a frame synchronization detection circuit receiving the frame synchronization signal through the synchronization signal input interface;
the sub-synchronous signal generating circuit is connected with the driving control circuit;
a double-synchronous signal generating circuit connected with the sub-synchronous signal generating circuit and the frame synchronous detecting circuit;
the double-synchronous detection circuit is connected with the double-synchronous signal generation circuit and the synchronous signal input interface; and
the synchronous mode selection circuit is connected with the frame synchronous detection circuit, the double synchronous detection circuit and the drive control circuit;
the sub-synchronous signal generating circuit is used for generating sub-synchronous signals according to the sub-synchronous information and the gray scale clock signals; the frame synchronization detection circuit is used for generating an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal; the double-synchronous signal generating circuit is used for carrying out superposition processing on the sub-synchronous signal and the internal frame synchronous signal to obtain a double-synchronous signal; the double synchronous detection circuit is used for detecting and identifying the double synchronous signals; the synchronous mode selection circuit is used for selecting the identified double synchronous signals or the internal frame synchronous signals according to the configuration information transmitted by the drive control circuit and sending the double synchronous signals or the internal frame synchronous signals to the drive control circuit.
4. The display driver chip of claim 3,
the drive control circuit is also used for determining a first working mode of the display drive chip according to the configuration information;
when the first working mode of the display driving chip is a frame synchronization mode, the synchronization mode selection circuit outputs the internal frame synchronization signal generated by the frame synchronization detection circuit to the driving control circuit;
and when the first working mode of the display driving chip is a double-synchronous mode, the synchronous mode selection circuit outputs a double-synchronous signal identified by the double-synchronous detection circuit to the driving control circuit.
5. The display driver chip of claim 3,
the drive control circuit is also used for determining a second working mode of the display drive chip according to the configuration information;
when the second working mode of the display driving chip is a main driving mode, the double synchronous detection circuit identifies the double synchronous signals generated by the double synchronous signals and sends the double synchronous signals to the synchronous mode selection circuit, and the synchronous mode selection circuit outputs the double synchronous signals identified by the double synchronous detection circuit to at least one slave display driving chip cascaded with the main display driving chip through the synchronous signal output interface;
when the second working mode of the display driving chip is a slave driving mode, the double synchronous detection circuit in the at least one slave display driving chip identifies the double synchronous signals output by the cascaded master display driving chip and then sends the double synchronous signals to the synchronous mode selection circuit in the at least one slave display driving chip, and the synchronous mode selection circuit in the at least one slave display driving chip outputs the double synchronous signals identified by the double synchronous detection circuit in the at least one slave display driving chip to the driving control circuit of the at least one slave display driving chip.
6. The display driver chip of any of claims 1 to 5, wherein the driving control circuit is further configured to: and determining the sub-refreshing times of the display driving chip according to the gray scale clock signal and the configuration information, generating sub-synchronization information according to the sub-refreshing times, and sending the sub-synchronization information to the double-synchronization circuit.
7. An LED display panel, comprising:
an LED pixel array comprising a plurality of LED pixel points and each of the LED pixel points comprising a plurality of LEDs; and
a plurality of display driving chips according to any one of claims 1 or 6, wherein the constant current driving circuit of the display driving chip is connected with the LED pixel array.
8. An LED display panel, comprising:
an LED pixel array comprising a plurality of LED pixel points and each of the LED pixel points comprising a plurality of LEDs; and
a plurality of display driver chips as claimed in any one of claims 2 to 5, wherein the constant current driver circuits of the display driver chips are connected to the LED pixel array.
9. The LED display panel of claim 8, wherein the plurality of display driver chips are cascaded through a synchronization signal output interface;
the display driving chips comprise a main display driving chip and at least one slave display driving chip, and a synchronous signal output interface of the main display driving chip is connected with a synchronous signal input interface of the at least one slave display driving chip.
10. The LED display panel of claim 8, wherein the plurality of display driver chips are cascaded through a synchronization signal output interface;
the display driving chips comprise a plurality of main display driving chips and a plurality of auxiliary display driving chips, and a synchronous signal output interface of each main display driving chip is connected with a synchronous signal input interface of at least one auxiliary display driving chip.
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