CN111586937A

CN111586937A - LED driving chip and cascade driving circuit

Info

Publication number: CN111586937A
Application number: CN202010608339.5A
Authority: CN
Inventors: 林斌斌; 黄梅芳
Original assignee: Shenzhen Jueming Technology Co ltd
Current assignee: Shenzhen Jueming Technology Co ltd
Priority date: 2020-06-29
Filing date: 2020-06-29
Publication date: 2020-08-25

Abstract

The embodiment of the invention provides an LED driving chip and a cascade driving circuit. The LED driving chip includes: the data coding and decoding modules are used for receiving input data input by the superior element and decoding the input data; the display output module is electrically connected with the data coding and decoding modules in sequence, and is used for receiving the decoded display data sent by the data coding and decoding modules when the input data are display data, so as to control the LED lamp to display according to the decoded display data, and achieve the effect of decoding the input data when the data coding and decoding modules are abnormal.

Description

LED driving chip and cascade driving circuit

Technical Field

The embodiment of the invention relates to the technical field of Light Emitting Diodes (LEDs), in particular to an LED driving chip and a cascade driving circuit.

Background

With the rapid development of LEDs, more and more kinds of LED driving chips are coming up.

At present, a common LED driving chip only has one data coding and decoding module. For a single data coding and decoding module, the input data is input in a single path, and the LED driving chip only decodes the input data in the single path.

However, for the LED driving chip of a single data codec module, if the single data codec module is abnormal, the data cannot be decoded normally.

Disclosure of Invention

The embodiment of the invention provides an LED driving chip and a cascade driving circuit, which can realize the effect of decoding input data when a data coding and decoding module is abnormal.

In a first aspect, an embodiment of the present invention provides an LED driving chip, including:

the data coding and decoding modules are used for receiving input data input by the superior element and decoding the input data;

and the display output module is electrically connected with the data coding and decoding modules in sequence, and is used for receiving the decoded display data sent by the data coding and decoding modules when the input data is display data so as to control the LED lamp to display according to the decoded display data.

Optionally, the output end of the LED driving chip is connected in series with a lower LED driving chip, and each data encoding and decoding module is further configured to send output data to the lower LED driving chip, where the output data is used as input data of the lower LED driving chip.

Optionally, the multiple data encoding and decoding modules sequentially receive the display data sent by the superior element according to a preset time interval;

and the display output module sequentially receives the display data sent by the data coding and decoding modules.

Optionally, the display data is one frame of image data of a video to be displayed, and the preset time interval is a ratio of a continuous display time of each frame of image data to the number of operations of the data encoding and decoding modules.

Optionally, the method further includes:

the data type judgment module is respectively connected with the data coding and decoding modules and is used for judging the data type corresponding to the input data;

and when the input data is display data, sending the display data to the display output module.

Optionally, when the input end of the LED driving chip is connected in series with the previous LED driving chip, the previous element includes a target previous element and the previous LED driving chip;

one of the data coding and decoding modules is used as a reference data coding and decoding module to receive the input data sent by a target upper-level element, wherein the target upper-level element is different from the upper-level LED driving chip;

and a residual data coding and decoding module in the plurality of data coding and decoding modules receives the input data sent by the upper-stage LED driving chip, wherein the residual data coding and decoding module is a data coding and decoding module in the plurality of data coding and decoding modules except the reference data coding and decoding module.

Optionally, the LED driving chip further includes:

the code rate detection module is used for detecting a code rate parameter corresponding to the display data when the input data is the display data;

the data buffer module is used for caching the display data;

the data encoding and decoding module is specifically configured to receive the code rate parameter sent by the code rate detecting module, extract the display data from the data buffering module, and decode the display data according to the code rate parameter to obtain the decoded display data.

Optionally, the data encoding and decoding module is specifically configured to determine a decoding threshold associated with the code rate parameter, and decode the display data according to the decoding threshold, where the decoding threshold is 1/(a preset coefficient rate parameter), and the preset coefficient is greater than 1;

if the display data is high-level data which is larger than the decoding threshold, the logic of the display data is 1;

and if the display data is high-level data smaller than the decoding threshold, the logic of the display data is 0.

Optionally, the LED driving chip further includes:

and the filtering module is arranged in front of the data coding and decoding module and used for filtering the input data and sending the filtered input data to the data coding and decoding module.

In a second aspect, an embodiment of the present invention provides a cascade driving circuit, which includes n LED driving chips according to any embodiment of the present invention, where the n LED driving chips are connected in series to form the cascade driving circuit.

The LED driving chip comprises a plurality of data coding and decoding modules, wherein each data coding and decoding module is used for receiving input data input by a superior element and decoding the input data; the display output module is electrically connected with the plurality of data coding and decoding modules in sequence, and is used for receiving the decoded display data sent by the data coding and decoding modules when the input data is the display data so as to control the LED lamp to display according to the decoded display data, so that the problem that the data cannot be normally decoded if the single data coding and decoding module is abnormal for an LED driving chip of the single data coding and decoding module is solved, and the effect of decoding the input data when the data coding and decoding module is abnormal is realized.

Drawings

Fig. 1 is a schematic structural diagram of an LED driving chip according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a cascade of a plurality of LED driving chips according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another cascade of a plurality of LED driving chips according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another cascade of a plurality of LED driving chips according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another LED driving chip according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a cascade driving circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Wherein the terms "first position" and "second position" are two different positions.

In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Fig. 1 is a schematic structural diagram of an LED driving chip according to an embodiment of the present invention. As shown in fig. 1, an embodiment of the present invention provides an LED driving chip 100, which includes a plurality of data encoding/decoding modules 110 and a display output module 120. The LED driving chip 100 of the present embodiment is used for decoding input data through a plurality of data encoding and decoding modules 110, wherein:

each of the data encoding and decoding modules 110 is configured to receive input data input by the upper level element and decode the input data;

the display output module 120 is electrically connected to the plurality of data encoding and decoding modules 110 in sequence, and the display output module 120 is configured to receive the decoded display data sent by the data encoding and decoding modules 110 when the input data is display data, so as to control the LED lamp to display according to the decoded display data.

In the present embodiment, each data codec module 110 is configured to receive input data input by an upper component and decode the input data. The input data may be display data, configuration data, other data, and the like, and is not limited in particular here. The display data is used for controlling the LED lamp to display, and the configuration data is used for configuring parameters of the LED driving chip 100, such as the number of operations performed by the configuration data codec module 110. When the input data is display data, the display output module 120 receives the decoded display data to control the LEDs to display. Optionally, the display output module 120 may be a DC display output module 120 in a DC dimming manner, and may also be a PWM display output module 120, which is not limited herein. DC dimming is to change the brightness of the screen by increasing or decreasing the power of the circuit of the screen panel, and since the power is equal to the voltage and the current, the brightness of the screen can be changed by only changing the voltage or the current. Taking the PWM display output module 120 as an example, the PWM display output module 120 outputs the PWM modulation format to the LED lamp for displaying, and converts the decoded display data into a PWM signal to control the LED lamp to display. The number of the data codec modules 110 can be increased according to the needs, and is not limited in particular. The plurality of data codec modules 110 means that the number of the data codec modules 110 is at least two.

It can be understood that, regardless of whether the input data is configuration data or display data, when a part of the plurality of data codec modules 110 is damaged or abnormal, as long as one data codec module 110 is normal, the input data can be normally received and normally decoded, and then configuration or display is performed.

In one embodiment, optionally, the LED driving chip 100 further includes a data type determining module 130. Wherein:

the data type determining module 130 is respectively connected to the data encoding and decoding modules 110, and is configured to determine a data type corresponding to the input data; when the input data is display data, the display data is sent to the display output module 120.

In this embodiment, how to determine the data type corresponding to the input data is not specifically limited, and may be determined according to an existing scheme. For example, the input data is followed by a Check code, which is determined by a Cyclic Redundancy Check (CRC). When the input data is display data, the data type determining module 130 sends the display data to the display output module 120, so that the display output module 120 controls the LED lamp to display.

In an embodiment, optionally, the plurality of data encoding and decoding modules 110 sequentially receive the display data sent by the upper level element according to a preset time interval; the display output module 120 sequentially receives the display data sent by the data encoding and decoding modules 110.

Optionally, the display data is a frame of image data of the video to be displayed, and the preset time interval is a ratio of a continuous display time of each frame of image data to the number of operations of the data encoding and decoding modules 110.

In the present embodiment, the upper-level element may be a controller, a previous-level LED driving chip 100 and/or a previous-n-level LED driving chip 100, etc., which is determined according to specific situations and is not particularly limited herein. It can be understood that, by sequentially receiving the display data sent by the upper-level element by the plurality of data codec modules 110, the display quality of the picture can be improved without improving the performance of the single data codec module 110.

For example, the video frame rate is 120, and assuming that the highest-energy encoding/decoding code stream of the data encoding/decoding module 110 is 800KHz, then 24 × 1.25US × 1080 is 32.4ms, that is, about 30 frame rates, that is, when 1080 LED driving chips 100 are cascaded, a single channel can only decode 30 frames of pictures, and a conventional single channel chip can decode 30 frames only. However, according to the technical solution of this embodiment, when the number of the plurality of data codec modules 110 is 4, 4 × 30 frames (a single data codec module 110) is 120 frames. On the premise of not improving the performance of a single data encoding and decoding module 110, that is, on the premise of not improving the highest encoding and decoding code stream of the data encoding and decoding module 110 to 800KHz, the 4 data encoding and decoding modules 110 can improve the display quality of the picture, and the picture display with the frame rate of 120 is achieved.

It should be noted that the plurality of data coding and decoding modules 110 sequentially receive the display data sent by the upper-level element according to a preset time interval, where the preset time interval is a ratio of a continuous display time of each frame of image data to a working quantity of the plurality of data coding and decoding modules 110. For example, assuming that each frame of image data is 32ms, there are 4 data codec modules 110 and 4 data codec modules 110 operate, a first frame of display data is sent to a first data codec module 110 first, a second frame of display data is sent to a second data codec module 110 after (32/4) ═ 8ms, a third frame of display data is sent to a third data codec module 110 after 8ms, and a fourth frame of display data is sent to a fourth data codec module 110 after 8 ms. It can be understood that, when there are 4 data encoding and decoding modules 110, each frame of data is 32ms, when there are 1 data encoding and decoding module 110, a frame of data is refreshed every 32ms, and the frame rate is about 30, but when there are 4 data encoding and decoding modules 110, a frame of data can be refreshed every 8ms, so that the display frame rate of the video is improved. It is understood that when the number of operations of the data codec module 110 is 2, one frame of image data is transmitted at an interval 32/2 of 16 ms.

In one embodiment, optionally, the output end of the LED driving chip 100 is connected in series with the lower LED driving chip 100, and each of the data codec modules 110 is further configured to send output data to the lower LED driving chip 100, where the output data serves as input data of the lower LED driving chip 100.

Specifically, the plurality of LED driving chips 100 form a cascade circuit in series.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a cascade of a plurality of LED driving chips 100 according to an embodiment of the present invention. As can be seen from fig. 2, the lower LED driving chip 100 of the (n-1) th LED driving chip 100 is the nth LED driving chip 100, that is, the lower LED driving chip 100 is the next LED driving chip 100, the current LED driving chip 100 is connected to the next LED driving chip 100 in multiple ways, and the data encoding and decoding module 110 of the current LED driving chip 100 is connected to the data encoding and decoding module 110 of the next LED driving chip 100 in a one-to-one correspondence manner.

Referring to fig. 3, fig. 3 is a schematic structural diagram of another cascade of a plurality of LED driving chips 100 according to an embodiment of the present invention. As can be seen from fig. 3, the lower LED driving chip 100 of the (n-2) th LED driving chip 100 includes the (n-1) th LED driving chip 100 and the nth LED driving chip 100, that is, the lower LED driving chip 100 includes the lower LED driving chip 100 and the lower nth LED driving chip 100.

In one embodiment, one of the data codec modules 110 serves as a reference data codec module 110 to transmit data to the next n-level LED driving chip 100, and the remaining data codec modules 110 correspondingly transmit data to the next LED driving chip 100.

Correspondingly, when the input end of the LED driving chip 100 is connected in series with the previous LED driving chip 100, the previous element includes a target previous element and the previous LED driving chip 100; one of the plurality of data encoding and decoding modules 110 is used as a reference data encoding and decoding module 110 to receive the input data sent by a target upper-level element, wherein the target upper-level element is different from the upper-level LED driving chip 100; the remaining data codec module 110 of the plurality of data codec modules 110 receives the input data sent by the previous LED driver chip 100, wherein the remaining data codec module 110 is a data codec module 110 of the plurality of data codec modules 110 except for the reference data codec module 110.

In the present embodiment, the target upper-level element is the upper n-level LED driving chip 100. As can be seen from fig. 3, the upper-level element of the nth LED driving chip 100 includes the (n-1) th LED driving chip 100 and the (n-2) th LED driving chip 100, i.e., the upper-level element includes the upper-level LED driving chip 100 and the upper-n-level LED driving chip 100. The reference data coding and decoding module 110 of the current-stage LED driving chip 100 is correspondingly connected to the reference data coding and decoding module 110 of the upper n-stage LED driving chip 100, and the remaining data coding and decoding module 110 of the current-stage LED driving chip 100 is correspondingly connected to the remaining data coding and decoding module 110 of the upper LED driving chip 100.

It can be understood that, by receiving the data sent by the reference data codec module 110 of the current-stage LED driving chip 100 from the upper n-stage reference data codec module 110 and sending the data to the reference data codec module 110 of the lower n-stage LED driving chip 100, even if the upper-stage LED driving chip 100 fails and cannot send the data, the current-stage LED driving chip 100 can also receive the data sent by the upper n-stage driving chip, so as to ensure that the current-stage LED driving chip 100 can normally display, and only some display quality is lost.

Referring to fig. 4, fig. 4 is a schematic structural diagram of another cascade of a plurality of LED driving chips 100 according to an embodiment of the present invention. As can be seen from fig. 4, the reference data codec module 110 of each stage of the LED driving chip 100 is correspondingly connected to the controller 200. In the present embodiment, the target upper-level element is the controller 200. It can be understood that the LED driving chip 100 of the current stage receives the data sent by the controller 200 through the reference data encoding and decoding module 110, and the remaining data encoding and decoding modules 110 receive the data sent by the LED driving chip 100 of the previous stage, so long as the controller 200 is not abnormal and any one LED driving chip 100 is damaged, the remaining LED driving chips 100 can also be ensured to display normally.

In one embodiment, optionally, if a data codec module 110 of the nth LED driving chip 100 is damaged, the data of the branch cannot be transmitted backward. At this time, the controller 200 may send a data detection instruction to each data codec module 110 at each power-on or specified period, when the LED driver chip 100 receives the instruction, each LED driver chip 100 returns a response message from the data codec module 110, the response message may be an address of each LED driver chip 100, and when the controller 200 receives the response message, it is determined that the branch has no address message after the nth address, the channel is incorrect, if all addresses of the LED driver chips 100 are received, the channel is normal, if the channel is incorrect, the controller 200 does not send display data of the branch, and averages the average frame number to keep the picture normal, and the phenomenon that the frame rates of the front and rear chips are asynchronous does not occur.

Referring to fig. 5, fig. 5 is a schematic structural diagram of another LED driving chip 100 according to an embodiment of the present invention. In this embodiment, the LED driving chip 100 further includes a code rate detecting module 140 and a code rate detecting module 140, wherein:

the code rate detecting module 140 is configured to detect a code rate parameter corresponding to the display data when the input data is the display data;

the code rate detection module 140 is configured to cache the display data;

the data encoding and decoding module 110 is specifically configured to receive the code rate parameter sent by the code rate detecting module 140, extract the display data from the data buffering module 150, and decode the display data according to the code rate parameter to obtain the decoded display data.

In this embodiment, the code rate parameter is a specific code rate reference value, for example, the code rate parameter is 800KHz (hertz) or 1.6MHz, and the like, and is not limited herein, and is determined according to the code rate of the previous stage element for sending the display data. The data transmission of the present embodiment may be controlled by a clock signal.

In this embodiment, specifically, the previous-stage element sends the display data to the current-stage LED driving chip 100 in a dynamic rate manner, and when the current-stage LED driving chip 100 receives the display data, the rate detection module 140 detects a rate parameter corresponding to the display data, and the data buffering module 150 buffers the display data. After the detection of the code rate detecting module 140 is completed, the data encoding and decoding module 110 extracts the display data from the data buffering module 150, decodes the display data according to the code rate parameter, and sends the decoded display data to the display output module 120, so that the display output module 120 can control the LED lamp to display according to the decoded display data.

For example, a video file of a dynamic motion image has a first half with a frame rate of 60 and a second half with a frame rate of almost still picture of 10. Then, a common controller decodes the video and sends the decoded video to the LED driving chips 100100 at a fixed rate of 800KHz for display, each LED driving chip 100100 needs to acquire 24-bit data for calculation, when 1080 chips are cascaded, high-definition display can be realized, and the frame rate is 1S/(1080 × 24 × 1.25US) ═ 30.86 frames. The controller may transmit the display data with different code rates according to the requirement of the picture display, for example, when the picture is highly dynamic, the display data is transmitted with a code rate of 1.6MHz, and when the picture is almost static, the display data is transmitted with a code rate of 266 KHz. In addition, the controller sends display data in a dynamic code rate manner, the LED driving chip 100100 performs adaptive decoding, a high dynamic frame rate can transmit a larger data amount by using a high code rate, a high frame rate frame is displayed, and a low code rate transmission is used when a still or slow moving frame is displayed, thereby saving power consumption.

In this embodiment, specifically, the present stage LED driving chip 100 sends data to the next stage LED driving chip 100. It should be noted that the data is sent to the next-stage LED driving chip 100 through the data encoding and decoding module 110 of the LED driving chip 100. Specifically, after the data is decoded, the data coding and decoding module 110 re-codes the data required by the remaining LED driving chip 100 and then sends the data to the next LED driving chip 100, so that the remaining LED driving chip 100 can also receive the data normally.

In an embodiment, the LED driving chip 100 further includes a filtering module, which is disposed before the code rate detecting module and the data buffering module, and is configured to filter the display data and send the filtered display data to the code rate detecting module and the data buffering module. It should be noted that the data to be coded to the following LED driving chip 100 should be sent with appropriate 0 and 1 data signals on the premise that the 0 code and 1 code are as far away from the threshold as possible and are not filtered out by the appropriate glitch. For example, when the decoding threshold is 500ns, then code 0 is sent with a high time of 250ns in the middle and code 1 is sent with a high time of 750ns in the middle.

In addition, when data is transmitted from the previous LED driving chip 100 to the next LED driving chip 100 through the cascade line, due to a load of a transmission medium, a transmitted data signal is clipped, so that a low level time or a high level time of the data signal is narrowed, and if the clipping is too large, codes 0 and 1 may be considered as glitch noise to be filtered out or errors occur, such as 0 to 1, or 1 to 0, and thus the middle high level time needs to be adjusted. For error codes, the display screen can be caused to flash, and the playing effect is very poor. Specifically, when clipping is to clip a high level, the high level is narrowed and the low level is widened; when clipping is clipping low, it narrows the low level and widens the high level. The specific clipping method is related to the operation method, and the high level time and the low level time may be adjusted according to the type of clipping without being limited thereto.

Specifically, when the clipping is to clip the low level and the binary code is 0, the high level time is adjusted to make the high level time far away from the decoding threshold and the difference between the high level time and the decoding threshold is larger than the clipping amplitude; when the clipping is to clip the low level and the binary code is 1, adjusting the high level time to make the high level time close to the decoding threshold and the high level time larger than the decoding threshold; when clipping is to cut high level and the binary code is 0, adjusting the high level time to make the high level time close to the decoding threshold and the high level time smaller than the decoding threshold; when clipping is clipping high level and the binary code is 1, the high level time is adjusted to make the high level time far away from the decoding threshold and the difference between the high level time and the decoding threshold is larger than the clipping amplitude.

For example, when the decoding threshold is 500ns, a high time of 250ns is generally used as the data signal of code 0, and a high time of 750ns is used as the data signal of code 1. When the clipping is to lower the level and the coding is 0, the high level time can be adjusted to 150ns for transmission; when clipping is clipping low level and coding is 1, then the high level time can be adjusted to 650 ns; when clipping is clipping high level and coding is 0, the high level time can be adjusted to 350 ns; when clipping is clipping high and the code is 1, then the high time can be adjusted to 850 ns.

It is understood that a configuration data may be sent before transmitting the data to inform each LED driving chip 100 of the operation mode, so that the LED driving chip 100 re-encodes the data according to the clipping mode related to the operation mode and sends the data to the next LED driving chip 100.

In an embodiment, the data encoding and decoding module 110 is specifically configured to determine a decoding threshold associated with the code rate parameter, and decode the display data according to the decoding threshold.

Specifically, the decoding threshold refers to a threshold for decoding the display data, and is associated with the code rate parameter. The decoding threshold is 1/(the preset parameter code rate parameter), wherein the preset coefficient is greater than 1, that is, 1/the preset coefficient is less than 1. For example, the 1/preset coefficient may be 1/2, 1/3 or the like which is close to 1/2, for example, a number which is not more than 1/6 different from 1/2, or the like, and may be set as needed, and is not particularly limited herein. Preferably, the decoding threshold is 1/(2 × rate parameter). Illustratively, when the code rate parameter is 1Mbps, the period is 1us (microseconds), the preset coefficient is 2, the decoding threshold is 500ns (nanoseconds), and when the high level time of the data signal of the display data is 250ns less than 500ns in one time period, the binary code is 0; when the high level time is 750ns and is more than 500ns, the binary code is 1.

In an embodiment, optionally, the LED driving chip 100 further includes a filtering module 160, where the filtering is disposed before the data codec module 110, and is configured to filter the input data and send the filtered input data to the data codec module 110.

It is understood that the accuracy of decoding can be improved by providing the filtering module 160 before the data codec module 110. According to the technical scheme of the embodiment of the invention, the LED driving chip comprises a plurality of data coding and decoding modules, and each data coding and decoding module is used for receiving input data input by the superior element and decoding the input data; the display output module is electrically connected with the data coding and decoding modules in sequence, and is used for receiving the decoded display data sent by the data coding and decoding modules when the input data is the display data so as to control the LED lamp to display according to the decoded display data. In addition, the plurality of data coding and decoding modules sequentially receive the display data sent by the superior element according to the preset time interval, and the display quality of the picture is improved on the premise of not improving the performance of a single data coding and decoding module.

Fig. 6 is a schematic structural diagram of a cascade driving circuit according to an embodiment of the present invention. As shown in fig. 6, an embodiment of the present invention provides a cascade driving circuit 10, which includes n LED driving chips 100, where the n LED driving chips 100 are connected in series to form the cascade driving circuit 10. Wherein:

each LED driving chip 100 includes a plurality of data encoding and decoding modules 110 and a display output module 120;

The first stage LED driving chip 100 of the cascade driving circuit 10 is connected to the controller 200. In the present embodiment, each data codec module 110 is configured to receive input data input by an upper component and decode the input data. The input data may be display data, configuration data, other data, and the like, and is not limited in particular here.

In one embodiment, optionally, one end of each of the LED driving chips 100 is electrically connected to the positive electrode of the common power line;

the other end of each of the LED driving chips 100 is electrically connected to the cathode of the common power line;

wherein, the anode and the cathode of the common power line are respectively connected to the controller 200, and the controller 200 is configured to transmit data to each of the LED driving chips 100 at the anode of the common power line in the form of an initial carrier signal.

In the present embodiment, data is transmitted to each LED driving chip 100 in the form of an initial carrier signal at the positive electrode of the common power line, and each LED driving chip 100 may control the LED lamp to display or configure the operating state of the LED driving chip 100 according to the received data. It can be understood that, by transmitting data to each LED driving chip 100 in the form of an initial carrier signal at the positive electrode of the common power line, the complexity is lower, and even if one of the LED driving chips 100 is damaged, the transmission of the other LED driving chips 100 is not affected, thereby improving the stability of data transmission.

For example, when the LED driving circuit 100 transmits display data to display a picture, when one of the LED driving chips 100 is damaged, only the LED driving chip 100 cannot drive the LED lamp to display, and the other LED driving chips 100 can normally drive the LED lamp to display, and the failed LED driving chip 100 only turns off the LED lamp, and the failed LED driving chip can be quickly located to a dead spot.

It should be noted that the data of this embodiment may be configuration data and/or display data, that is, the data may be only the display data or the configuration data, or the display data and the configuration data may be sent together. Wherein the configuration data is used for configuring the operating state of the LED driving chip 100. Optionally, the configuration data may be used to configure one or more of gamma coefficient, current adjustment, and grayscale accuracy. The display data is used for driving the LED driving chip 100 to control the LED lamp to display. The n LED driving chips in the LED driving circuit 100 of the present embodiment are not cascaded.

In the present embodiment, each LED driving chip 100 in the LED driving circuit 100 is configured with an address in advance. It can be understood that the pre-configured address may be a fixed address that is initialized before the LED driver chips 100 leave the factory, and thus no cascade connection is required between the LED driver chips 100; in addition, the pre-configured address may not be initialized to a fixed address before shipping, and the LED driving chip 100 needs to perform address initialization by cascade connection. According to the technical scheme of the embodiment of the invention, the cascade drive circuit comprises an LED drive chip, the LED drive chip comprises a plurality of data coding and decoding modules, and each data coding and decoding module is used for receiving input data input by the superior element and decoding the input data; the display output module is electrically connected with the data coding and decoding modules in sequence, and is used for receiving the decoded display data sent by the data coding and decoding modules when the input data is the display data so as to control the LED lamp to display according to the decoded display data. In addition, the plurality of data coding and decoding modules sequentially receive the display data sent by the superior element according to the preset time interval, and the display quality of the picture is improved on the premise of not improving the performance of a single data coding and decoding module.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An LED driving chip, comprising:

2. The LED driving chip according to claim 1, wherein the output terminal of the LED driving chip is connected in series with a lower LED driving chip, and each of the data codec modules is further configured to transmit output data to the lower LED driving chip, wherein the output data serves as input data of the lower LED driving chip.

3. The LED driving chip according to claim 1, wherein the plurality of data encoding/decoding modules sequentially receive the display data transmitted by the upper level element at preset time intervals;

4. The LED driving chip according to claim 3, wherein the display data is a frame of image data of a video to be displayed, and the preset time interval is a ratio of a duration of display of each frame of image data to a number of operations of the plurality of data codec modules.

5. The LED driving chip according to claim 1, further comprising:

6. The LED driving chip according to claim 1, wherein when the input terminal of the LED driving chip and the previous-stage LED driving chip are connected in series, the upper-stage element includes a target upper-stage element and the previous-stage LED driving chip;

7. The LED driving chip according to claim 1, wherein the LED driving chip further comprises:

the code rate detection module is used for caching the display data;

8. The LED driving chip according to claim 7, wherein the data encoding and decoding module is specifically configured to determine a decoding threshold associated with the code rate parameter, and decode the display data according to the decoding threshold, wherein the decoding threshold is 1/(a preset coefficient rate parameter), and wherein the preset coefficient is greater than 1;

9. The LED driving chip according to claim 1, wherein the LED driving chip further comprises:

10. A cascade driving circuit, comprising n LED driving chips according to any one of claims 1 to 9, wherein the n LED driving chips are connected in series to form the cascade driving circuit.