CN114664230B - Display driving chip and LED display panel - Google Patents
Display driving chip and LED display panel Download PDFInfo
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- CN114664230B CN114664230B CN202011528641.6A CN202011528641A CN114664230B CN 114664230 B CN114664230 B CN 114664230B CN 202011528641 A CN202011528641 A CN 202011528641A CN 114664230 B CN114664230 B CN 114664230B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The embodiment of the invention discloses a display driving chip and an LED display panel. The display driving chip includes: a synchronization signal input interface; a gradation clock generation circuit; a drive control circuit connected to the gradation clock generation circuit; the double synchronous circuit is connected with the gray scale clock generating circuit, the driving control circuit and the synchronous signal input interface; and the constant current driving circuit is connected with the driving control circuit. According to the embodiment of the invention, the double synchronous circuits are added in the display driving chip, so that the display picture output by the display driving chip can achieve a synchronous effect, the working condition and the influence of manufacturing of the display driving chip are improved, and the display effect is improved.
Description
Technical Field
The invention relates to the technical field of display control, in particular to a display driving chip and an LED display panel.
Background
At present, the LED display device is applied to various fields due to the advantages of low cost, low power consumption, high visibility, free assembly and the like. Meanwhile, with the popularization of the application of the LED display device, the requirements of people on the display quality of the LED display device are also higher and higher, so how to improve the display quality of the LED display device has become a research hot spot in the field. As the application scenes of LEDs are more and more, the synchronicity of the display pictures of LEDs is more and more focused.
The LED display control card transmits the frame synchronization signal sent by the upper computer to the driving chip and controls the driving chip to output, so that the display picture of each frame is ensured to be synchronously displayed. However, since the manufacturing of the driving chips and the operating conditions of the driving chips are different, the gray scale clock periods generated by the different driving chips may be deviated. Under the control of the gray scale clock, pulse width modulation signals and line feed signals generated by different driving chips can not be synchronized among the different driving chips, and finally, the display images are not synchronized, so that the display effect is poor.
Disclosure of Invention
Therefore, in order to overcome at least part of the defects and shortcomings in the prior art, the embodiment of the invention provides a display driving chip and an LED display panel so as to improve the display effect.
In one aspect, an embodiment of the present invention provides a display driving chip, including: a synchronization signal input interface; a gradation clock generation circuit; a drive control circuit connected to the gradation clock generation circuit; the double-synchronization generating circuit is connected with the gray scale clock generating circuit, the driving control circuit and the synchronous signal input interface; a constant current drive circuit connected to the drive control circuit; the gray scale clock generation circuit is used for generating a gray scale clock signal; the driving control circuit is used for receiving display data and configuration information and generating sub-synchronous information according to the configuration information and the gray scale clock signal; the double synchronization circuit receives a frame synchronization signal through the synchronization signal input interface and generates a double synchronization signal according to the gray scale clock signal, the frame synchronization signal and the sub synchronization information; the driving control circuit generates a pulse width modulation signal according to the double synchronous signals, the configuration information and the display data and sends the pulse width modulation signal to the constant current driving circuit; the constant current driving circuit generates driving current according to the pulse width modulation signal and outputs the driving current.
According to the technical scheme, the drive control circuit receives the configuration information and the display data, then the drive control circuit sends the sub-synchronous information to the double-synchronous circuit, the double-synchronous circuit generates the double-synchronous signal according to the sub-synchronous information, the frame synchronous signal and the gray scale clock signal, and sends the double-synchronous signal to the drive control circuit to generate the pulse width modulation signal, and then the constant current drive circuit is controlled to generate constant current output, so that the output of the display drive chip is controlled, the synchronous times of the display drive chip is increased, and the problems of asynchronous display pictures and poor display effect caused by gray scale clock deviation of the drive chip are solved.
In one embodiment of the present invention, the display driving chip further includes: and the synchronous signal output interface is used for outputting the double synchronous signals generated by the double synchronous signal circuit to at least one cascaded next-stage display driving chip.
In one embodiment of the present invention, the double synchronization circuit includes: the frame synchronization detection circuit is connected with the synchronization signal input interface to receive the frame synchronization signal; a sub-synchronization signal generation circuit connected to the drive control circuit; a double synchronization signal generating circuit connected to the sub synchronization signal generating circuit and the frame synchronization detecting circuit; the double synchronous detection circuit is connected with the double synchronous signal generation circuit and the synchronous signal input interface; and a synchronization pattern selection circuit connected to the frame synchronization detection circuit, the double synchronization detection circuit, and the drive control circuit; the sub-synchronous signal generating circuit is used for generating a sub-synchronous signal according to the sub-synchronous information and the gray scale clock signal; the frame synchronization detection circuit is used for generating an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal; the double-synchronizing signal generating circuit is used for superposing the sub-synchronizing signal and the internal frame synchronizing signal to obtain the double-synchronizing signal; the double synchronization detection circuit is used for detecting and identifying the double synchronization signals; the synchronous mode selection circuit is used for selecting the identified double synchronous signal or the internal frame synchronous signal according to the configuration information transmitted by the drive control circuit and transmitting the double synchronous signal or the internal frame synchronous signal to the drive control circuit.
In one embodiment of the present invention, the driving control circuit is further configured to determine a first operation mode of the display driving chip according to the configuration information; when the first working mode of the display driving chip is a frame synchronization mode, the synchronization mode selection circuit outputs an internal frame synchronization signal generated by the frame synchronization detection circuit to the driving control circuit; when the first working mode of the display driving chip is a double-synchronous mode, the synchronous mode selection circuit outputs the double-synchronous signal identified by the double-synchronous detection circuit to the driving control circuit.
In one embodiment of the present invention, the driving control circuit is further configured to determine a second operation mode of the display driving chip according to the configuration information; when the second working mode of the display driving chip is a main driving mode, the double synchronous detection circuit recognizes the double synchronous signals generated by the double synchronous signals and then sends the double synchronous signals to the synchronous mode selection circuit, and the synchronous mode selection circuit outputs the double synchronous signals recognized by the double synchronous detection circuit to at least one slave display driving chip cascaded with the main display driving chip through the synchronous signal output interface; when the second working mode of the display driving chip is a slave driving mode, the double synchronous detection circuit in the at least one slave display driving chip recognizes the double synchronous signals output by the cascaded master display driving chip and then sends the double synchronous signals to the synchronous mode selection circuit in the at least one slave display driving chip, and the synchronous mode selection circuit in the at least one slave display driving chip outputs the double synchronous signals recognized by the double synchronous detection circuit in the at least one slave display driving chip to the driving control circuit of the at least one slave display driving chip.
In one embodiment of the present invention, the drive control circuit is further configured to: determining the sub-refresh times of the display driving chip according to the gray scale clock signal and the configuration information, generating sub-synchronization information according to the sub-refresh times, and sending the sub-synchronization information to the double-synchronization circuit.
In another aspect, an embodiment of the present invention provides an LED display panel, including: an LED pixel array comprising a plurality of LED pixels and each of the LED pixels comprising a plurality of LEDs; and a plurality of display driving chips as described in the foregoing embodiments, wherein the constant current driving circuit of the display driving chip is connected to the LED pixel array.
In one embodiment of the present invention, the plurality of display driving chips are cascaded through a synchronization signal output interface; the display driving chips comprise a master display driving chip and at least one slave display driving chip, and a synchronous signal output interface of the master display driving chip is connected with a synchronous signal input interface of the at least one slave display driving chip.
In one embodiment of the present invention, the plurality of display driving chips are cascaded through a synchronization signal output interface; the display driving chips comprise a plurality of master display driving chips and a plurality of slave display driving chips, and a synchronous signal output interface of each master display driving chip is connected with a synchronous signal input interface of at least one slave display driving chip.
The technical scheme can have the following advantages or beneficial effects: the embodiment of the invention firstly receives configuration information and display data through the drive control circuit, then sends sub-synchronous information to the double-synchronous circuit through the drive control circuit, the double-synchronous circuit generates a double-synchronous signal according to the sub-synchronous information, an internal frame synchronous signal and a gray scale clock signal, and sends the double-synchronous signal to the drive control circuit to generate a pulse width modulation signal, and then controls the constant current drive circuit to generate constant current output, thereby controlling the output of the display drive chip, increasing the synchronous times of the display drive chip, and improving the problems of asynchronous display picture and poor display effect caused by gray scale clock deviation of the drive chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1A is a schematic circuit diagram of a display driving chip according to an embodiment of the present invention.
Fig. 1B is a schematic circuit diagram of another display driving chip according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a specific circuit structure of a dual synchronous generating circuit according to an embodiment of the present invention.
Fig. 3A is a schematic diagram of a specific circuit of a main display driving chip of a dual-synchronization generating circuit in a dual-synchronization mode according to an embodiment of the present invention.
Fig. 3B is a schematic diagram of a specific circuit of a main display driving chip of a dual-synchronization generating circuit in a frame synchronization mode according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a specific circuit of a dual-synchronization generating circuit according to an embodiment of the present invention from a display driving chip in a dual-synchronization mode.
Fig. 5 is a schematic diagram of a specific circuit of a dual-synchronization generating circuit according to an embodiment of the present invention from a display driving chip in a frame synchronization mode.
Fig. 6 is a schematic diagram of a specific circuit structure of a display driving chip according to an embodiment of the present invention.
Fig. 7 is a timing output diagram of a dual synchronization signal and a frame synchronization signal in an embodiment of the present invention.
Fig. 8 is a schematic diagram of a part of a structure of an LED display panel according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a portion of another LED display unit according to an embodiment of the present application.
Fig. 10 is a schematic diagram of a portion of another LED display unit according to an embodiment of the present application.
Description of the drawings: 10: a display driving chip; 11: a gradation clock generation circuit; 12: a drive control circuit; 13: a double synchronization circuit; 14: constant current drive circuit: 15: a synchronization signal input interface; 16: a synchronous signal output interface; 20: scanning the chip; 111: a frequency doubling circuit; 121: a command processing circuit; 122: a shift register circuit; 123: a buffer circuit; 124: a counter; 125: a gray level scattering processing circuit; 126: a channel control circuit; 131: a frame synchronization detection circuit; 132: a sub-synchronization signal generation circuit: 133: a double synchronization signal generation circuit; 134: a synchronous mode selection circuit; 135: a double synchronization detection circuit; 300: an LED display panel; 400: an LED display panel; 401: an LED pixel array; 402; a main display driving chip; 403: and driving the chip from the display.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
[ first embodiment ]
Fig. 1A is a schematic structural diagram of a display driving chip 10 according to an embodiment of the invention. As shown in fig. 1A, the display driving chip 10 includes, for example: a gradation clock generation circuit 11, a drive control circuit 12, a double synchronization circuit 13, a constant current drive circuit 14, and a synchronization signal input interface 15.
Wherein the drive control circuit 12 is connected to the gradation clock generation circuit 11; the double synchronization circuit 13 connects the gray scale clock generating circuit 11, the driving control circuit 12 and the synchronization signal input interface 15; the constant current drive circuit 14 is connected to the drive control circuit 12.
Wherein, the configuration information and the display data (shown as DIN [2:0] in FIG. 1A) can be received through other interfaces of the display driving chip, such as a data input interface; the configuration information and the display data may be sent through other chips connected to the data input interface, for example, a front-end control card (also called a receiving card) or an upper computer, which is not limited herein.
The synchronization signal input interface 15 is configured to receive a frame synchronization signal, where the frame synchronization signal may be sent through another chip connected to the synchronization signal input interface 15, for example, a front end control card (also called a receiving card) or an upper computer, and the disclosure is not limited herein. The synchronization signal input interface 15 may also receive other signals, such as a double synchronization signal or an intra frame synchronization signal, etc., and the signal received by the synchronization signal input interface 15 may be determined according to the actual connection state of the display driver chip, which is not limited herein.
Wherein the gray scale clock generating circuit 11 is used for generating a gray scale clock signal and transmitting the gray scale clock signal to the driving control circuit 12 and the double synchronization circuit 13; the gray scale clock generating circuit 11 may automatically generate the gray scale clock signal internally, or may receive the clock signal through the data input interface 15, which is not limited herein.
The drive control circuit 12 may acquire display data DIN [2 ] through a data input interface: 0] and configuration information, and generates sub-synchronization information according to the configuration information and a gray scale clock signal, and transmits the sub-synchronization information to the double synchronization circuit 13.
The configuration information may include, for example, a first operation mode, where the first operation mode includes an operation mode of the current display driver chip itself, for example, a frame synchronization mode, a double synchronization mode, and so on, and in other embodiments, the configuration information may further include, in the case of multiple display driver chips, other operation modes of the configuration display driver chip, for example, a driving mode, and so on, where the specific application is not limited; the configuration information can be information issued by the main control circuit, a receiving card (also called a display control card) or an upper computer.
The double synchronization circuit 13 receives the frame synchronization signal and the sub-synchronization information transmitted from the driving control circuit 12 through the synchronization signal input interface 15, generates the double synchronization signal according to the gray scale clock signal, the frame synchronization signal and the sub-synchronization information, and transmits the double synchronization signal to the driving control circuit 12.
The display driving chip 10 performs a complete refresh in each frame of the area currently controlled to display or performs multiple complete refreshes in each frame of the LED display screen, each complete refresh is called sub refresh, and the sub synchronization information includes sub refresh frequency information that the display driving chip needs to complete refresh when completing complete display of one frame of the area currently controlled to display; the configuration information further includes sub-refresh times, then the driving control circuit determines, according to the configuration information, that the number of sub-refresh times, for example, the number of times that the current control display region needs to complete one frame of complete display is 4 times, and then generates sub-synchronization information, for example, the sub-synchronization information is information that the display driving chip 10 needs to complete one frame of complete display for 4 times according to the number of sub-refresh times, the display data and the gray scale clock signal.
The driving control circuit 12 is further configured to generate a pulse width modulation signal according to the double synchronization signal, the display data and the configuration information, and send the pulse width modulation signal to the constant current driving circuit 14;
the constant current driving circuit 14 is configured to receive the pulse width modulated signal and generate a driving current, and simultaneously drive a plurality of channels (DOUT shown in fig. 1A) to output the driving current.
The working principle of the embodiment is as follows: the display driving chip 10 is powered on, and then the gray scale clock generating circuit 11 generates a gray scale clock signal and transmits the gray scale clock signal to the driving control circuit 12 and the double synchronization circuit 13; meanwhile, the driving control circuit 12 receives display data and configuration information, then the driving control circuit 12 generates sub-synchronization information according to the gray scale clock signal and the configuration information and sends the sub-synchronization information to the double synchronization circuit 13, the double synchronization circuit 13 is controlled to receive a frame synchronization signal through a synchronization signal input interface 15 according to the configuration information, then the double synchronization circuit 13 generates a double synchronization signal according to the received sub-synchronization information and the frame synchronization signal and sends the double synchronization signal to the driving control circuit 12 according to the configuration information transmitted by the driving control circuit, when the display driving chip 10 determines that the first working mode is the double synchronization mode according to the configuration information, the driving control circuit 12 generates a pulse width modulation signal according to the double synchronization signal, the configuration information and the display data and sends the pulse width modulation signal to the constant current driving circuit 14, and the constant current driving circuit 14 generates driving current output according to the pulse width modulation signal.
The embodiment of the invention designs the display driving chip 10, firstly receives configuration information and display data through the driving control circuit 12, then sends sub-synchronous information to the double-synchronous circuit through the driving control circuit, the double-synchronous circuit generates double-synchronous signals according to the sub-synchronous information, the frame synchronous signals and the gray scale clock signals and sends the double-synchronous signals to the driving control circuit 12, the driving control circuit 12 generates pulse width modulation signals according to the double-synchronous signals, the configuration information and the display data, and further controls the constant current driving circuit 14 to generate constant current output, thereby controlling the output of the display driving chip, increasing the synchronous times of the display driving chip, and solving the problems of asynchronous display picture and poor display effect caused by gray scale clock deviation of the driving chip.
Further, as shown in fig. 1B, the display driver chip 10 further includes a synchronization signal output interface 16 for outputting the dual synchronization signal generated by the dual synchronization signal circuit 13 to at least one next stage display driver chip in cascade connection.
By providing the synchronizing signal output interface 16 on the display driving chip 10, the double synchronizing signal can be sent to other display driving chips of the next stage connected with the current display driving chip, so that display synchronization is performed between the display driving chips connected with each other when the double synchronizing signal output by the display driving chip of the previous stage arrives, and when the other synchronizing signal is output through the synchronizing signal output interface, the effect of synchronizing the display driving chips connected with each other can be achieved, and wiring is reduced.
Further, as shown in fig. 6, the gradation clock generation circuit 11 includes: the frequency doubling circuit 111 may obtain the input clock signal through a data input interface, or may generate the gray scale clock signal internally, which is not limited herein. After the input clock signal is obtained from the data input interface, the data clock signal is subjected to frequency multiplication processing to obtain a gray scale clock signal GCLK.
Further, as shown in fig. 6, the driving control circuit 12 includes: a command processing circuit 121, a shift register circuit 122, a buffer circuit 123, a counter 124, a gradation break-up processing circuit 125, and a channel control circuit 126.
Wherein, the shift register circuit 122 is connected to the command processing circuit 121; the buffer circuit 123 is connected to the shift register circuit 122; the counter 124 connects the command processing circuit 121 and the gradation clock generation circuit 11; the gradation breaking processing circuit 125 connects the command processing circuit 121 and the counter 124; the channel control circuit 126 connects the command processing circuit 121, the counter 124, the gradation break-up processing circuit 125, the buffer circuit 123, and the double synchronization circuit 13.
The command processing circuit 121 is connected to the shift register circuit 122 and receives the control of the gray scale clock signal GCLK and receives the configuration information outputted from the shift register circuit 122.
The shift register circuit 122 is used for accessing display data DIN [2 ]: 0] and configuration information. The shift register circuit 122 is configured to receive the display data and the configuration information and send the configuration information to the command processing circuit 121. For example, the Shift Register circuit 122 of the present embodiment includes a Shift Register (Shift Register) and circuit logic for command response and data transfer (such as DMA transfer). DMA is abbreviated herein as Direct Memory Access, chinese name direct memory access.
The buffer circuit 123 is connected to the shift register circuit 122 to acquire and store the display data. For example, the buffer circuit 123 of the present embodiment includes an SRAM (Static Random Access Memory ) buffer memory and a RAM Controller (RAM Controller).
The counter 124 is connected to the command processing circuit 121 and the frequency doubling circuit 111, and is configured to receive the gray scale clock signal GCLK and generate a gray scale clock count value under the control of the gray scale clock signal GCLK.
The gray scale breaking processing circuit 125 is connected to the command processing circuit 121 and the counter 124, and is configured to receive control of the command processing circuit 121, and further control counting operation of the counter 124 and generate gray scale packet control signals.
The channel control circuit 126 is connected to the command processing circuit 121, the counter 124, the buffer circuit 123, the constant current driving circuit 14, and the double synchronization circuit 13, and is configured to generate a pulse width modulation signal according to the gray scale clock count value, the gray scale packet control signal, the double synchronization signal, the display data acquired by the buffer circuit 123, and the configuration information, and send the pulse width modulation signal to the constant current driving circuit 14, where the constant current driving circuit 14 generates driving current according to the pulse width modulation signal and outputs the driving current to a plurality of output channels (DOUT [95:0] shown in fig. 3). In this embodiment, the display driving chip 10 is used as an LED display driving chip, and for example, has 96 output channels DOUT [95:0], so that 96 rows of LED lamps can be carried; taking three RGB LED light points as an example to form one LED pixel point, it can carry 32 columns of RGB full-color LED pixel points, that is, 96 output channels DOUT [95:0] are divided into 32 red (R) component output channels, 32 green (G) component output channels and 32 blue (B) component output channels.
The channel control circuit 126 is further configured to generate sub-synchronization information according to the gray scale clock count value, the gray scale packet control signal, and the configuration information stored in the buffer circuit 123, and send the sub-synchronization information to the double synchronization circuit 13.
Further, as shown in fig. 2, the double synchronization circuit 13 includes: a frame synchronization detection circuit 131, a sub-synchronization signal generation circuit 132, a double synchronization signal generation circuit 133, a synchronization pattern selection circuit 134, and a double synchronization detection circuit 135.
Wherein the frame synchronization detecting circuit 131 connects the gray scale clock generating circuit 11 and the synchronization signal input interface 15 and receives a frame synchronization signal through the synchronization signal input interface 15; the sub-synchronization signal generation circuit 132 connects the gradation clock generation circuit 11 and the drive control circuit 12; the double synchronization signal generation circuit 133 connects the sub synchronization signal generation circuit 132, the gradation clock generation circuit 11, the frame synchronization detection circuit 131, and the double synchronization detection circuit 135; the synchronization pattern selection circuit 134 is connected to the frame synchronization detection circuit 131, the double synchronization signal generation circuit 133, the gradation clock generation circuit 11, the drive control circuit 12, and the double synchronization detection circuit 135, and the double synchronization detection circuit is connected to the synchronization signal input interface 15, the gradation clock generation circuit 11, the double synchronization generation circuit 133, and the synchronization pattern selection circuit 134; note that, in fig. 1A and 1B, the connection relationship between the double synchronization circuit and the gradation clock generation circuit 11 is shown, that is, the gradation clock generation circuit 11 supplies the gradation clock signal to each block in the double synchronization circuit 13, so that the connection relationship between each block in the double synchronization circuit 13 and the gradation clock generation circuit is not shown in fig. 2, but does not represent that each block in the double synchronization circuit 13 is not connected to the gradation clock generation circuit 11.
The frame synchronization detecting circuit 131 is configured to obtain a frame synchronization signal through the synchronization signal input interface 15, generate an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock information after detecting the input of the frame synchronization signal, and output the internal frame synchronization signal to the dual synchronization signal generating circuit 133; the internal frame synchronization signal is a frame synchronization signal suitable for a current display driving chip, and the internal frame synchronization signal is different from the frame synchronization signal only in time sequence or pulse width between the internal frame synchronization signal and the frame synchronization signal.
The sub-synchronization signal generating circuit 131 is configured to receive the sub-synchronization information sent by the driving control circuit 12 and the gray scale clock signal generated by the gray scale clock generating circuit 11, generate a sub-synchronization signal according to the sub-synchronization information and the gray scale clock signal, and output the sub-synchronization signal to the double-synchronization signal generating circuit 133; the sub-synchronous information is, for example, information that the display driving chip needs to complete refreshing for 4 times when completing complete display of a frame for a current control display area; the sub-synchronization signal generation circuit 131 then generates sub-synchronization signals, that is, generates 4 sub-synchronization signals, based on the sub-synchronization information and the gray scale clock signal.
The dual synchronization signal generating circuit 133 is configured to receive the intra frame synchronization signal and the sub synchronization signal, superimpose the intra frame synchronization signal and the sub synchronization signal to generate the dual synchronization signal, and output the dual synchronization signal to the synchronization mode selecting circuit 134;
the double synchronization detection circuit 135 is configured to detect the double synchronization signal sent by the double synchronization generating circuit, identify an intra-frame synchronization signal and a sub-synchronization signal in the double synchronization signal, and send the identified double synchronization signal to the synchronization mode selection circuit. As shown in fig. 5, the double synchronization signal includes an intra frame synchronization signal and a sub synchronization signal, and then 2 intra frame synchronization signals and 4 sub synchronization signals are identified. Wherein the dual synchronization detection circuit 135 may also be configured to receive a dual synchronization signal via the synchronization signal input interface 15.
The dual synchronization detection circuit 135 may be further configured to receive a dual synchronization signal sent by a previous stage display driver chip through the synchronization signal input interface 15, identify an intra-frame synchronization signal and a sub-synchronization signal in the dual synchronization signal, and send the identified dual synchronization signal to the synchronization mode selection circuit.
The synchronization mode selection circuit 134 is configured to receive the identified double synchronization signal or the intra frame synchronization signal, and output the double synchronization signal or the intra frame synchronization identified in the double synchronization signal to the driving control circuit 12.
The double synchronization signal is a double synchronization signal generated by superposing the sub synchronization signal and the internal frame synchronization signal, the display driving chip completes display synchronization when the frame synchronization signal arrives, and the display synchronization is also performed when the sub synchronization signal arrives. As shown in fig. 7, the dual synchronization signal includes a plurality of sub-synchronization signals in addition to the frame synchronization signals, and the period and the number of the sub-synchronization signals may be configured by the driving control circuit 12, that is, the period and the number of the sub-synchronization signals may be set by a user, and then put into the configuration information, or may be configured by the driving control circuit 12, which is not limited herein, and then the driving control circuit 12 generates sub-synchronization information according to the configuration information and the gray clock signal, and then the sub-synchronization signal generating circuit 131 generates the sub-synchronization signal according to the sub-synchronization information and the gray clock signal, for example, the sub-synchronization information is information that the display driving chip needs to completely refresh for 4 times for completing a complete display of a current control region, and generates 4 sub-synchronization signals according to the sub-synchronization information and the gray clock signal and sends the sub-synchronization signal to the dual synchronization signal generating circuit 133. Then, the double synchronization signal generating circuit 133 superimposes the internal frame synchronization signal and the 4 sub-synchronization signals to generate the double synchronization signal, where the double synchronization signal is a signal in which the 4 sub-synchronization signals are superimposed between two frame synchronization signals (as shown in the double synchronization signal timing diagram in fig. 7), and due to the difference caused by the different working environments or manufacturing processes of the gray scale clock generating circuit 11 in the display driving chip 10, the accumulated error generated between two frame synchronization signals is cleared in time by refreshing and synchronizing the sub-synchronization signals multiple times.
In order to more clearly understand the display drive control circuit 10 of the present embodiment, the operation principle thereof will be exemplified with reference to fig. 1A, 1B, 2, 3A, 3B, 6 and 7.
After the display driving chip 10 starts to power up normally, the display driving chip 10 receives the configuration information and the display data through the combination command and sends them to the shift register circuit 122 inside the driving control circuit 12.
The frequency multiplier 111 of the gradation clock generation circuit 11 generates a gradation clock signal by internally or externally accessing a clock signal, and transmits the gradation clock signal to the counter 124 in the drive control circuit 12 and the double synchronization circuit 13.
The shift register circuit 122 receives configuration information and display data DIN [2:0]; and transmits the configuration information to the command processing circuit 121.
The counter 124 is configured to receive the gray clock signal and generate a gray clock count value under the control of the gray clock signal; the gray scale breaking-up processing circuit 125 is then configured to receive the control of the command processing circuit to control the counting operation of the counter 124 and generate a gray scale packet control signal; the channel control circuit 126 then obtains the configuration information, the gray scale clock count value and the gray scale packet control signal from the shift register circuit 122, generates sub-synchronization information according to the configuration information, the gray scale clock count value and the gray scale packet control signal, and transmits the sub-synchronization information to the sub-synchronization signal generating circuit.
Then the sub-synchronization signal generating circuit 132 generates a sub-synchronization signal according to the sub-synchronization information and the gray scale clock signal and sends the sub-synchronization signal to the double-synchronization signal generating circuit 133, and at the same time, the frame synchronization detecting circuit 131 receives a frame synchronization signal through the synchronization signal input interface 15 and generates an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal and sends the internal frame synchronization signal to the double-synchronization signal generating circuit 133, and the double-synchronization signal generating circuit 133 superimposes the sub-synchronization signal and the internal frame synchronization signal to obtain the double-synchronization signal and sends the double-synchronization signal to the double-synchronization detecting circuit 135; the dual synchronization detection circuit 135 detects and identifies the intra-frame synchronization signal and the sub-synchronization signal in the dual synchronization signal, and sends the identified intra-frame synchronization signal and the sub-synchronization signal to the synchronization mode selection circuit 134, when the display driver chip 10 determines that the first operation mode is the dual synchronization mode according to the configuration information, the synchronization mode selection circuit 134 selects the identified dual synchronization signal (i.e., the identified intra-frame synchronization signal and the sub-synchronization signal) according to the configuration information, and sends the selected dual synchronization signal to the driving control circuit 12, and simultaneously outputs the dual synchronization signal to a next stage of display driver chip cascaded with the current display driver chip 10 through the synchronization signal output interface 16.
The timing chart of the double synchronization signals is shown in fig. 7, the double synchronization signals include a frame synchronization signal, a plurality of sub-synchronization signals are added between two frame synchronization signals, the period of the sub-synchronization signals can be flexibly set, the display driving chip 10 performs a complete refresh on the area of the current control display in each frame or performs a plurality of complete refreshes on each frame of the LED display screen, each complete refresh is called sub-refresh, the sub-synchronization information includes sub-refresh frequency information that the display driving chip completes a complete display of the area of the current control display for one frame and needs complete refresh, and then sub-synchronization information is generated according to the number of sub-refreshes, display data and gray scale clock signals, for example, the sub-synchronization information is information that the display driving chip 10 completes a complete display of the area of the current control display for 4 times. Multiple sub-refreshes can be achieved within a period of one frame synchronization signal. Then, the command processing circuit 111 clears the gray scale clock count value of the counter 124 that counts the pulses of the gray scale clock signal GCLK generated by the frequency multiplier circuit 111 after receiving the double synchronization signal.
The buffer circuit 123 then acquires and stores display data from the shift register circuit 122, and then sends the display data to the channel control circuit 126;
at this time, the drive control circuit 12 has received the double synchronization signal, and then the channel control circuit 126 generates a pulse width modulation signal from the gradation clock count value, the gradation packet control signal, the double synchronization signal, the display data, and the configuration information, and sends the pulse width modulation signal to the constant current drive circuit 14.
The constant current driving circuit 14 generates a driving current according to the pulse width modulation signal and passes through an output channel DOUT [95:0] output.
In addition, the first operation mode further includes a frame synchronization mode, and when the driving control circuit 12 determines that the first operation mode is the frame synchronization mode according to the configuration information, the synchronization mode selecting circuit 134 selects the internal frame synchronization signal according to the configuration information, inputs the internal frame synchronization signal to the driving control circuit 12, and outputs the internal frame synchronization signal to a next stage display driving chip cascaded with the current display driving chip through the synchronization signal output interface 16.
At this time, the drive control circuit 12 has received the intra frame synchronization signal, and then the channel control circuit 126 generates a target pulse width modulation signal from the gradation clock count value, the gradation packet control signal, the intra frame synchronization signal, the display data, and the configuration information, and sends the target pulse width modulation signal to the constant current drive circuit 14.
The constant current driving circuit 14 generates a target driving current according to the target pulse width modulation signal and passes through an output channel DOUT [95:0] output
In summary, the embodiment of the invention receives the configuration information and the display data through the driving control circuit, then sends the sub-synchronization information to the double-synchronization circuit through the driving control circuit, the double-synchronization circuit generates the double-synchronization signal according to the sub-synchronization information and the gray scale clock signal, and sends the double-synchronization signal to the driving control circuit to generate the pulse width modulation signal, and then controls the constant current driving circuit to generate constant current output, thereby controlling the output of the display driving chip, increasing the synchronization times of the display driving chip, and improving the problems of asynchronous display picture and poor display effect caused by the gray scale clock deviation of the driving chip.
[ second embodiment ]
Fig. 8 is a schematic diagram of a portion of an LED display panel 300 according to an embodiment of the present invention. As shown in fig. 8, the LED display panel 300 includes: a plurality of LED pixel arrays PA, a plurality of display driving chips 10 (illustrated as one example in the figure).
Wherein each LED pixel array PA comprises 32 columns of pixels P and each pixel P comprises a plurality of LEDs, such as R, G, B three primary color LED light points, so that the LED pixel array PA has 96 columns of LED light points. Each 96 columns of LED lamps are respectively connected to 96 output channels DOUT0 to DOUT95 in each display driving chip 10, and each column of pixels P is connected to three adjacent output channels of the constant current driving circuit 14. Furthermore, the pixel array PA includes 32 rows of pixels P, and the 32 rows of pixels P are respectively connected to the 32 output channels LINE0 to LINE31 of the scan control chip 20.
The display driving chips are as shown in fig. 1A and include a synchronous signal input interface 15, and each display driving chip is connected between the display control card and the LED pixel array.
The scan control chip 20 of the present embodiment includes, for example, a row decoding chip, which can cooperate with the display driving chip 10 to sequentially generate 32 row scan signals (or scan driving signals) during each round of 32 scan. It should be noted that, the output channels of the scan control chip 20 in this embodiment are not limited to 32, but may be other numbers, such as 64, etc., and the specific number may be determined according to the actual application requirements.
The display driving chip of the present embodiment receives display data DIN [2:0], configuration information and frame synchronization signal.
[ third embodiment ]
Fig. 9 is another LED display panel 400 according to an embodiment of the present invention, where the LED display panel 400 includes: a plurality of LED pixel arrays 401 and a plurality of display driving chips 10; the plurality of LED pixel arrays 401 are described in the second embodiment, and the details thereof are not described herein.
Wherein a constant current driving circuit in each of the plurality of display driving chips is connected to each of the plurality of LED pixel arrays.
The display driver chips are display driver chips including a synchronization signal input interface 15 and a synchronization signal output interface 16 as described in fig. 1B, and are cascaded through the synchronization signal output interface.
As shown in fig. 9, the plurality of display driving chips includes one master display driving chip 402 and at least one slave display driving chip 403. The master display driver chip 402 and the slave display driver chip 403 may be determined by configuration information, where the configuration information includes a second operation mode, where the second operation mode is a different operation state of the current display driver chip compared to other display driver chips, for example, the second operation mode includes a master driving mode and a slave driving mode, and then the current display driver chip determines that the display driver chip is the master display driver chip or the slave display driver chip according to the master driving mode and the slave driving mode in the second operation mode in the configuration information, for example, when the second operation mode is the master driving mode, the current display driver chip determines that the current display driver chip is the master display driver chip according to the configuration information, and when the second operation mode is the slave driving mode, the current display driver chip determines that the current display driver chip is the slave display driver chip according to the configuration information.
The synchronous signal output interface of each main display driving chip is connected with at least one synchronous signal input interface of the auxiliary display driving chip.
In order to more clearly understand the LED display panel 400 of the present embodiment, the operation principle thereof will be illustrated with reference to fig. 3A to 5 and 9.
The LED display panel 400 is powered on, and the display driving chips determine a master display driving chip 402 and at least one slave display driving chip 403 according to a second working mode in the configuration information, wherein a synchronous output interface of the master display driving chip is connected with a synchronous input interface of the at least one slave display driving chip; as shown in fig. 3A, fig. 3B, and fig. 9, when the current display driver chip is determined to be the master display driver chip according to the second working mode, the driving control circuit in the master display driver chip generates sub-synchronization information according to the configuration information and the gray clock signal and sends the sub-synchronization information to the dual synchronization circuit, and the dual synchronization circuit generates dual synchronization signals or intra-frame synchronization signals and sends the dual synchronization signals or intra-frame synchronization signals to the driving control circuit in the master display driver chip, and simultaneously sends the dual synchronization signals or intra-frame synchronization signals to the synchronization signal input interface of at least one slave display driver chip connected with the master display driver chip through the synchronization signal output interface. That is, the master display driver chip transmits the dual synchronization signal or the intra frame synchronization signal to the slave display driver chip having a connection relationship with the master display driver chip, and when the slave display driver chip has no connection relationship with the master display driver chip, the slave display driver chip does not receive the dual synchronization signal or the intra frame synchronization signal.
As shown in fig. 4 and 9, when the current display driving chip is determined to be the slave display driving chip according to the second operation mode, and the current slave display driving chip is determined to be the double synchronization mode according to the configuration information, the double synchronization signal detection circuit 135 in the double synchronization circuit 13 in the current slave display driving chip receives the double synchronization signal which is cascaded with the master display driving chip and is sent by the synchronization signal output interface 16 through the synchronization signal input interface 15. As shown in fig. 5, the current slave display driver chip determines the frame synchronization mode according to the configuration information, and the frame synchronization signal detection circuit in the current slave display driver chip receives an internal frame synchronization signal through the synchronization signal input interface 16 to the synchronization signal output interface 15 of the master display driver chip of the previous stage cascaded to the slave display driver chip. That is, when the current display driving chip is the slave display driving chip, the signal received by the current display driving chip is sent through the master display driving chip which is in connection with the current display driving chip at the upper stage.
The working principle of the multiple display driving chips determined as the frame synchronization mode or the double synchronization mode according to the first working mode is similar to that of the display driving chip described in the first embodiment, and details thereof are not repeated here.
Still further, as shown in fig. 10, the plurality of display driver chips are determined as a plurality of master display driver chips 402 and a plurality of slave display driver chips 403 according to configuration information, and a synchronization signal output interface of each of the plurality of master display driver chips 402 is connected to a synchronization signal input interface of at least one slave display driver chip 403, that is, each of the plurality of master display driver chips is connected to at least one slave display driver chip, and outputs a dual synchronization signal or an intra-frame synchronization signal to at least one slave display driver chip cascaded to the master display driver chip through the synchronization signal output interface of the master display driver chip.
Each of the plurality of master display driver chips 402 is connected to at least one slave display driver chip 403, and the working principles of the plurality of master display driver chips and the plurality of slave display driver chips are similar to those of the single master display driver chip and the at least one slave display driver chip connected to the single master display driver chip in fig. 9, which are not described herein.
Wherein the frame synchronization signal is issued, for example, by a display control card; the display control card may be used for outputting display data, configuration information and frame synchronization signals, and for example, adopts a hardware structure similar to a receiving card, a scanning card or a module controller which are mature in the technical field of LED display control, that is, adopts a programmable logic device such as an FPGA (Field Programmable Gate Array ) device.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched for use without conflict in technical features and contradiction in structure, without departing from the inventive purpose of the present invention.
Furthermore, it should be noted that the foregoing embodiment of the present invention is described taking the implementation of gray scale capable of completing multiple color components by a single display driving circuit as an example, but the embodiment of the present invention is not limited thereto, and the single display driving circuit may be designed to complete the implementation of gray scale of only a single color component, so that the gray scale data of three color components of R, G, B may be implemented by three different display driving circuits respectively.
Furthermore, it should be appreciated that in the several embodiments provided by the present invention, the disclosed systems, apparatuses and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the partitioning of elements is merely a logical functional partitioning, and there may be additional partitioning in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A display driving chip, comprising:
a synchronization signal input interface;
a gradation clock generation circuit;
a drive control circuit connected to the gradation clock generation circuit;
the double synchronous circuit is connected with the gray scale clock generating circuit, the driving control circuit and the synchronous signal input interface;
a constant current drive circuit connected to the drive control circuit;
the gray scale clock generation circuit is used for generating a gray scale clock signal;
the driving control circuit is used for receiving display data and configuration information and generating sub-synchronous information according to the configuration information and the gray scale clock signal;
The double synchronization circuit receives a frame synchronization signal through the synchronization signal input interface and generates a double synchronization signal according to the gray scale clock signal, the frame synchronization signal and the sub synchronization information;
the driving control circuit generates a pulse width modulation signal according to the double synchronous signals, the configuration information and the display data and sends the pulse width modulation signal to the constant current driving circuit;
the constant current driving circuit generates driving current according to the pulse width modulation signal.
2. The display driver chip of claim 1, further comprising:
and the synchronous signal output interface is used for outputting the double synchronous signals generated by the double synchronous signal circuit to at least one cascaded next-stage display driving chip.
3. The display driver chip of claim 2, wherein the dual synchronization circuit comprises:
a frame synchronization detection circuit for receiving the frame synchronization signal through the synchronization signal input interface;
a sub-synchronization signal generation circuit connected to the drive control circuit;
a double synchronization signal generating circuit connected to the sub synchronization signal generating circuit and the frame synchronization detecting circuit;
The double synchronous detection circuit is connected with the double synchronous signal generation circuit and the synchronous signal input interface; and
a synchronization pattern selection circuit connected to the frame synchronization detection circuit, the double synchronization detection circuit, and the drive control circuit;
the sub-synchronous signal generating circuit is used for generating a sub-synchronous signal according to the sub-synchronous information and the gray scale clock signal; the frame synchronization detection circuit is used for generating an internal frame synchronization signal according to the frame synchronization signal and the gray scale clock signal; the double-synchronizing signal generating circuit is used for superposing the sub-synchronizing signal and the internal frame synchronizing signal to obtain the double-synchronizing signal; the double synchronization detection circuit is used for detecting and identifying the double synchronization signals; the synchronous mode selection circuit is used for selecting the identified double synchronous signal or the internal frame synchronous signal according to the configuration information transmitted by the drive control circuit and transmitting the double synchronous signal or the internal frame synchronous signal to the drive control circuit.
4. The display driver chip of claim 3, wherein the display driver chip,
the driving control circuit is also used for determining a first working mode of the display driving chip according to the configuration information;
When the first working mode of the display driving chip is a frame synchronization mode, the synchronization mode selection circuit outputs an internal frame synchronization signal generated by the frame synchronization detection circuit to the driving control circuit;
when the first working mode of the display driving chip is a double-synchronous mode, the synchronous mode selection circuit outputs the double-synchronous signal identified by the double-synchronous detection circuit to the driving control circuit.
5. The display driver chip of claim 3, wherein the display driver chip,
the driving control circuit is also used for determining a second working mode of the display driving chip according to the configuration information;
when the second working mode of the display driving chip is a main driving mode, the double synchronous detection circuit recognizes the double synchronous signals generated by the double synchronous signals and then sends the double synchronous signals to the synchronous mode selection circuit, and the synchronous mode selection circuit outputs the double synchronous signals recognized by the double synchronous detection circuit to at least one slave display driving chip cascaded with the main display driving chip through the synchronous signal output interface;
when the second working mode of the display driving chip is a slave driving mode, the double synchronous detection circuit in the at least one slave display driving chip recognizes the double synchronous signals output by the cascaded master display driving chip and then sends the double synchronous signals to the synchronous mode selection circuit in the at least one slave display driving chip, and the synchronous mode selection circuit in the at least one slave display driving chip outputs the double synchronous signals recognized by the double synchronous detection circuit in the at least one slave display driving chip to the driving control circuit of the at least one slave display driving chip.
6. The display driver chip of any of claims 1-5, wherein the drive control circuit is further configured to: determining the sub-refresh times of the display driving chip according to the gray scale clock signal and the configuration information, generating sub-synchronization information according to the sub-refresh times, and sending the sub-synchronization information to the double-synchronization circuit.
7. An LED display panel, comprising:
an LED pixel array comprising a plurality of LED pixels and each of the LED pixels comprising a plurality of LEDs; and
a plurality of display driving chips as defined in any one of claims 1 or 6, wherein the constant current driving circuit of the display driving chip is connected to the LED pixel array.
8. An LED display panel, comprising:
an LED pixel array comprising a plurality of LED pixels and each of the LED pixels comprising a plurality of LEDs; and
a plurality of display driver chips as defined in any one of claims 2-5, wherein said constant current drive circuit of said display driver chip is connected to said LED pixel array.
9. The LED display panel of claim 8, wherein the plurality of display driver chips are cascaded through a synchronization signal output interface;
The display driving chips comprise a master display driving chip and at least one slave display driving chip, and a synchronous signal output interface of the master display driving chip is connected with a synchronous signal input interface of the at least one slave display driving chip.
10. The LED display panel of claim 8, wherein the plurality of display driver chips are cascaded through a synchronization signal output interface;
the display driving chips comprise a plurality of master display driving chips and a plurality of slave display driving chips, and a synchronous signal output interface of each master display driving chip is connected with a synchronous signal input interface of at least one slave display driving chip.
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