JP2002313092A - Shift register, electrooptical device, driving circuit and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacity of a shift register which can transfer signals bi-directionally. SOLUTION: The shift register in which circuit blocks 1450 comprising clocked inverters 1451, 1452 being effective respectively exclusively in accordance with a logical level of a control signal and clocked inverters 1453, 1454 being effective respectively exclusively in accordance with a logical level of a transfer direction control signal are connected in multi-stages, and which transfer signals in a direction indicated by the logical level of the transfer direction control signal, every time the logical level of a clock signal is inverted, is provided with a control block 1460 in which it is detected that an input and an output in the circuit block 1450 in a certain stage are significant or no, when it is detected as significance, a clock signal is supplied to the clocked inverters 1451, 1452 of the stage as a control signal, when it is detected as insignificance, a transfer direction control signal is supplied to the clocked inverters 1451, 1452 of the stage as a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, an electro-optical device, a drive circuit, and an electronic device which enable a signal to be transferred bidirectionally and which reduce the capacity and power consumption of a clock signal line. .

[0002]

2. Description of the Related Art In recent years, an electro-optical device which performs display by electro-optical change of an electro-optical material such as a liquid crystal or an organic EL (electro-luminescence) has been developed using a cathode ray tube (CRT).
As a display device that replaces, it is being widely used in various information processing devices and televisions. Here, the electro-optical devices are classified according to a driving method or the like.
An active matrix type, in which pixels are driven by pixel switches, and a passive matrix type, in which pixels are driven without using pixel switches, can be broadly classified. Among them, the former active matrix electro-optical device has the following configuration.

That is, in an active matrix type electro-optical device, a pixel electrode is formed corresponding to the intersection of a scanning line extending in a row direction and a data line extending in a column direction. A pixel switch such as a thin film transistor which is turned on / off in accordance with a scanning signal supplied to a scanning line is interposed between the pixel electrode and the data line at the intersection, and a counter electrode is provided between the pixel electrode and the data line. Are configured to face each other.

In such a configuration, when a scanning signal of an ON voltage is applied to a scanning line, a pixel switch connected to the scanning line is turned on. In this ON state,
When a data signal corresponding to the gradation (density) is supplied to the data line, the data signal is applied to the pixel electrode via the pixel switch, so that the electro-optical material sandwiched between the pixel electrode and the counter electrode is provided. , A voltage corresponding to the data signal is applied. As a result, the electro-optical material changes electro-optically. As a result, the amount of transmitted light, the amount of reflected light, or the amount of light emitted from the pixel (in any case, the amount of light visually recognized by the observer) is reduced by the data signal applied to the pixel electrode. It depends on the voltage. Therefore, by performing such control for each pixel, a predetermined display becomes possible.

Here, the scanning signal is output from a scanning line driving circuit. This scanning line driving circuit has a Y shift register in which a plurality of stages of circuit blocks are connected in multiple stages along the Y direction. Here, the Y shift register first shifts the start pulse supplied at the beginning of the vertical scanning period using a Y clock signal serving as a reference for horizontal scanning, and
In addition, a logical operation is performed on the pulse signals shifted by the circuit blocks of each stage, and the pulse signals are sequentially and exclusively set to the active level and supplied to the respective scanning lines. As a result, the scanning lines are selected one by one in order.

On the other hand, a data signal is output from a data line driving circuit. The data line driving circuit supplies a sampling control signal within a horizontal effective scanning period to a sampling switch that samples an image signal supplied in synchronization with vertical scanning and horizontal scanning for each data line. ing. Specifically, the data line driving circuit has an X shift register in which a plurality of stages of circuit blocks are connected in multiple stages along the X direction. Here, the X shift register is
First, the start pulse supplied at the beginning of the horizontal scanning period is shifted using an X clock signal synchronized with the period at which the image signal is supplied, and second, the start pulse is shifted by the circuit blocks of each stage. The configuration is such that a pulse signal is logically operated and a sampling control signal sequentially and exclusively at an active level is output. Thus, each of the sampling switches samples the image signal in accordance with the sampling control signal, and supplies the image signal to the corresponding data line.

In a circuit block, a clock signal is input to the gate of a clocked inverter.
If a configuration in which the clock signal is supplied to the circuit block as it is is adopted, the capacity of the clock signal line for supplying the clock signal increases. This capacity causes charge / discharge to be performed wastefully every time the logic level of the clock signal changes, so that not only becomes a major factor impeding low power consumption, but also a sufficient drive capacity for the capacity is required. . In particular, the X clock signal is three times greater than the Y clock signal.
Since the frequency is of the order of magnitude, power consumed in the clock signal line for supplying the X clock signal cannot be ignored.

Therefore, a detection circuit for detecting whether the input and output are significant in each circuit block,
The clock signal is supplied only to the circuit block for which the detection result is positive (that is, only to the circuit block that is actually transmitting the start pulse), and one of the power supply voltages is supplied to the other circuit blocks. And a clock control circuit for determining the output state of the clocked inverter in each case.
-199284).

On the other hand, in recent years, electro-optical devices have been required to have a function of inverting a displayed image vertically and horizontally as required. For example, a projector that enlarges and projects an image is used by being placed on a desk or hung from a ceiling. Therefore, it is necessary to invert the displayed image vertically and horizontally according to the installation situation. For example, in a rotary panel monitor of a video camera, the displayed image also needs to be vertically and horizontally inverted in accordance with the rotation angle. For this reason, the X and Y shift registers are of a type that can transfer the start pulse not only in one direction but also in any direction by a control signal.

[0010]

However, when the technique of providing a detection circuit and a clock control circuit at each stage of such a block circuit of a shift register capable of bidirectional transfer is applied, the configuration becomes complicated. Problem. In detail, a configuration is required in which the power supply voltage supplied to the gate of the clocked inverter is switched and supplied according to the transfer direction. Therefore, the configuration is complicated by this configuration, and the circuit area is required accordingly. In addition, there are problems such as a reduction in product yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to enable data to be transferred bidirectionally and to reduce the capacity and power consumption of a clock signal line. An object of the present invention is to provide a shift register, an electro-optical device, a driving circuit thereof, and electronic equipment.

[0012]

In order to achieve the above object, a shift register according to the present invention uses a clock signal to transfer data in a direction indicated by a logical level of a transfer direction control signal. A shift register in which blocks are connected in multiple stages, and a detection circuit that detects whether an input signal and an output signal in one circuit block are significant, and the input signal or the output signal is significant by the detection circuit. When it is detected that there is, the clock signal is supplied to the circuit block, and when it is detected that both the input signal and the output signal are insignificant, a certain period is set during the period in which the transfer is to be performed. A signal having a logic level, the logic level of which varies according to the direction of the transfer, is supplied to the circuit block in place of the clock signal. It is characterized in configuration and a that the clock control circuit. According to this configuration, since the clock signal is supplied by the clock control circuit only to the circuit block in which the input signal or the output signal is detected as significant, the capacity of the clock signal line to which the clock signal is supplied is kept small. Can be For this reason, the power consumed by the capacity can be kept low. When it is detected that both the input signal and the output signal of one circuit block are insignificant, the logic level is not a power supply voltage but a constant logic level during a period in which transfer is to be performed. A signal whose level fluctuates is supplied to the circuit block by the clock control circuit. Therefore, the circuit configuration does not need to be enlarged. In this configuration, it is preferable that the signal having a constant logical level during a period in which the transfer is to be performed and having a logical level varying in accordance with the direction of the transfer is the transfer direction control signal. In this case, the existing signal can be effectively used without generating a special signal.

According to another aspect of the present invention, there is provided a shift register according to the present invention, comprising: a first and a second clocked inverter which are mutually exclusive according to a logic level of a control signal; A circuit block including third and fourth inverters that are mutually exclusive according to the logic level of the direction control signal are connected in multiple stages, and each time the logic level of the clock signal is inverted, the transfer direction control is performed. A shift register for performing transfer in a direction indicated by a logical level of a signal, wherein the detection circuit detects whether an input signal and an output signal in one circuit block are significant, and the detection circuit Or, if the output signal is detected to be significant, the clock signal, if the input signal and the output signal are not both significant The transfer direction control signal when issued, is characterized in structure respectively and a clock control circuit supplied as the control signal to the first and second clocked inverters in the circuit block. In this configuration, the clock signal is supplied by the clock control circuit only to the circuit block in which the input signal or the output signal is detected to be significant, so that the capacity of the clock signal line to which the clock signal is supplied can be reduced. For this reason, the power consumed by the capacity can be kept low. When it is detected that both the input signal and the output signal of one circuit block are not significant, a transfer direction control signal is supplied instead of the power supply voltage. For this reason, the circuit configuration does not need to be enlarged, and there is no need to generate a special signal.

Next, in order to achieve the above object, in a driving circuit for an electro-optical device according to the present invention, a clock is supplied to an electro-optical device having pixels corresponding to intersections of scanning lines and data lines. A driving circuit for an electro-optical device in which circuit blocks for shifting a pulse in a direction indicated by a logical level of a transfer direction control signal using a signal and outputting the shifted signal to either a scanning line or a data line are connected in multiple stages. A detection circuit that detects whether the input and output of a pulse in one circuit block is significant, and when the input or output of the pulse signal is detected as significant by the detection circuit, Supplies the clock signal to the circuit block, and if it is detected that both the input and the output are insignificant, transfers the pulse. A clock control circuit for supplying a signal having a constant logic level during a period and having a logic level varying in accordance with a vertical scanning direction or a horizontal scanning direction to the circuit block in place of the clock signal. And Also in this configuration, similarly to the above shift register, the capacity of the clock signal line to which the clock signal is supplied can be kept small, so that the power consumed by the capacity can be kept low, and the circuit configuration does not need to be enlarged. .

According to another aspect of the present invention, there is provided an electro-optical device including pixels corresponding to intersections of scanning lines and data lines.
Using a clock signal, a driving circuit in which a circuit block that shifts a pulse in a direction indicated by a logical level of a transfer direction control signal and outputs the pulse to either a scan line or a data line is connected in multiple stages is one drive circuit. A detection circuit that detects whether the input and output of the pulse in the circuit block are significant; and, when the input or output of the pulse is detected as significant by the detection circuit, the clock signal While supplying to the circuit block, if both the input and the output are detected as insignificant, the logic level is constant during the period in which the transfer of the pulse is to be performed, and in the vertical scanning direction or the horizontal scanning direction. A clock control circuit that supplies a signal whose logic level changes in response to the clock signal to the circuit block in place of the clock signal. It is set to. Also in this configuration, similarly to the shift register and the driving circuit, the capacity of the clock signal line to which the clock signal is supplied can be reduced, so that the power consumed by the capacity can be reduced, and the circuit configuration can be enlarged. It does not need to be changed.

Further, in the electronic apparatus according to the present invention, since the above-described electro-optical device is provided in the display unit, the configuration can be simplified and the power consumption can be reduced. In addition, as such electronic devices, there are devices that need to turn the image left and right or upside down, such as a light valve of a projector that is installed on a desk or suspended from a ceiling or a rotary monitor of a video camera. is assumed.

[0017]

Embodiments of the present invention will be described below.

<Overall Electro-Optical Device> First, for convenience of explanation, an overall electro-optical device including a shift register according to an embodiment of the present invention will be described. This electro-optical device performs display using liquid crystal as an electro-optical material, and FIG. 1 is a block diagram showing this configuration.

As shown in this figure, the electro-optical device 1
In 00, a plurality of m scanning lines 112 are arranged in a row (X).
On the other hand, a plurality of n data lines 114 are formed extending along the column (Y) direction. The scanning line 112 and the data line 11
Pixels are formed corresponding to the intersections with No. 4.

More specifically, a pixel includes a thin film transistor (Thin Fil) corresponding to a portion where the scanning line 112 and the data line 114 cross each other (electrically insulated).
m Transistor (hereinafter referred to as “TFT”) 116 is provided, its gate is connected to the scanning line 112, its source is connected to the data line 114, and its drain is connected to the pixel electrode 118. In the embodiment, when the TFT 116 is of an N-channel type, when the scanning signal supplied to the scanning line 112 becomes H level, TF
T116 is turned on between the source and the drain. Here, the pixel electrode 118 is opposed to the counter electrode 108 to which a constant voltage is commonly applied. And, by both electrodes and the liquid crystal 105 sandwiched between both electrodes,
A liquid crystal capacitor is formed, and the amount of transmitted light changes according to the effective value of the voltage applied between both electrodes. Note that the pixel electrode 118 (the drain of the TFT 116)
Is connected to one end of a storage capacitor 117, while the other end of the storage capacitor 117 is commonly connected to all pixels by a capacitor line 113, so that a signal Stg of a constant voltage is applied.

The scanning line driving circuit 130 includes the shift register according to the embodiment, which will be described in detail later. The scanning line driving circuit 130 supplies a start pulse DY defining the start of the vertical scanning period to the clock signal YCL and the inverted clock. By sequentially latching in accordance with the signal YCLinv, the scanning signals that become H level sequentially exclusively for one vertical scanning period are transferred to the transfer direction control signals Dir-D and Dir.
The signal is supplied to the scanning line 112 in the direction indicated by -U. Here, the transfer direction control signal Dir-
D and Dir-U are signals for indicating the vertical scanning direction. When vertical scanning is performed in the downward direction (+ Y direction) in FIG. 1, the transfer direction control signal Dir-D becomes H level, and When the vertical scanning is performed in the upward direction (-Y direction) while the control signal Dir-U is at the L level, the transfer direction control signal Dir-D is at the L level and the transfer direction control signal Dir-U is at the H level. Becomes That is, the transfer direction control signals Dir-D and Dir-U are signals that indicate the vertical scanning direction with mutually exclusive logical levels.

Then, the transfer direction control signals Dir-D, D
When ir-U becomes H level and L level, respectively, and the vertical scanning direction is instructed downward, the scanning signals Y1, Y
2, Y3,..., Ym are exclusively at the H level, while the transfer direction control signals Dir-D and Dir-U are at the L and H levels, respectively, and the vertical scanning direction is directed upward. , The scanning signals Ym, Ym-1, Ym-2,
, And exclusively at H level in the order of Y1. Note that the scanning signals Y3, Ym-1, and Ym-2 are respectively in the third row,
It is supplied to the (m-1) th and (m-2) th scanning lines 112, but is not shown.

On the other hand, the data line drive circuit 140 includes the shift register according to the embodiment, which will be described in detail later, and includes a start pulse DX for defining the start of a horizontal scanning period and a clock signal XCL and an inverted clock. By sequentially latching in accordance with the signal XCLinv, a sampling control signal sequentially and exclusively at H level for one horizontal effective scanning period is output in the direction specified by the transfer direction control signals Dir-L and Dir-R. Is what you do. Here, the transfer direction control signal Di
r-L and Dir-R are signals for instructing the horizontal scanning direction. When performing horizontal scanning in the right direction (+ X direction) in FIG. 1, the transfer direction control signal Dir-L becomes H level, When horizontal transfer is performed in the left direction (−X direction) while the transfer direction control signal Dir-R becomes L level,
The transfer direction control signal Dir-L goes low, and the transfer direction control signal Dir-R goes high. That is, the transfer direction control signals Dir-L and Dir-R are signals that indicate the horizontal scanning direction with mutually exclusive logical levels.

Then, the transfer direction control signals Dir-L, D
When ir-R becomes H level and L level, respectively, and the horizontal scanning direction is instructed to the right, the sampling control signals Xs1, Xs2, Xs3,... Transfer direction control signals Dir-L, D
When ir-R becomes L level and H level, respectively, and the horizontal scanning direction is directed to the left direction, the H level is exclusively obtained in the order of the sampling control signals Xsn, Xsn-1, Xs-2,. Becomes Note that the sampling control signal X
sn-1 and Xsn-2 are the (n-1) -th column,
It is supplied to the sampling switch 151 corresponding to the data line 114 of the (n-2) th column, but is not shown.

Next, the sampling switch 151 is inserted between one end of the data line 114 in each column and the image signal line 171 to which the image signal VID is supplied, and the corresponding sampling control signal is set to the H level. It turns on when it becomes. Here, an image signal VID having a voltage corresponding to the gradation (density) of a pixel is supplied to the image signal line 171 from a higher-level device (not shown) in synchronization with horizontal scanning and vertical scanning.

<Data Line Driving Circuit> Next, details of the data line driving circuit 140 in FIG. 1 will be described. FIG. 2 is a block diagram showing a configuration of the data line driving circuit 130. As shown in this figure, the data line driving circuit 1
Reference numeral 40 denotes an X that can transfer the start pulse DX in both directions.
The X shift register 1400 includes (m + 2) stages of transfer unit circuits 1402, 1
404 are cascaded. That is,
The total number of transfer unit circuits 1402 and 1404 is
The number is "2" larger than the number m of fourteen.
FIG. 2 shows a configuration in which the number n of the data lines 114 is an odd number.

Here, when the horizontal scanning direction is the right direction, in the transfer unit circuits 1402 and 1404, the left end is input and the right end is output. Therefore, when the horizontal scanning direction is the right direction, the transfer unit circuit 14
02, 1404, in order from the left in the figure,
,..., N, and n + 1. Also, for convenience, when the horizontal scanning direction is the right direction, 0 steps, 1 step,
, XLn, the signals output from the right end of the transfer unit circuits of the n stages are denoted as XL0, XL1,..., XLn, respectively. Conversely, when the horizontal scanning direction is the left direction, in the transfer unit circuits 1402 and 1404, the right end is input and the left end is output. Therefore, when the horizontal scanning direction is the left direction, the transfer unit circuit 14
02 and 1404 are counted as 0, 1,..., N, and n + 1 in order from the right, as shown in parentheses in the figure. For convenience, when the horizontal scanning direction is the left direction, signals output from the left ends of the 0-stage, 1-stage,..., N-stage transfer unit circuits are respectively represented by XR0, XR1,.
It will be described as XRn.

Regardless of whether counting from the left or from the right, the code of the transfer unit circuit in the even-numbered (including 0) stage is set to 1402 for convenience, and the code of the transfer unit circuit in the odd-numbered stage is set to 1404. . Transfer unit circuits 1402, 1404
Are the same as each other as described later,
The supply of the clock signal XCL supplied via the clock signal line 1412 and the supply of the inverted clock signal XCLinv supplied via the inverted clock signal line 1414 are interchanged, so that their operations are distinguished. .

On the other hand, a complementary analog switch 1422
Turns on when the transfer direction control signal Dir-L is at the H level (when the transfer direction control signal Dir-R is at the L level) and turns on the start pulse DX at the node A (that is, in the case of rightward transfer). (The input terminal of the transfer unit circuit at the 0th stage). The complementary analog switch 1424 also has a transfer direction control signal Di.
When r-L is at L level (transfer direction control signal signal D
It turns on when ir-R is at the H level, and supplies the start pulse DX to the node B (that is, the input terminal of the transfer unit circuit at the 0th stage in the case of the leftward transfer).

Here, the sampling control signals Xs1, Xs
To generally describe s2, Xs3, ..., Xsn,
An integer j that satisfies 1 ≦ j ≦ n is used. NAND circuit 14
Numeral 32 is for calculating the NAND of the signals XLj-1 and XLj output from the adjacent transfer unit circuits when the horizontal scanning direction is the right direction.
Is to re-negate the NAND by the NAND circuit 1432 and output the result as the sampling control signal Xsj. That is, the NAND circuit 1432 and the NOT circuit 1434 are provided corresponding to the data lines 114 in each column.

Next, the transfer unit circuit 140 in the even-numbered stage
The transfer unit circuits 1404 in the second and odd stages will be described. FIG. 3 is a circuit diagram showing the detailed configuration.
As shown in this figure, transfer unit circuits 1402, 14
04 includes a circuit block 1450 and a control block 1460. Of these, circuit block 1
450 controls the transfer of the start pulse DX, and the control block 1460 controls the clock signal to the corresponding circuit block 1450.

Here, N in control block 1460
The OR circuit (detection circuit) 1462 calculates the NOR of the input and output of the corresponding circuit block 1450. In addition, the NOT circuit 1464 obtains the re-denial of the NOR by the NOR circuit 1462 in order to drive the complementary analog switches 1472, 1474, 1476, and 1478.

On the other hand, analog switches 1472 and 147
Reference numeral 4 functions as a selector for selecting either the transfer direction control signal Dir-R or the clock signal XCL in the even-numbered stage (the inverted clock signal XCLinv in the odd-numbered stage). Specifically, when the NOR signal of the NOR circuit 1462 is at H level (when the NOT signal of the NOT circuit 1464 is at L level), the analog switch 1472 is turned on and the analog switch 1474 is turned off. The direction control signal Dir-R is supplied as a control signal to the clocked inverter 1451 in the circuit block 1450. Conversely, when the NOR signal of the NOR circuit 1462 is at L level (when the NOT signal of the NOT circuit 1464 is at H level), the analog switch 147 is output.
2 is turned off while the analog switch 1474 is turned on, so that the clock signal XCL in the even-numbered stage (the inverted clock signal XCLinv in the odd-numbered stage) is supplied to the clocked inverter 1451 as a control signal.

The analog switches 1476 and 147
Reference numeral 8 functions similarly as a selector for selecting either the transfer direction control signal Dir-L or the inverted clock signal XCLinv in the even-numbered stage (the clock signal XCL in the odd-numbered stage). In detail, NO
When the NOR signal of the R circuit 1462 is at the H level, the analog switches 1476 and 1478 are turned on and off, respectively, so that the transfer direction control signal Dir-L is supplied as a control signal to the clocked inverter 1452. On the other hand, when the NOR signal from the NOR circuit 1462 is at the L level, the analog switch 1476,
1478 turn off and on, respectively, so that the inverted clock signal XCLinv in the even-numbered stages (the clock signal XCL in the odd-numbered stages) is supplied to the clocked inverter 1452.
As a control signal. That is, the NOR circuit 1462 functions as a detection circuit, and the analog switch 1
472, 1474, 1476, and 1478 function as a clock control circuit that supplies a clock signal or a transfer direction control signal according to the detection result of the NOR circuit.

Next, the circuit block 1450 includes clocked inverters 1451 and 1452 each performing a negative operation when the supplied control signal is at the H level.
Clocked inverter 14 that performs a negative operation when supplied transfer direction control signal Dir-L is at H level.
53, and a clocked inverter 1454 that performs a negation operation when the supplied transfer direction control signal Dir-R is at H level. When the horizontal scanning direction is the right direction, the clocked inverter 1451 inputs the signal input from the left end to the circuit block 1450 and outputs the signal to the clocked inverter 1453 side, while the horizontal scanning direction is If it is to the left, the output of the clocked inverter 1454 is input and fed back to the input of the clocked inverter 1454. The clocked inverter 1452 receives the output of the clocked inverter 1453 when the horizontal scanning direction is rightward and feeds it back to the input of the clocked inverter 1453. On the other hand, when the horizontal scanning direction is leftward, The signal input from the right end is input to the circuit block 1450 and output to the clocked inverter 1454 side.

The circuit block 1450 in FIG.
Here, the complementary configuration is omitted for the sake of understanding the description. More specifically, clocked inverters 1451, 1452, 1453, and 145 constituting circuit block 1450
4 are actually two P-channel TFTs and two serially connected between the higher voltage Vdd and the lower voltage Vss of the power supply, as shown in FIG. Complementary to the N-channel type TFT. Therefore, the analog switches 1472, 147
Reference numeral 4 denotes a clock for transmitting either the transfer direction control signal Dir-R or the clock signal XCL in the even-numbered stage (the inverted clock signal XCLinv in the odd-numbered stage) together with the gate of the N-channel TFT in the clocked inverter 1451. P in the inverter 1452
It is configured to supply the gate of the channel type TFT as well. Similarly, analog switches 1476 and 1478 are
Either the transfer direction control signal Dir-L or the inverted clock signal XCLinv in the even-numbered stage (the clock signal XCL in the odd-numbered stage) is supplied to the clocked inverter 1451 together with the gate of the N-channel TFT in the clocked inverter 1452. Is also supplied to the gate of the P-channel TFT. The transfer direction control signal Dir-L is transmitted to the P-channel type TF in the clocked inverter 1454 together with the N-channel type TFT in the clocked inverter 1453.
The transfer direction control signal D is also supplied to the gate of T.
ir-R is equal to N in clocked inverter 1454.
Clocked inverter 14 with channel type TFT
It is also supplied to the gate of the P-channel TFT at 53.

The data line driving circuit 140 having such a configuration
In FIG. 2, when the horizontal scanning direction is the right direction, the analog switch 1422 is turned on in FIG. 2 by the transfer control signal Dir-L at H level and the transfer direction control signal Dir-R at L level, and the analog switch 1
Since the switch 424 is turned off, the start pulse DX is input to the left end of the transfer unit circuit 1402 at the 0th stage counted from the left. Further, the clocked inverter 1453 in FIG.
An N-channel TFT to which ir-L is supplied as a control (gate) signal, and a transfer control signal Dir-L at L level.
All the P-channel TFTs to which R is supplied as a control signal are turned on. Therefore, the clocked inverter 1
453 performs a normal negation operation. On the other hand, in the clocked inverter 1454, the transfer control signal Dir-L at the H level is supplied as a control signal to the P-channel TFT, and the transfer control signal Dir-L at the L level is supplied to the clocked inverter 1454.
All the N-channel TFTs to which R is supplied as a control signal are turned off. Therefore, the clocked inverter 1
454 becomes a high impedance state.

Therefore, when the horizontal scanning direction is the right direction, the equivalent circuits of the circuit blocks 1450 in the even-numbered stages and the odd-numbered stages are as shown in FIG. That is, the output of clocked inverter 1451 is inverted by clocked inverter 1453,
In addition to the output signal of the circuit block 1450, a signal obtained by inverting the output signal by the clocked inverter 1452 is fed back to the input of the clocked inverter 1453.

At this time, during the period when the clock signal XCL is at the H level (the period when the inverted clock signal XCLinv is at the L level), the clocked inverter 1451 of the even-numbered stages is used.
Performs a negative operation, the output signal of clocked inverter 1453 in the even-numbered stage matches the input signal of clocked inverter 1451. Next, when the clock signal XCL changes to L level (the inverted clock signal XCLinv changes to H level), the clocked inverter 1 of the even-numbered stage
Since 452 performs a negative operation, the output signal of the clocked inverter 1453 in the even-numbered stage is latched. On the other hand, during the period when the clock signal XCL is at the L level, the clocked inverter 1451 in the odd-numbered stage performs a negating operation, so that the output signal of the clocked inverter 1453 in the odd-numbered stage is output in the even-numbered stage preceding the odd-numbered stage. It matches the latched signal, that is, the input signal of the clocked inverter 1451 of the odd-numbered stage.

Therefore, the signal output from the clocked inverter 1453 of the odd-numbered stage is higher than the signal output from the clocked inverter 1453 of the preceding even-numbered stage in the clock signal XCL (inverted clock signal XCLin).
v) is delayed by a half cycle. Therefore, when the horizontal scanning direction is the right direction, 0-stage, 1-stage, 2-stage,
The signals XL0, XL1, XL2, XL3,..., XLn output from the three-stage,.
It is as shown in FIG. That is, the signal X of the 0th stage
L0 is a signal obtained by capturing the start pulse DX when the clock signal XCL rises (falling of the inverted clock signal XCLinv), and the subsequent signals XL1 and XL
2, XL3,..., XLn are obtained by sequentially shifting the signal XL0 by a half cycle of the clock signal XCL (inverted clock signal XCLinv).

The NAND circuit 14 corresponding to each column
32 and the negation circuit 1434 extract an overlapping portion between signals output from adjacent stages,
As shown in FIG. 6, the sampling control signal Xs1,
Xs2, Xs3,..., Xsn are output in this order.

In this embodiment, when the horizontal scanning direction is the right direction, the circuit block 145 in a certain stage
0 (the clocked inverter 14)
When the input signal of the clock circuit 51 is high, or when the signal (the output signal of the clocked inverter 1453) output to the right end of the circuit block 1450 in this stage is at high level, the NOR operation by the NOR circuit 1462 is performed. The signal goes low (a negative signal from the NOT circuit 1464 goes high). Here, when the horizontal scanning direction is the right direction, the clocked inverter 1 in a certain stage
The time when the input signal of 451 is H level or the time when the output signal of the clocked inverter 1453 in this stage is H level is when the circuit block 1450 in this stage transfers the start pulse DX.
At this time, the analog switches 1472 and 1476 are turned off and the analog switches 1474 and 1478 are turned on. As a result, the clock signal XCL is supplied to the even-numbered stage, and the inverted clock signal XCLinv is supplied to the odd-numbered stage. Supplied as a control signal to
In the even-numbered stages, the inverted clock signal XCLinv
However, in the odd-numbered stages, the clock signal XCL is supplied to the clocked inverter 1452 as a control signal.

On the other hand, when the input signal of clocked inverter 1451 is at the L level and the output signal of clocked inverter 1451 is at the L level, the NOR signal of NOR circuit 1462 becomes H level (Negation). The negation signal from the circuit 1464 becomes L level). Here, when the horizontal scanning direction is the right direction, when both the input signal of the clocked inverter 1451 in a certain stage and the output signal of the clocked inverter 1453 in this stage are at L level, This is when the circuit block 1450 is not involved in the transfer of the start pulse DX. At this time, the analog switch 14
72, 1474, 1476, and 1478 are reversed, so that the L-level transfer direction control signal Dir-R
Is supplied to the clocked inverter 1451 as a control signal, and the H-level transfer direction control signal Dir-L
Is supplied to the clocked inverter 1452 as a control signal.

For this reason, the transfer control signal D at L level
N-channel type TF in which ir-R is supplied as a control signal
Since both T and the P-channel TFT to which the transfer control signal Dir-L at the H level is supplied as a control signal are turned off, the clocked inverter 1451 enters a high impedance state. On the other hand, an N-channel TFT to which a transfer control signal Dir-L at H level is supplied as a control signal, and a transfer control signal Dir-R at L level
Are turned on, the P-channel TFTs supplied as control signals are turned on.
Performs a normal negation operation. Therefore, the clocked inverters 1452 and 1453 form a latch circuit independent of the clock signal. The premise of forming such a latch circuit is that the input signal of the clocked inverter 1451 and the clocked inverter 1
453 are both at L level,
The L level is held and output by the latch circuit.

On the other hand, when the horizontal scanning direction is the left direction,
Since the analog switches 1422 and 1424 in FIG. 2 are turned off and on, respectively, by the transfer control signal Dir-L at L level and the transfer direction control signal Dir-R at H level, the start pulse DX is counted from the right. This is input to the right end of the transfer unit circuit 1402 of the 0th stage. In FIG. 4, clocked inverter 1454 has transfer control signal D at H level.
an N-channel TFT to which ir-R is supplied as a control (gate) signal; and a transfer control signal Dir- at H level.
All the P-channel TFTs to which R is supplied as a control signal are turned on. Therefore, the clocked inverter 1
454 performs a normal negation operation. On the other hand, in the clocked inverter 1453, the transfer control signal Dir-R at the H level is supplied as a control signal to the P-channel TFT, and the transfer control signal Dir-R at the L level is supplied to the clocked inverter 1453.
All the N-channel TFTs whose L is supplied as a control signal are turned off. Therefore, the clocked inverter 1
453 is in a high impedance state.

Therefore, when the horizontal scanning direction is the left direction, the equivalent circuit of the circuit block 1450 in the even and odd stages is as shown in FIG. 5B. That is, the output of clocked inverter 1452 is inverted by clocked inverter 1454,
In addition to the output signal of the circuit block 1450, a signal obtained by inverting the output signal by the clocked inverter 1451 is fed back to the input of the clocked inverter 1454.

Here, a configuration in which a plurality of circuit blocks 1450 each serving as an equivalent circuit in FIG. 5B are connected, and FIG.
The configuration in which the circuit blocks 1450, which are equivalent circuits to each other, are connected in multiple stages has a symmetrical relationship with each other, including the supply relationship of the clock signal XCL and the inverted clock signal XCLinv. For this reason, when the horizontal scanning direction is the left direction, the sampling control signal output from the data line driving circuit 140 shows the time-series relationship of the sampling control signal output when the horizontal scanning direction is the right direction. It will be reversed.

That is, when the horizontal scanning direction is the left direction, the 0th stage signal XR0 counted from the right, as shown in FIG.
Are taken at the rising edge (falling of the inverted clock signal XCLinv), and the following signals XR1 and XR
2, XR3,..., XRn are obtained by sequentially shifting the signal XR0 by a half cycle of the clock signal XCL (inverted clock signal XCLinv). And N corresponding to each column
By the AND circuits 1432 and 1434 (see FIG. 2),
The overlapping portions of the signals output from the adjacent stages are extracted, and as shown in FIG. 7, the sampling control signals Xsn, Xsn-1, Xsn-2,..., Xs1
Are output in this order.

In this embodiment, when the horizontal scanning direction is the left direction, when the input signal of the clocked inverter 1452 in a certain stage is at the H level, or when the output of the clocked inverter 1454 in the stage is When the signal is at the H level, that is, when the circuit block 1450 in this stage transfers the start pulse DX, the clock control circuit in that stage causes the clock block in the even stage to transfer the start pulse DX, as in the case where the horizontal scanning direction is rightward. When the clock signal XCL is in an odd-numbered stage, the inverted clock signal XCLinv is supplied to the clocked inverter 1451 as a control signal. In the even-numbered stage, the inverted clock signal XCLinv is in an odd-numbered stage. Indicates that the clock signal XCL is supplied to the clocked inverter 1452 by the control signal and It is supplied Te.

On the other hand, when the input signal of clocked inverter 1451 is at L level and the output signal of clocked inverter 1451 is at L level, that is, circuit block 1450 in this stage does not transfer start pulse DX. At this time, the transfer control signal Dir- at the H level is output by the clock control circuit in the stage.
R is supplied to the clocked inverter 1451 as a control signal, and the transfer direction control signal Dir-
L is supplied to the clocked inverter 1452 as a control signal.

Therefore, the transfer control signal D at L level
N-channel type TF in which ir-L is supplied as a control signal
Since both T and the P-channel TFT to which the transfer control signal Dir-R at H level is supplied as a control signal are turned off, the clocked inverter 1452 enters a high impedance state. On the other hand, an N-channel TFT to which a transfer control signal Dir-R at H level is supplied as a control signal, and a transfer control signal Dir-L at L level
Are turned on, the P-channel TFTs supplied as control signals are turned on.
Performs a normal negation operation. Therefore, the clocked inverters 1451 and 1454 form a latch circuit independent of the clock signal. The premise of forming such a latch circuit is that the input signal of the clocked inverter 1452 and the clocked inverter 1
Since both output signals 454 are at L level,
The L level is held and output by the latch circuit.

As described above, in the present embodiment, when the control block 1460 in a certain stage transfers the start pulse DX by the circuit block 1450 in that stage,
Clock signal XCL and inverted clock signal XCLinv
Is supplied to the clocked inverter of the circuit block 1450 as a control signal, and when the circuit block 1450 in the stage does not transfer the start pulse DX, the clock signal XCL and the inverted clock signal XCL
transfer direction control signals Dir-L, Dir-
R is supplied to the clocked inverter of the circuit block 1450 as a control signal. Therefore, in the present embodiment, the clock signal line 1412 to which the clock signal XCL is supplied and the inverted clock signal line 1414 are connected to the transfer unit circuit 1402 that transfers the start pulse DX,
1404, and other transfer unit circuits 1402,
It will be disconnected from 1404. For this reason, in the present embodiment, the capacity of the clock signal line 1412 and the inverted clock signal line 1414 is
Since the power consumption is drastically reduced as compared with the configuration in which 0 is not provided, power is not wasted due to these capacitances every time the logic level of the clock signal changes.

Further, in this embodiment, when the circuit block 1450 in a certain stage does not transfer the start pulse DX, the signal supplied to the clocked inverter of the circuit block 1450 as a control signal is the higher voltage Vdd of the power supply or The transfer direction control signals Dir-R and Dir-U are used instead of the lower voltage Vss. The reason is as follows. That is, if the X shift register 1400 is configured to perform, for example, transfer only in the right direction, when the circuit block 1450 in a certain stage does not transfer the start pulse DX,
In order to set the output signal of the clock signal 50 to L level in the circuit block 1450, the control signal of the N-channel TFT in the clocked inverter 1451 includes the lower voltage Vss of the power supply (the control signal of the P-channel TFT). A configuration in which the higher voltage Vdd of the power supply is supplied, and the higher voltage Vdd of the power supply (the lower voltage Vss of the power supply for the control signal of the P-channel TFT) is supplied to the control signal of the N-channel TFT in the clocked inverter 1452. (See, for example, the above-mentioned JP-A-10-199284).

However, such a configuration is not sufficient if the transfer is performed in the right and left directions as in the present embodiment. In this configuration, when trying to transfer to the left, when the start pulse is not transferred,
Since the clocked inverter 1452 is in the negative operation and the clocked inverter 1454 is also in the negative operation, that is, since the circuit block is in a so-called cylinder missing state from the input to the output, the function of the shift register is lost. It is. Considering the development of the one-way transfer configuration, when performing the transfer in the right direction, the control signal of the N-channel TFT in the clocked inverter 1451 is applied to the lower voltage Vss (the control signal of the P-channel TFT). While supplying the higher voltage Vdd of the power supply and supplying the higher voltage Vdd (the lower voltage Vss of the power supply to the control signal of the P-channel TFT) to the control signal of the N-channel TFT in the clocked inverter 1452, When the transfer is performed in the direction, the power supply voltage should be switched and supplied. However,
In such a configuration in which the power supply voltage is switched according to the transfer direction, a power supply voltage replacement circuit is separately required. In addition, this power supply voltage replacement circuit is required for each transfer unit circuit.
There will be significant effects that cannot be ignored. For example, problems such as a decrease in the yield, an increase in the area of the shift register, and a difficulty in reducing the data line pitch occur.

Therefore, the clock control circuit according to the present embodiment includes a circuit block 145 that does not transfer a start pulse.
0, the clocked inverters 1451, 1452
, The transfer direction control signals Dir-R and Dir-U are supplied instead of the power supply voltage. In such a configuration, since a circuit for switching the power supply voltage in accordance with the transfer direction is not necessary, problems such as a decrease in yield and an increase in the area of the shift register occur. In particular, in an electro-optical device with a built-in drive circuit in which the drive circuit is formed around the display area, the area required for the drive circuit can be reduced, so that the frame can be narrowed easily.

The data line drive circuit 14 has been described so far.
Although 0 has been described, the scanning line driving circuit 130 has a similar configuration. Specifically, as shown in FIG. 8, the arrangement direction of the Y shift register 1300 is the Y direction, and the number of transfer unit circuits 1302 and 1304 forming the Y shift register 1300 is larger than the number m of the scanning lines 112. The scanning line driving circuit 130 has the same configuration as that of the data line driving circuit 140 except that the number of supplied signals is increased by “2” and the supplied signals are different. The scanning line driving circuit 13
0, a start pulse DY and a clock signal YC
L, inverted clock signal YCLinv, transfer direction control signal D
ir-D and Dir-U are as described above. Note that FIG. 8 illustrates a configuration in which the number m of the scanning lines 112 is an odd number.

<Image Display Operation> Next, the display operation of the above-described electro-optical device will be described. First, the normal rotation image display operation when the vertical scanning direction is downward and the horizontal scanning direction is rightward will be described. In this case, since the transfer direction control signal Dir-D goes high and the transfer direction control signal Dir-H goes low, the analog switches 1322 and 1334 turn on and off, respectively, and thus define the beginning of the vertical scanning period. Start pulse DY
Is supplied to the upper end of the zero-stage transfer unit circuit 1302 counted from the top. Therefore, as shown in FIG. 9, the scanning signals Y1, Y2, Y3,..., Ym are output in order.

More specifically, in FIG.
, One-stage, two-stage, three-stage,..., M-stage transfer unit circuits 130
2 (1304) is a signal obtained by capturing the start pulse DY at the rising edge of the clock signal YCL (falling edge of the inverted clock signal YCLinv), and further adding the clock signal YCL (inverted clock signal YCLin).
v) are sequentially shifted by a half cycle, and
NAND circuit 1332 and NOT circuit 1 corresponding to each row
By 334, the overlapping portion of the signals output from the adjacent stages is extracted, and the scanning signals Y1, Y2,.
, Ym.

Here, when the scanning signal Y1 becomes H level, the TFT whose gate is connected to the scanning line 112 of the first row is used.
116 are all turned on. On the other hand, during the period when the scanning signal Y1 is at the H level, the image signal VID corresponding to each pixel
Are sampling control signals Xs1, Xs2, Xs3,
.., Respectively, in synchronization with the supply of Xsn.
1 in turn. Here, when the sampling control signal Xs1 becomes H level, the sampling switch 151 in the first column is turned on, so that the image signal VID becomes
The data is sampled on the data line 114 of the first column. Then, the image signal VID sampled on the data line 114 in the first column is applied to the pixel electrode 118 in the first row and the first column via the TFT 116 which is turned on, and is written into the liquid crystal capacitance.

Next, when the sampling control signal Xs2 becomes H level, the sampling switch 151 in the second column is turned on, so that the image signal VID is changed to the data line 1 in the second column.
14 which is sampled and turned on
The data is written to the liquid crystal capacitors in one row and two columns through the line 16. In the same manner, the image signal VID is sampled, and 1
Writing is performed up to the liquid crystal capacitance in the row n column. Thus, the writing of the liquid crystal capacitance from the first column to the n-th column in the first row is completed. Thereafter, the scanning signals Y2, Y3,.
Sequentially turn to the H level, the writing of the liquid crystal capacitors from the first column to the n-th column is executed in the second row, the third row,... Thus,
A normal image in which the vertical scanning direction is the downward direction and the horizontal scanning direction is the right direction is formed.

Next, an inverted image display operation when the vertical scanning direction is the upward direction and the horizontal scanning direction is the left direction will be described. In this case, the transfer direction control signal Dir-D
Becomes L level and the transfer direction control signal Dir-U becomes H level, so that the analog switches 1322 and 1334
Turns off and on, respectively, resulting in a start pulse DY
Are supplied to the lower end of the zero-stage transfer unit circuit 1302 counted from the bottom. Therefore, as shown in FIG. 10, the scanning signals Ym, Ym-1, Ym-2,..., Y1 are output in order.

Here, when the scanning signal Ym becomes H level, the TFT whose gate is connected to the scanning line 112 of the m-th row
116 are all turned on. On the other hand, during the period in which the scanning signal Ym is at the H level, the image signal VID includes the sampling control signals Xsn, Xsn-1, Xsn-2,.
Are supplied in order via the image signal line 171 in synchronization with the supply of the signals. Here, the sampling control signal Xs
When n becomes the H level, the sampling switch 151 in the n-th column is turned on, so that the image signal VID corresponding to the pixel in the m-th row and the n-th column is sampled on the data line 114 in the n-th column. Then, the image signal VID sampled on the data line 114 of the n-th column is the ON state of the TFT 1
The voltage is applied to the pixel electrode 118 of m rows and n columns via 16 and written into the liquid crystal capacitance.

Next, when the sampling control signal Xsn-1 goes to the H level, the sampling switch 151 in the (n-1) th column is turned on, so that the image signal VID becomes (n-
The data is sampled by the data line 114 in the 1) th column and written into the liquid crystal capacitance in the m-th row (n-1) column through the TFT 116 which is turned on. Similarly, the image signal V
The ID is sampled and written to the liquid crystal capacitance of m rows and 1 column. Thus, the writing of the liquid crystal capacitance from the n-th column to the first column in the m-th row is completed. Or later,
When the scanning signals Ym-1, Ym-2,..., Y1 sequentially become H level, the (m-1) th row, the (m-1) th row,.
In the row, the writing of the liquid crystal capacitance from the nth column to the 1st column is executed in the same manner as in the mth row, and an inverted image of one frame is formed. In this way, a normal image in which the vertical scanning direction is the upward direction and the horizontal scanning direction is the left direction is formed.

<Application Example> In the above-described embodiment, for example, when the circuit block 1450 in a certain stage does not transfer the start pulse DX in the data line driving circuit 140, it is supplied as a control signal to the clocked inverter of the circuit block 1450. The signals to be transferred are the transfer direction control signals Dir-R and Dir-L, but have a constant logical level during the period when the X shift register 1400 should perform the transfer, and the logical level fluctuates according to the transfer direction. Any signal is acceptable. For example, as shown in FIG. 11, when a circuit block 1450 in a certain stage does not transfer a start pulse DX, a control block 1460 in a certain stage generates a signal instead of the transfer direction control signals Dir-R and Dir-L. Fix and Fixinv are the clocked inverters 1451 of the circuit block 1450 in this stage,
1452 may be provided.

Here, as shown in FIG.
ix are signals XL0 and XL output from the circuit block 1450 of each stage when the horizontal scanning direction is the right direction.
It becomes L level during the period when 1,..., XLn are output.
In other periods, while taking an arbitrary logical level, if the horizontal scanning direction is the left direction, the circuit blocks 145 of each stage
.., XRn output from 0, but at an H level during a period during which the signals XR0, XR1,. Also, the signal Fixinv
Are signals XL0, XL1,... Output from the circuit blocks 1450 of each stage when the horizontal scanning direction is the right direction.
,..., Become high during the period during which XLn is output. In the other period, when the horizontal scanning direction is the left direction, the signal output from the circuit block 1450 at each stage. .., XRn are at the L level during a period during which they are output, but are signals at an arbitrary logic level during other periods. Such a configuration is convenient when the transfer direction control signals Dir-L and Dir-R are routed to the analog switches 1472 and 1476, respectively, where there is not enough space.

Further, for example, in the data line driving circuit 140, transfer direction control signals Dir-L and Dir-R whose logical levels are opposite to each other are used as signals indicating the horizontal scanning direction, as shown in FIG. A configuration may be adopted in which a one-phase transfer direction control signal Dir-L is supplied to each stage, and a NOT circuit 1480 is provided in each stage to obtain a signal whose logic level is opposite to the transfer direction control signal Dir-L. In such a configuration, only one transfer direction control signal is supplied to each stage, and accordingly, the number of connection points to the outside is reduced.

Further, both the technique in FIG. 11 and the technique in FIG. 13 may be applied to obtain the configuration shown in FIG. That is, the one-phase signal Fix is supplied to each stage, while the negation circuit 1490 is provided at each stage to provide the signal Fi.
A signal Fixinv having a logical level opposite to x is obtained at each stage, and a one-phase transfer direction control signal Dir-L is supplied to each stage, while a NOT circuit 1480 is provided at each stage.
The transfer direction control signal Dir-L may be configured to obtain a signal whose logic level is opposite to that of the transfer direction control signal Dir-L. Note that the signal Fix may be obtained from the signal Fixinv or the transfer direction control signal Di.
Needless to say, the transfer direction control signal Dir-L may be obtained from rR. Further, in the present embodiment,
The circuit block 1450 transfers the start pulse DY to the right by the clocked inverters 1451, 1452, and 1453, while transferring the start pulse DY to the clocked inverter 145.
1, 1452, and 1454, the transfer is performed in the left direction. However, the present invention is not limited to this. For example, a circuit block may be configured using a plurality of complementary analog switches. Even when the analog switch is used, the clock control circuit replaces the clock signal (inverted clock signal) with the transfer direction control signal (or the signal synchronized therewith) when the circuit block does not participate in the transfer of the start pulse. ) Is not different from the above-described embodiment.

In the above-described electro-optical device 100,
Although the number of stages of the shift registers 1300 and 1400 is odd, this is merely for convenience and may be an even number. Further, in the above-described electro-optical device 100, for example, in the data line driving circuit 140, the NAND circuit 1432 and the NOT circuit 1434 provided in each column perform sampling control on overlapping portions of pulse signals output from adjacent circuit blocks 1450. Although the configuration is such that the signal is obtained as a signal, a configuration may be added in which a logical operation process is performed so that there are no overlapping pulses, and then waveform shaping is further performed.

On the other hand, in the data line drive circuit 140 described above, one sampling switch 151 is driven by the sampling control signal. However, the image signal is distributed to a plurality of systems and expanded a plurality of times on the time axis. Further, the data lines 114 are divided into a plurality of
The configuration may be such that the sampling switches for the number of blocks constituting the block are simultaneously driven. Also, instead of the dot sequential driving in which the sampled image signals are sequentially supplied one data line at a time, the line sequential driving in which the sampled image signals are sequentially latched and then supplied to all the data lines simultaneously may be adopted. .

In addition, the above-mentioned electro-optical device is a liquid crystal display device using liquid crystal as an electro-optical material, and this liquid crystal display device can be applied to any of a transmission type, a reflection type and a transflective type. It is. Further, the present invention can be applied to a passive matrix system as well as an active matrix system. Further, the electro-optical device can be applied to various devices such as an organic EL device, a fluorescent display tube, a plasma display panel, and a digital mirror device.

<Electronic Apparatus> Next, some electronic apparatuses using the electro-optical device according to the above-described embodiment will be described.

<Part 1: Projector> First, a projector using the above-described electro-optical device 100 as a light valve will be described. FIG. 15 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 2100, a lamp unit 2102 including a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is R (red) and G by three mirrors 2106 and two dichroic mirrors 2108 disposed inside.
The light is separated into three primary colors (green) and B (blue), and guided to light valves 100R, 100G, and 100B corresponding to the respective primary colors.

Here, the light valves 100R, 100G
And 100B are basically the same as the electro-optical device 100 according to the above-described embodiment, that is, the transmissive liquid crystal display device. That is, the light valves 100R, 10R
0G and 100B each function as an optical modulator that generates an RGB primary color image. In addition, since the B light has a longer optical path than other R and G lights, the B light is guided through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an emission lens 2124 to prevent the loss. I will

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 2112 from three directions. And
In the dichroic prism 2112, the R and B lights are refracted at 90 degrees, while the G light travels straight.
Thus, a color image obtained by combining the primary color images is projected onto the screen 2120 via the projection lens 2114. Here, when the projector 2100 mounted on a desk is used by suspending the bottom surface of the projector 2100 toward the ceiling, it is necessary to invert the top, bottom, left, and right of the image modulated by the light valve as compared with when the projector is used on a desk. There is
In the present embodiment, as described above, the scanning line driving circuit 130
The vertical scanning direction by the data line driving circuit 1
If the horizontal scanning direction by 40 is the left direction, an inverted image is formed.

<Part 2: Video Camera> Next, an example in which the above-described electro-optical device 100 is applied to a monitor of a handy type video camera will be described. FIG. 16 is a perspective view showing the configuration of the video camera. As shown in this figure, the main body 2210 of the video camera 2200 includes:
In addition to the electro-optical device 100 used as the monitor 10, an optical system 2212, a hand grip 2214, and the like are provided. Here, the electro-optical device 100 has a shaft 2224.
The hinge 2216 is attached to the hinge 2216 so as to be freely rotatable around the hinge 2216. Further, the hinge 2216 is configured to open and close with respect to the main body 2210 around the shaft 2222.

For this reason, in the electro-optical device 100, it is necessary to make the relationship between the top, bottom, left and right of the displayed image inverted between the mode shown in the figure and the mode in which the photographer is located at the back side of the figure and used in the viewfinder. is there. Here, in the present embodiment, as described above, the vertical scanning direction by the scanning line driving circuit 130,
If the horizontal scanning directions by the data line driving circuit 140 are set to be opposite to each other, it is possible to invert the top, bottom, left and right of the display image.

<Summary of Electronic Apparatus> The electronic apparatus is not limited to the example described with reference to FIGS. 15 and 16, and it is necessary to invert the image vertically and horizontally according to various situations. Applicable to all of the devices with

[0078]

As described above, according to the present invention, in a shift register capable of bidirectional transfer, it is possible to reduce the capacity and power consumption of a clock signal line.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an electro-optical device to which a shift register according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a data line driving circuit in the same electro-optical device.

FIG. 3 is a circuit diagram showing a configuration of a clock control circuit and a circuit block in the data line driving circuit.

FIG. 4 is a diagram showing an element configuration in the circuit block.

FIG. 5A is a diagram illustrating an equivalent circuit of a circuit block when the horizontal scanning direction is the right direction, and is a diagram illustrating an equivalent circuit of the circuit block when the horizontal scanning direction is the left direction. .

FIG. 6 is a timing chart showing the operation of the data line driving circuit when the horizontal scanning direction is the right direction.

FIG. 7 is a timing chart showing the operation of the data line driving circuit when the horizontal scanning direction is the left direction.

FIG. 8 is a block diagram illustrating a configuration of a scanning line driving circuit to which the shift register according to the embodiment is applied.

FIG. 9 is a timing chart for explaining a normal rotation image display operation in the electro-optical device.

FIG. 10 is a timing chart for explaining a display operation of a reversed image in the same electro-optical measure.

FIG. 11 is a circuit diagram illustrating a configuration example of a clock control circuit and a circuit block.

FIG. 12 shows signals Fix and Fixinv in the same configuration example.
5 is a timing chart showing signal waveforms of FIG.

FIG. 13 is a circuit diagram illustrating a configuration example of a clock control circuit and a circuit block.

FIG. 14 is a circuit diagram illustrating a configuration example of a clock control circuit and a circuit block.

FIG. 15 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus including the electro-optical device.

FIG. 16 is a perspective view illustrating a configuration of a video camera as an example of an electronic apparatus including the electro-optical device.

[Explanation of symbols]

 100 electro-optical device 105 liquid crystal 112 scanning line 114 data line 116 TFT 118 pixel electrode 130 scanning line driving circuit 140 data line driving circuit 1300 shift register 1350 circuit block 1360 clock control circuit 1400 Shift register 1412, 1414 clock signal line 1450 circuit block 1451-1454 clocked inverter 1460 clock control circuit 2100 projector 2200 video camera

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 623 G09G 3/20 623H 3/36 3/36 F term (Reference) 5C006 AA22 AF69 AF72 BB16 BC03 BC06 BC11 BF03 BF27 EC02 EC11 FA37 FA47 5C080 BB05 DD26 JJ02 JJ03 JJ04 JJ06 KK43

Claims (6)

[Claims] 1. A shift register in which circuit blocks performing transfer in a direction indicated by a logical level of a transfer direction control signal using a clock signal are connected in multiple stages, and an input signal and an output signal in one circuit block are significant. A detection circuit that detects whether the input signal or the output signal is significant, and supplies the clock signal to the circuit block while the detection circuit detects that the input signal or the output signal is significant. If both the signal and the output signal are detected to be insignificant, a signal having a constant logic level during the period in which the transfer is to be performed and having a logic level that varies according to the direction of the transfer is performed by the clock. And a clock control circuit that supplies a signal to the circuit block in place of a signal. 2. The transfer direction control signal, wherein a signal having a constant logic level during a period in which the transfer is to be performed and having a logic level that varies in accordance with the direction of the transfer is the transfer direction control signal. 2. The shift register according to 1. 3. The first and second clocked inverters, which are exclusively enabled according to the logic level of a control signal, and the third clocked inverter, which is exclusively enabled according to the logic level of a transfer direction control signal. And a circuit block including a fourth inverter and a multi-stage circuit block, each time the logic level of the clock signal is inverted, performing a transfer in the direction indicated by the logic level of the transfer direction control signal. A detection circuit for detecting whether an input signal and an output signal in one circuit block are significant; and the clock signal when the input signal or the output signal is detected to be significant by the detection circuit. If both the input signal and the output signal are detected to be insignificant, the transfer direction control signal And a clock control circuit for supplying the control signal to the first and second clocked inverters in the clock circuit. 4. An electro-optical device comprising pixels corresponding to intersections of scanning lines and data lines, wherein a clock signal is used to shift a pulse in a direction indicated by a logical level of a transfer direction control signal. A drive circuit for an electro-optical device in which circuit blocks that output signals on either side of a scanning line or a data line are connected in multiple stages, and detects whether input and output of a pulse in one circuit block are significant. A detection circuit, when the input or output of the pulse signal is detected to be significant by the detection circuit, the clock signal is supplied to the circuit block, and both the input and the output are not significant. If detected, it is at a constant logic level during the period in which the transfer of the pulse is to be performed, and depends on the vertical scanning direction or the horizontal scanning direction. The signal management level varies, the driving circuit of the electro-optical device characterized by comprising a clock control circuit for supplying to the circuit block in place of the clock signal. 5. An electro-optical device comprising a pixel corresponding to an intersection of a scanning line and a data line, wherein a pulse is shifted in a direction indicated by a logic level of a transfer direction control signal using a clock signal. A driving circuit in which circuit blocks for outputting to either side of a scanning line or a data line are connected in multiple stages; a detection circuit for detecting whether a pulse input and an output of one circuit block are significant; When the circuit detects that the input or output of the pulse is significant, it supplies the clock signal to the circuit block, and when it is detected that both the input and the output are insignificant, A signal that has a constant logic level during a period in which the pulse transfer is to be performed, and has a logic level that varies depending on the vertical scanning direction or the horizontal scanning direction. The electro-optical device which comprises a clock control circuit for supplying to the circuit block in place of the clock signal. 6. The electronic apparatus according to claim 5, wherein the display unit includes the electro-optical device.