CN115862559A - Signal transmission method, controller, source driver and electronic device - Google Patents

Abstract

The present disclosure relates to a signal transmission method, a controller, a source driver, and an electronic apparatus. The signal transmission method is used for the controller to transmit the display signal to the source driver. The signal transmission method comprises the following steps: and in one frame of display period, providing display signals to the source driver in at least two modes through the low-voltage differential signal interface, wherein the display signals comprise a plurality of display sub-signals, each display sub-signal comprises a mode identification signal, and the mode identification signals are used for indicating the mode of the display sub-signals to the source driver so as to enable the source driver to process the display sub-signals according to the mode of the display sub-signals. The method realizes a multi-mode transmission operation between the controller and the source driver, thereby realizing multiplexing of a low voltage differential signal interface for providing both image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission and ensuring that various control functions can be flexibly embedded in the source driver.

Description

Signal transmission method, controller, source driver and electronic device

Technical Field

Embodiments of the present disclosure relate to a signal transmission method, a controller, a source driver, and an electronic device.

Background

In the field of display technology, for example, a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines arranged to cross the gate lines. A timing controller (T-con) of the display panel needs to supply gate signals and data signals to a plurality of rows of gate lines and a plurality of columns of data lines through a gate driving circuit and a source driving circuit, respectively, so as to form gray voltages required for each gray scale required for displaying an image in pixel units of each row in a line-by-line scanning manner, for example, and further display an image of one frame.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal transmission method for a controller to transmit a display signal to a source driver, the method including: and in one frame of display period, providing display signals to the source driver in at least two modes through the low-voltage differential signal interface, wherein the display signals comprise a plurality of display sub-signals, each display sub-signal comprises a mode identification signal, and the mode identification signals are used for indicating the mode of the display sub-signals to the source driver so as to enable the source driver to process the display sub-signals according to the mode of the display sub-signals.

An embodiment of the present disclosure provides another signal transmission method for a source driver to receive a display signal from a controller, the source driver including a low voltage differential signal interface, the method including: providing a display signal in one frame display period in at least two modes through a low-voltage differential signal interface receiving controller, wherein the display signal comprises a plurality of display sub-signals, and each display sub-signal comprises a mode identification signal; determining the mode of each display sub-signal according to the mode identification signal aiming at each display sub-signal; and processing each display sub-signal according to the mode to which each display sub-signal belongs.

At least one embodiment of the present disclosure provides a controller for transmitting a display signal to a source driver, the controller including: and the low-voltage differential signal interface is configured to provide display signals to the source driver in at least two modes in one frame display period, wherein the display signals comprise a plurality of display sub-signals, each of the plurality of display sub-signals comprises a mode identification signal, and the mode identification signals are used for indicating the mode to which the display sub-signals belong to the source driver so as to enable the source driver to process the display sub-signals according to the mode to which the display sub-signals belong.

At least one embodiment of the present disclosure provides a source driver for acquiring a display signal from a controller, the source driver including: the low voltage differential signal interface is configured to receive a display signal provided by the controller in at least two modes within one frame display period, wherein the display signal comprises a plurality of display sub-signals, and each display sub-signal comprises a mode identification signal; a mode determination unit configured to determine, for each display sub-signal, a mode to which each display sub-signal belongs, according to the mode identification signal; and the processing unit is configured to process each display sub-signal according to the mode to which each display sub-signal belongs.

At least one embodiment of the present disclosure provides an electronic device, including a controller provided in any one of the embodiments of the present disclosure; in the source driver provided by any of the embodiments of the present disclosure, the source driver is connected to the controller through a low voltage differential signal interface to receive a display signal; and a display panel connected with the source driver to receive a driving signal provided by the source driver, the driving signal being generated based on the display signal.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel;

fig. 1B shows a schematic structural diagram of a connection between the timing controller TCON and the source driver through a mini-LVDS interface;

fig. 1C illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure;

fig. 2A is a schematic diagram illustrating a signal format of a display sub-signal provided in a row configuration mode according to at least one embodiment of the disclosure;

fig. 2B is a schematic diagram illustrating a signal format of a display sub-signal provided in a frame configuration mode according to at least one embodiment of the present disclosure;

fig. 2C is a schematic diagram illustrating a signal format of a display sub-signal provided by a calibration configuration mode according to at least one embodiment of the disclosure;

fig. 3A and 3B are schematic signal formats of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

fig. 4A illustrates a timing diagram of a trigger signal provided by at least one embodiment of the present disclosure;

fig. 4B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure;

fig. 5 is a schematic diagram illustrating a timing relationship of a transmission operation in at least two modes according to at least one embodiment of the present disclosure;

fig. 6A is a timing diagram illustrating display sub-signals provided in a row configuration mode according to at least one embodiment of the disclosure;

fig. 6B is a timing diagram of display sub-signals provided in a frame configuration mode according to at least one embodiment of the disclosure;

fig. 7A illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 7B illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 8 illustrates a schematic block diagram of a controller provided by at least one embodiment of the present disclosure;

fig. 9 illustrates a schematic block diagram of a source driver provided by at least one embodiment of the present disclosure; and

fig. 10 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Various driving circuits for the display panel generally include a scan driving integrated circuit (also referred to as a gate driver or a G-IC), a data driving integrated circuit (also referred to as a source driver or an SD-IC), a controller, and the like. The controller is mainly used to convert data signals, control signals, clock signals, and the like received from the outside (e.g., a signal source such as a storage device, a network modem, and the like) into data signals, gate signals, control signals, clock signals, and the like suitable for the source driver and the gate driver, so as to implement image display driving of the display panel. For example, the Controller may be a Timing Controller (TCON). The source driver is mainly used for receiving the digital signals (display signals or image signals) and control signals and the like provided by the controller, converting the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and inputting the analog gray scale voltage signals into each row of pixel units of a pixel array of the display panel. The gate driver is mainly used for starting pixel units of each row of the pixel array line by line (or interlaced line), for example, and is matched with the source driver under the action of the control signal, and a required data signal is input into the corresponding pixel unit for the started pixel unit line, so that the pixel unit can display according to the data signal.

In the display process of the display panel, the video and the animation are formed by combining a plurality of pictures which are sequentially displayed according to time sequence (for example, the frame rate is 60Hz or 120Hz, and the like), each picture is a frame, namely, one frame of image refers to a complete picture displayed by the display panel. During the display of one frame of image, the gate driver sequentially turns on each row of pixel units in the pixel array from the first row to the last row to scan, and during the scanning, the source driver inputs the data signals required by each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required by one frame of image. For example, due to the process of the pixel units of the display panel, the display screen needs to be continuously refreshed to obtain a clear and complete display effect with good quality, each time the display screen needs to display one frame of image, and the multiple frames of continuously displayed images form a static screen or a dynamic screen in visual effect.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel. As shown in FIG. 1A, the circuit driving system architecture includes a timing controller TCON, a gate driver G-IC, a source driver SD-IC, and a display Panel Panel. The circuit driving system architecture further includes a power management integrated circuit PMIC, a Gamma (Gamma) circuit, a common electrode voltage (Vcom) circuit, and the like.

The input terminal voltage Vin of the power management integrated circuit is, for example, 5V or 12V, and the output voltages include a digital operating voltage DVDD supplied to each IC, an analog voltage AVDD supplied to the Gamma circuit and the Vcom circuit, a gate-on voltage VGH supplied to the gate driver G-IC, a gate-off voltage VGL, and the like. A common electrode voltage (Vcom) circuit is used to supply a common voltage to the pixel array.

The control signals output from the timing controller TCON include control signals supplied to the gate driver G-IC and control signals supplied to the source driver SD-IC. For example, the control signals supplied to the source driver SD-IC include a Start Horizontal (STH) signal at which data transfer starts, a line Clock (CPH) signal, a data transfer control signal Load, and a data polarity inversion signal POL. For example, the control signals supplied to the gate driver G-IC include a frame Start Signal (STV) representing scan on of one frame, a scan Clock signal (CPV), an Enable signal (Enable), and the like.

For example, the input digital interface type of the timing controller TCON may be, for example, a Low-Voltage Differential Signaling (LVDS), an Embedded Display signal (eDP) interface, a V-by-One (Vx 1) interface, and the like. The type of digital interface at the output of the timing controller TCON may be mini-LVDS, for example, for communicating with the source driver SD-IC.

The LVDS interface transmits signals in a line pair form including one clock line pair and several signal line pairs. For example, the LVDS signal line pair includes three control signals: a field sync signal, a line sync signal, and an enable signal. The mini-LVDS interface is similar to the LVDS interface, and signals are transmitted by a differential signal line pair; unlike the LVDS signal line pair, the signal transmitted by the mini-LVDS signal line pair of the mini-LVDS interface does not contain control signals, which are transmitted through a signal line or a signal differential pair independent of the mini-LVDS signal line pair.

Fig. 1B shows a schematic diagram of a connection between the timing controller TCON and the source driver via a mini-LVDS interface. As shown in fig. 1B, the timing controller TCON supplies a control signal and an image data signal to the plurality of source drivers. The plurality of source drivers includes, for example, a source driver SD #1, a source driver SD #2, and the like, the number of source drivers is related to the physical resolution of the display panel, and may need tens or even hundreds for one display panel. Each of the source drivers is connected through a clock signal line pair for transmitting a clock signal, a mini-LVDS signal line pair for transmitting an image data signal, and a control signal line for transmitting a plurality of control signals. The mini-LVDS signal line pair may be 3 pairs of signal lines or 6 pairs of signal lines. The control signal lines may or may not be differential signal pairs. The mini-LVDS signal line and the plurality of control signal lines are independent of each other.

For example, the timing controller TCON and the source driver SD #1 are connected through a mini-LVDS signal line pair transmitting a data signal, a LOAD control signal line transmitting a data transmission control signal LOAD, a POL control signal line transmitting a control signal POL, a POL2 control signal line transmitting a control signal POL2, and the like; the TCON and the source driver SD #2 are also connected via a mini-LVDS signal line pair, a LOAD control signal line, a data polarity inversion control signal line (e.g., a POL control signal line, a POL2 control signal line, a POLC control signal line, etc.), and the like.

Other control signal lines, such as a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, etc., may also be included between each source driver and the TCON.

As shown in fig. 1B, the mini-LVDS signal line pair is used only for transmitting image data signals and is not used for transmitting control signals such as polarity inversion configuration information, data transmission control information, and the like. Therefore, there are a plurality of signal lines and a plurality of signal line interfaces between the timing controller and the source drivers, which results in occupying a large signal routing space in the display panel, and this problem is more pronounced particularly when the number of source drivers is large. Some commonly used control functions cannot be flexibly embedded in the source driver if the available signal routing space in the display panel is not sufficient to accommodate the multiple data lines.

To this end, embodiments of the present disclosure provide a signal transmission method for a controller to transmit a display signal to a source driver. The signal transmission method comprises the steps of providing display signals to a source driver in at least two modes through a low-voltage differential signal interface in one frame display period, wherein the display signals comprise a plurality of display sub-signals, each display sub-signal comprises a mode identification signal, and the mode identification signals are used for indicating the mode of the display sub-signals to the source driver so that the source driver processes the display sub-signals according to the mode of the display sub-signals. The signal transmission method realizes multi-mode transmission operation between the controller and the source driver through the mode identification signal, thereby realizing multiplexing of a low-voltage differential signal interface, enabling the multiplexing to be used for providing image data and configuration data for the source driver, reducing the number of interfaces for signal transmission, and ensuring that various control functions can be flexibly embedded into the source driver.

Fig. 1C illustrates a flow chart of a signal transmission method according to at least one embodiment of the present disclosure. For example, the signal transmission method provided by the embodiment of the disclosure is suitable for both an LVDS interface and a mini-LVDS interface.

As shown in fig. 1C, the signal transmission method includes step S10 and step S20. The signal transmission method provided in fig. 1C is performed by, for example, the timing controller TCON in fig. 1A. For example, the signal transmission method is used for the timing controller TCON to transmit the display signal to the source driver SD-IC.

Step S10: a display signal is acquired.

Step S20: and in one frame of display period, providing display signals to the source driver in at least two modes through the low-voltage differential signal interface, wherein the display signals comprise a plurality of display sub-signals, each display sub-signal comprises a mode identification signal, and the mode identification signals are used for indicating the mode of the display sub-signals to the source driver so as to enable the source driver to process the display sub-signals according to the mode of the display sub-signals.

For step S10, the display signal may comprise, for example, image data and configuration data. For example, the timing controller TCON receives the LVDS differential signal from the outside and parses the LVDS differential signal to separate image data such as RGB data.

In the embodiments provided by the present disclosure, the display signal provided by the low voltage differential signaling interface includes both the configuration data (e.g., control signal) and the image data, and thus a plurality of control signal lines independent of the mini-LVDS signal line or the LVDS signal line are no longer required between the controller and the source driver. For example, the LOAD control signal line, the data polarity inversion control signal line (e.g., the POL control signal line, the POL2 control signal line, the POLC control signal line, etc.), the horizontal DOT inversion (H2 DOT) control signal line, the bias voltage (PWRC) control signal line, etc., in fig. 1B may be omitted. For example, the signal transmission method provided in the embodiment of the present disclosure is such that only a mini-LVDS signal line and a clock signal line are included between the source driver and the controller, and each of the source driver and the controller may include only a mini-LVDS interface and a clock signal interface. Of course, the source driver and the controller may each include other interfaces as well as spare, for example, a LOAD control signal line, a data polarity inversion control signal line POL, and the like.

Accordingly, embodiments of the present disclosure reduce the number of interfaces and signal lines for signal transmission, and ensure that various control functions can be flexibly embedded in a source driver.

For example, the configuration data may be generated by a timing control module in the timing controller. The configuration data is used to configure the source driver such that after the source driver receives and stores the configuration data, the image data is processed according to the configuration data. For example, the source driver outputs image data to the pixel array according to the timing provided by the configuration data.

In some embodiments of the present disclosure, the configuration data includes control signals required in the process of displaying the RGB data by the pixel array. For example, if the display panel is a liquid crystal display panel and the liquid crystal display panel needs to control the polarity of liquid crystal molecules during the RGB data display process, the control signal may include a data polarity inversion control signal (e.g., a POL control signal, a POL2 control signal, and a POLC control signal). For another example, a start signal of line data is required in the process of displaying RGB data by the pixel array, and the control signal may include a start signal STH of line data. For another example, the display panel may also be an OLED display panel or the like, for example, and the embodiment of the present disclosure is not limited thereto.

The configuration data may be set by those skilled in the art according to actual needs, and the present disclosure does not limit the configuration data, and the data polarity inversion control signal, the frame scanning start signal, and the start signal of the line data are merely examples.

With respect to step S20, in an embodiment of the present disclosure, the low voltage differential signal interface includes a plurality of pairs of transmission lines, each pair of transmission lines including two complementary differential signals, through which image data and configuration data are transmitted. For example, the low voltage differential signal interface may be a mini-LVDS interface, an LVDS interface, or the like.

The one-Frame display Period includes, for example, an image display Period (Active Frame) and a Vertical Blanking Period (VBP). During image display, for example, pixels in the pixel array display image data line by line, and during the vertical blanking interval, preparation is made for display of the next frame of image data.

In some embodiments of the present disclosure, display signals are provided to the source driver in at least two modes in sequence, for example, through a low voltage differential signaling interface.

For example, the display signal includes at least one display sub-signal provided in each of at least two modes.

For example, each mode provides a display sub-signal that includes configuration data and image data. For another example, the at least two modes include a first mode and a second mode, the first mode including the configuration data and the image data, and the second mode including the configuration data. As another example, the first mode includes configuration data and the second mode includes image data.

In some embodiments of the present disclosure, at least one of the at least two modes is a row configuration mode, the configuration data comprises row configuration data, and the display sub-signal provided by the row configuration mode comprises row configuration data and row image data.

The display sub-signals provided by the row configuration mode configure the source drivers for display of image data for a row of pixels. The line image data is, for example, RGB data corresponding to the line in the pixel array. The row configuration data is used to configure the source driver so that the source driver outputs the row image data and timing control signals, etc. to the row of pixels in response to the row configuration data.

In some embodiments of the present disclosure, at least one of the at least two modes is a frame configuration mode. The configuration data comprises frame configuration data and the display sub-signals provided by the frame configuration mode comprise frame configuration data.

The display sub-signals provided by the frame configuration mode are used to configure the source driver for the display of a frame of image. The frame configuration data is used, for example, to configure the source driver so that the source driver outputs a control signal for the frame image. The frame configuration data may include, for example, a Gamma (Gamma) setting signal, an Amplification (AMP) offset control signal, a shift direction selection signal, and the like.

In some embodiments of the present disclosure, at least one of the at least two modes includes a correction configuration mode, the configuration data includes a correction signal, and the display sub-signal provided by the correction configuration mode includes a correction signal, for example, the correction signal is used to correct timing of a clock signal and a display signal of the source driver.

In an embodiment of the present disclosure, each display sub-signal provided by the row configuration mode, each display sub-signal provided by the frame configuration mode, and each display sub-signal provided by the correction configuration mode each include a pattern recognition signal for distinguishing whether the display sub-signal is provided by the controller in the row configuration mode, the controller in the frame configuration mode, or the controller in the correction configuration mode.

In some embodiments of the present disclosure, the display signals are provided to the source driver through the low voltage differential signaling interface in at least two modes of signal formats defined by the first signaling protocol. The signal formats of at least two modes defined by the first signal transmission protocol are exemplified below with reference to fig. 2A to 2C.

Fig. 2A is a schematic diagram illustrating a signal format of a display sub-signal provided in a row configuration mode according to at least one embodiment of the present disclosure.

The first display sub-signal and the second display sub-signal provided to the source driver in the row configuration mode are shown in the example of fig. 2A. It should be understood that the first display sub-signal and the second display sub-signal are only signal formats for illustrating the display sub-signals provided in the row configuration mode, and do not mean that the two display sub-signals are provided to the source driver only in the row configuration mode, and actually, the number of the display sub-signals provided to the source driver in the row configuration mode may be the same as the number of rows of the pixel array, that is, the display sub-signals are provided to each row of pixels in the row configuration mode, respectively.

As shown in fig. 2A, the display sub-signal provided by the row configuration mode includes a mode identification signal a to indicate that the display sub-signal belongs to the row configuration mode.

As shown in fig. 2A, the display sub-signals provided by the line configuration mode include line configuration data and line image data (e.g., RGB data for one line of pixels). Hereinafter, in the embodiments of the present disclosure, RGB (red green blue) data is taken as an example of image data, but it is to be noted that the present disclosure is not limited thereto, and for example, some display devices may also employ image data in the form of, for example, RGBW (red green blue white) or the like. For example, the first display sub-signal includes first line configuration data and first line RGB data, and the second display sub-signal includes second line configuration data and second line RGB data.

The first row RGB data is RGB data of an optional row of sub-pixels in the pixel array, and the first row arrangement data is arrangement data corresponding to the RGB data of the row of sub-pixels at all times.

In some embodiments of the present disclosure, as shown in fig. 2A, the display sub-signal provided by the row configuration mode includes: and combination data which combines the line arrangement data of each line and the line image data of each line in the image data. For example, the first display sub-signal is formed by combining the first row configuration data and the first row RGB data, and the second display sub-signal is formed by combining the second row configuration data and the second row RGB data. That is, the controller sequentially supplies the display sub-signals corresponding to each row of pixels to the source driver. In this embodiment, the configuration data and the image data of one row are combined and transmitted through the low voltage differential signal interface, so that not only is multiplexing of the low voltage differential signal interface realized, but also the source driver can timely process the image data of each row according to the configuration data of each row so as to facilitate image display.

In the signal format example shown in fig. 2A, for each display sub-signal, the row configuration data is located in front of the RGB data, i.e. for each display sub-signal, the controller supplies the row configuration data to the source driver first, and then supplies the RGB data for that row to the source driver. Providing the line configuration data to the source driver first and then providing the RGB data for the line to the source driver can facilitate the source driver to process the RGB data for the line in time according to the line configuration data.

Fig. 2B is a schematic diagram illustrating a signal format of a display sub-signal provided in a frame configuration mode according to at least one embodiment of the present disclosure.

As shown in fig. 2B, the frame configuration mode provides a display sub-signal including frame configuration data and invalid data.

As shown in fig. 2B, the display sub-signal provided by the frame configuration mode includes a mode identification signal B to indicate that the display sub-signal belongs to the frame configuration mode.

In some embodiments of the present disclosure, for example, a frame configuration mode is applied to the vertical blanking period. During the vertical blanking period, the pixel array does not display image data, and thus the display sub-signals provided by the frame configuration mode may include invalid data.

In other embodiments of the disclosure, if the data length of the frame configuration data is the same as the data length of the combined data provided by the row configuration mode, the display sub-signal provided by the frame configuration mode may not include invalid data. In embodiments of the present disclosure, invalid data may refer to, for example, a data signal at a logically invalid level.

In the signal format example shown in fig. 2B, for each display sub-signal, the frame configuration data precedes the invalid data, i.e., for each display sub-signal, the controller provides the frame configuration data to the source driver first, and then provides the invalid data to the source driver.

Fig. 2C is a schematic diagram illustrating a signal format of a display sub-signal provided by a calibration configuration mode according to at least one embodiment of the disclosure.

As shown in fig. 2C, the display sub-signals provided by the calibration configuration mode include calibration signals. For example, in at least one example, the correction signal may include, for example, a delay time length of the clock signal or a data signal used to calculate the delay time length of the clock signal, or the like. The correction signal can be set by a person skilled in the art according to the relevant correction method. In some embodiments of the present disclosure, the controller provides the correction signal to the source driver in a correction configuration mode during the vertical blanking interval.

For example, the transmission of the display signal depends on a clock signal. For example, ideally, the edge transitions of the clock signal are aligned with the middle instants at which the display signal is at the active logic level, but due to the delay of the clock signal or the display signal in practice, the edge transitions of the clock signal are not aligned with the middle instants at which the display signal is at the active logic level, and therefore correction of the clock signal or the display signal, for example, is required. The correction signal is used, for example, to align the transition edges of the clock signal with the middle time when the display signal is at an active logic level.

As shown in fig. 2C, the display sub-signal provided by the correction configuration mode includes a mode identification signal C to indicate that the display sub-signal belongs to the correction configuration mode.

In some embodiments of the present disclosure, the at least two transmission modes include: at least two of a row configuration mode, a frame configuration mode, and a correction configuration mode.

For example, the at least two modes include a row configuration mode and a frame configuration mode, the row configuration mode providing a display sub-signal comprising row configuration data and image data, and the frame configuration mode providing a display sub-signal comprising frame configuration data. For the explanation of the row configuration mode and the frame configuration mode, refer to the above description.

In some embodiments of the present disclosure, the at least two modes further include a correction configuration mode, the display sub-signals provided by the correction configuration mode include correction signals, and the correction signals are used for correcting the timing of the clock signals of the source driver and the display signals. For an explanation of the correction configuration mode, refer to the above description.

In some embodiments of the present disclosure, since the RGB image data need to be transmitted during the image display period and the RGB image data need not be transmitted during the vertical blank period, the display sub-signals are transmitted in different modes during the image display period and the vertical blank period, respectively.

For example, the at least two modes include a row configuration mode and a frame configuration mode. And transmitting display sub-signals required for displaying image data of each row of pixels to the source driver in a row configuration mode during image display, and transmitting the display sub-signals required for a vertical blanking period to the source driver in a frame configuration mode during the vertical blanking period. For example, the frame configuration mode and the correction configuration mode are during a vertical blanking period within one frame display period. The frame configuration mode and the correction configuration mode enable the source driver to perform frame configuration and timing correction in the vertical blanking period to prepare for display of the next image frame during the vertical blanking period, and the frame configuration and timing correction are performed during the vertical blanking period, so that time is saved and display efficiency is improved.

In some embodiments of the present disclosure, the frame configuration mode includes a power consumption control sub-mode that provides the processing signal for the source driver during at least the vertical blanking period for controlling (e.g., reducing) the power consumption of the source driver during at least the vertical blanking period, controlling the overall power consumption of the system.

For example, power consumption configuration sub-data for reducing power consumption of the source driver at least during the vertical blanking period is included in the frame configuration data. For example, the source driver enters a low power consumption operating state in response to the power consumption configuration sub-data, in which at least a portion of the circuit blocks of the source driver are powered down, thereby reducing power consumption of the source driver at least during vertical blanking. The processing signal provided by the power consumption control submode may be, for example, a logic inactive level. In the embodiment of the present disclosure, for example, the logic inactive level may be a low level signal representing the process signal "0", and the logic active level may be a high level signal representing the process signal "1", for example. During the period that the source driver is in the low power consumption operation state, the controller provides a logic inactive level to the source driver to reduce power consumption during the vertical blanking period. For example, the power consumption configuration sub-data includes at least a portion of the circuit modules that the source driver disables during the vertical blanking period. Those skilled in the art may define the circuit modules disabled during the vertical blanking period into the power consumption configuration sub-data to issue the disabled circuit modules to the source driver, so that the source driver disables the circuit modules in the power consumption configuration sub-data during the vertical blanking period. In some embodiments of the present disclosure, disabling a circuit block may refer to powering down the circuit block.

For example, the circuit module disabled in the vertical blanking device indicated by the power consumption configuration subdata includes an output driver, and the source driver is configured to power down the output driver during the vertical blanking.

In some embodiments of the present disclosure, each display sub-signal comprises a data signal. That is, each display sub-signal includes a data signal in addition to the pattern recognition signal. The data signal may comprise, for example, the image data and configuration data described above. Sequentially providing the display signals to a source driver in at least two modes through a low voltage differential signal interface, comprising: the method comprises the steps of sequentially providing a plurality of display sub-signals to a source driver in at least two modes by using a low voltage differential signal interface, and for each display sub-signal, providing a data signal to the source driver through the low voltage differential signal interface after providing a mode identification signal to the source driver through the low voltage differential signal interface.

For example, for the display sub-signals provided in the row configuration mode, the controller provides the mode identification signal a to the source driver through the low voltage differential signal interface, and then provides the row configuration data and the row image data to the source driver through the low voltage differential signal interface.

As shown in fig. 2A to 2C, the mode identification signal of the display sub-signal provided in each mode may be located before the configuration data, that is, the controller provides the mode identification signal of each display sub-signal to the source driver first, and then provides the configuration data of the display sub-signal to the source driver. For example, for the line configuration mode, the controller provides the pattern recognition signal a to the source driver, then provides the line configuration data to the source driver, and then provides the line image data to the source driver. For another example, for the frame configuration mode, the controller provides the mode identification signal B to the source driver, then provides the frame configuration data to the source driver, and then provides the invalid data to the source driver. For another example, for the calibration configuration mode, the controller provides the mode identification signal C to the source driver before providing the calibration signal to the source driver. In an embodiment of the present disclosure, the invalid data may be, for example, a logic invalid level signal, such as a low level signal.

The pattern recognition signal is located in front of the configuration data, so that the source driver can correctly analyze and process subsequently received data in time according to the pattern to which the display sub-signal belongs to obtain row configuration data, frame configuration data or a correction signal and the like.

Fig. 3A and 3B are schematic diagrams illustrating a signal format of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure.

As shown in fig. 3A, in one frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 301 supplied in a line configuration mode, a display sub-signal 302 supplied in a frame configuration mode, and a display sub-signal 303 supplied in a correction configuration mode.

For example, the plurality of display sub-signals 301 are provided in a row configuration mode during image display, the display sub-signals 302 are provided in a frame configuration mode during vertical blanking and the display sub-signals 303 are provided in a correction configuration mode.

As shown in fig. 3A, providing display signals to the source driver in at least two modes through the low voltage differential signal interface during one frame display period includes: and sequentially providing the display signals to the source driver in at least two modes by using the low voltage differential signal interface during one frame display period, and sequentially providing one or more display sub-signals to the source driver by using the low voltage differential signal interface for each mode.

For example, in the example of fig. 3A, the plurality of display sub-signals 301 are provided to the source driver in a row configuration mode, the display sub-signals 302 are provided to the source driver in a frame configuration mode, and the display sub-signals 303 are provided to the source driver in a correction configuration mode using the low voltage differential signaling interface. For example, for a row configuration mode comprising a plurality of display sub-signals 301, the plurality of display sub-signals 301 are provided to the source driver in sequence using a low voltage differential signal interface. That is, in the example of fig. 3A, the plurality of display sub-signals 301 are provided to the source driver by using the low voltage differential signal interface, the display sub-signals 302 are provided to the source driver by using the low voltage differential signal interface, and the display sub-signals 303 are provided to the source driver by using the low voltage differential signal interface.

As shown in fig. 3A, each display sub-signal 301 provided in the line arrangement mode includes line data LPC and image data (e.g., RGB data). As shown in fig. 3B, the line data LPC includes a pattern recognition signal a and line configuration data. For example, the mode identification signal a includes a RESET signal RESET and a row mode Start signal LPC Start. For example, the row mode start signal may be a logic inactive level, e.g., "000". For the pattern identification signal and the row configuration data of the row configuration pattern, refer to the above description.

As shown in fig. 3A, each display sub-signal 302 provided in the frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The display sub-signals provided in the frame configuration mode include the data signals 312 provided in the power consumption control sub-mode. As shown in fig. 3B, the frame data FPC includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the frame data FPC is a RESET signal RESET and a frame pattern Start signal FPC Start. For example, the frame mode start signal may be different from the row mode start signal, e.g., a logic active level such as "111", to distinguish between the frame configuration mode and the row configuration mode. For the pattern recognition signal and the frame configuration data of the frame configuration pattern, refer to the above description.

During the time that the controller provides the data signal 312 (including the invalid data IDLE0 and the invalid data IDLE 1) to the source driver in the power consumption configuration sub-mode, at least a part of the circuit blocks in the source driver are in a power-down state to save power consumption.

As shown in fig. 3A, the frame configuration mode includes a power consumption control sub-mode. The display sub-signal 302 provided in the frame configuration mode includes a processing signal provided to the source driver in the power consumption control sub-mode, the processing signal including, for example, the invalid data IDLE0 and the invalid data IDLE1. During the period that the controller provides the invalid data IDLE0 and the invalid data IDLE1 to the source driver in the power consumption control sub-mode, at least part of the circuit modules in the source driver are in a power-down state to save power consumption. In the example of fig. 3A, before the invalid data IDLE0 is supplied to the source driver in the power consumption control sub-mode, the controller supplies the trigger signal PSI to the source driver again to instruct the source driver to enter the low power consumption operation state.

As shown in fig. 3A, each display sub-signal 303 provided in the correction configuration mode includes correction data ASC. As shown in fig. 3B, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C may be, for example, a logic inactive level. For the calibration signal, refer to the above description.

As shown in fig. 3A, after the display signal for one frame display period is transmitted to the source driver, the transmission of the display signal for the next frame display period to the source driver is continued.

As shown in fig. 3A, before each display sub-signal is provided to the source driver, a trigger signal is provided to the source driver to inform the source driver to perform a transmission operation for at least two modes.

In some embodiments of the present disclosure, the controller may transmit the display signal to the source driver through a single mode in addition to transmitting the display signal to the source driver in at least two modes.

In this embodiment, the source driver is notified of the at least two modes of transmission operation by the trigger signal, which facilitates compatibility between the source driver and the controller with other transmission operations than the at least two modes of transmission operation, providing compatibility. For example, a single mode transfer operation may be compatibly performed between the controller and the source driver in addition to the transfer operation through at least two modes. For example, the display signals that may be transmitted in at least two modes conform to a first signaling protocol, and the display signals that may also be transmitted to the source driver in a single mode conform to a second signaling protocol. If the controller and the source driver execute the transmission operation of at least two modes, the controller firstly provides a trigger signal to the source driver as an indication signal of the transmission operation of at least two modes; if the controller and the source driver execute the single-mode transmission operation, the controller firstly provides a single-mode indication signal different from the trigger signal to the source driver. The second signal transmission protocol may be some other protocol than the first signal transmission protocol, for example, some transmission protocols in the related art. The signal line multiplexing can be realized by setting the trigger signal, so that the chip has multiple functions, and the difficulty of popularization of the first signal transmission protocol is reduced.

In some embodiments of the present disclosure, the trigger signal includes at least one trigger sub-signal, and providing the trigger signal to the source driver includes: and sequentially providing at least one trigger sub-signal to the source driver, wherein each trigger sub-signal comprises a set timing relation between the data transmission control signal and the data polarity inversion control signal.

In some embodiments of the present disclosure, for example, the trigger signal includes two trigger sub-signals. The source driver determines to perform a signal transmission operation in at least two modes in response to receiving two consecutive trigger sub-signals. By using the plurality of trigger sub-signals as the trigger signals, noise interference can be at least partially avoided, and the accuracy of pattern recognition is improved.

In some embodiments of the present disclosure, the setting of the timing relationship between the data transfer control signal and the data polarity inversion control signal comprises: the first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge is at least partially time coincident with a second transition state of the data transmission control signal after the second transition edge.

The data polarity inversion control signal controls the polarity inversion of the data signal output by the source driver through the switching of high and low levels so as to realize the alternating current driving of the liquid crystal. The data transfer control signal is used to latch data and a data polarity inversion signal input to the source driver at a rising edge, and the falling edge controls the release of the data to the panel.

In this example, the controller and the source driver may be connected through a mini-LVDS signal line, a POL signal line, and a LOAD signal line, and thus other lines such as a POL2 control signal line and a POLC control signal line, a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, and the like may be omitted entirely or partially. Therefore, this example can not only reduce the number of signal lines between the controller and the source driver, but also inform the source driver which kind of transfer operation is performed to be compatible with the transfer operation of the single mode.

Fig. 4A illustrates a timing diagram of a trigger signal according to at least one embodiment of the present disclosure.

As shown in fig. 4A, the trigger signal includes at least two (two, three, or more) trigger sub-signals. For example, in the case of two trigger sub-signals, the trigger signal includes a trigger sub-signal PSI1 and a trigger sub-signal PSI2.

The trigger sub-signal PSI1 and the trigger sub-signal PSI2 both include a data transmission control signal LOAD and a data polarity inversion control signal POL, and a predetermined timing relationship is satisfied between the data transmission control signal LOAD and the data polarity inversion control signal POL.

As shown in fig. 4A, the timing relationship is set such that a first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than a second transition edge (e.g., rising edge) of the data transmission control signal LOAD, and a first transition state (e.g., high state) of the data polarity inversion control signal POL after the first transition edge is at least partially temporally coincident with a second transition state (e.g., high state) of the data transmission control signal LOAD after the second transition edge. The time interval tLD _ RST is a time interval between a rising edge of the data transmission control signal LOAD and the reset signal, as described with reference to fig. 5. For example, the source driver determines to perform at least two modes of transmission operation in response to receiving a rising edge of the data polarity inversion control signal POL in the second trigger sub-signal.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL is later than the data transmission control signal LOAD by a time length tS2 in the same period of the data transmission control signal LOAD and the data polarity inversion control signal POL, so that the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD. The data polarity inversion control signal POL and the data transmission control signal LOAD are simultaneously in a high state for a time length tH2 after the rising edge.

Fig. 4B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure.

As shown in fig. 4B, the single mode indication signal includes the data transmission control signal LOAD 'and the data polarity inversion control signal POL', and a first transition edge (e.g., a rising edge) of the data polarity inversion control signal POL 'is earlier than a second transition edge (e.g., a rising edge) of the data transmission control signal LOAD', and a first transition state (e.g., a high state) of the data polarity inversion control signal POL 'after the first transition edge is at least partially time-coincident with a second transition state (e.g., a high state) of the data transmission control signal LOAD' after the second transition edge.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL 'is earlier than the data transmission control signal LOAD' by the time length tS1 in the same period of the data transmission control signal LOAD 'and the data polarity inversion control signal POL', so that the rising edge of the data polarity inversion control signal POL 'is earlier than the rising edge of the data transmission control signal LOAD'.

The embodiment of fig. 4A and 4B can distinguish between the single mode transmission operation and the at least two modes of transmission operation by the data transmission control signal and the data polarity inversion control signal, and is easy to implement without modifying the hardware circuit of the interface. In this way, the same set of controller and source driver can selectively implement the first signaling protocol or the second signaling protocol as needed without providing a set of controller and source driver for the first signaling protocol and the second signaling protocol, respectively, and thus the cost of design, development, manufacturing, and management can be reduced for the supplier.

Fig. 5 is a schematic diagram illustrating a timing relationship of a transmission operation in at least two modes according to at least one embodiment of the present disclosure.

As shown in fig. 5, in this example, the signals for the transmission operation in at least two modes include a data transmission control signal LOAD, a data polarity inversion control signal POL, and a low voltage differential signal.

It should be noted that the low-voltage differential signal is transmitted by a plurality of differential signal line pairs, for example, 3 differential signal line pairs or 6 differential signal line pairs, each of which serves as a signal transmission channel. Since each differential signal line pair transmits signals in a similar manner, only the timing relationship between one signal transmission channel LV0 and the data transmission control signal LOAD, the data polarity inversion control signal POL is shown in the example of the present disclosure.

As shown in fig. 5, the controller provides the data transfer control signal LOAD and the data polarity inversion control signal POL as trigger signals to the source driver in a set timing relationship. In the example of fig. 5, only one trigger sub-signal PSI is shown as trigger signal.

After the trigger signal is provided to the source driver, a time interval length t _HD Thereafter, the pattern recognition signal and the configuration data are provided to the source driver.

For example, if the display sub-signals are supplied to the source drivers in a row configuration mode, then for a time period t _HD Thereafter, the controller sequentially provides the reset signal and the row mode start signal to the source driver as a mode recognition signal of the row configuration mode. For example, a person skilled in the art may set a first time length t between a rising edge of the data polarity inversion control signal POL and a rising edge of the data transfer control signal LOAD in the timing controller _SET A time interval tLD _ RST between a rising edge of the data transmission control signal LOAD and the reset signal, thereby calculating a data polarity inversion control signalTime length t between rising edge of number POL and reset signal _HD . Alternatively, one skilled in the art may directly set the time length t between the rising edge of the data polarity inversion control signal POL and the reset signal _HD 。

After providing the pattern recognition signal to the source driver, the controller provides the row configuration data to the source driver. Thereafter, the line image data is supplied to the source driver.

In some embodiments of the present disclosure, the row configuration data may be, for example, a row data packet including 16 bits, such as a row data packet including a 0 th bit data LPC [0], a 1 st bit data LPC [1], \8230; a 15 th bit data LPC [15].

Table one illustrates an exemplary definition of a row data packet provided by at least one embodiment of the present disclosure.

Watch 1

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a start of frame indication signal. For example, bit 0 LPC [0] of a row of data packets is the start of frame indicator. In the row configuration data of the first display row of each frame, LPC [0] is, for example, high level.

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a data polarity inversion control signal. For example, the 1 st bit LPC [1] of the row data packet is the data polarity inversion control signal POL; the 2 nd bit LPC 2 of the line data packet is a data polarity reversal control signal POLC; the 3 rd bit LPC [3] of the row data packet is the data polarity inversion control signal POL2.

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a charge sharing function control signal. For example, the 4 th bit to the 7 th bit of the line data packet, i.e., LPC [ 4.

As shown in table one, in a row configuration data provided in the present disclosure, a reserved bit is further included for flexibly adding some row configurations, so as to improve configuration flexibility. For example, bits 8 to 15, i.e., LPC [ 8.

It should be noted that table one is merely an example of a row packet definition, and has no limiting effect on the embodiments of the present disclosure. Other definitions of a row of data packets may be devised by those skilled in the art. For example, the row packet may be 8 bits, 32 bits, 64 bits, or the like.

For example, if the display sub-signals are provided to the source driver in the frame configuration mode, then the time period t is longer _HD Thereafter, the controller sequentially supplies the reset signal and the frame mode start signal to the source driver as a mode recognition signal of the frame configuration mode. The controller provides the frame configuration data to the source driver after providing the pattern recognition signal of the frame configuration pattern to the source driver.

In some embodiments of the present disclosure, the frame configuration data may be, for example, a frame data packet including 256 bits, e.g., the frame data packet includes a 0 th bit data FPC [0], a 1 st bit data FPC [1], \ 8230; \8230;, a 255 th bit data FPC [255].

Table two illustrates an exemplary definition of a frame data packet provided in at least one embodiment of the present disclosure.

Watch two

As shown in table two, in one frame configuration data provided by the present disclosure, the frame configuration data includes receiver offset setting, receiver enable setting, display data inversion, shift direction selection, amplification (AMP) offset control, channel amplifier chopping control, gamma buffer chopping control, channel number control, source driver Identification (ID).

For example, in some embodiments of the present disclosure, the frame configuration data further includes a configuration of differential signal line pairs. For example, in the example of Table two, bit 21 FPC [21] of the frame configuration data represents the configuration of the differential signal line pairs. For example, if FPC [21] is 0, it means that 3 pairs of differential signal lines are used to transmit display signals; if FPC [21] is 1, it means that the display signal is transmitted using 6 pairs of differential signal lines. In the embodiment of the present disclosure, for example, "1" represents a high level and "0" represents a low level.

For example, in the example of Table two, the 22 nd bit FPC [22] of the frame configuration data represents the bits transmitted per cycle. For example, if FPC [22] is 0, it means 6 bits are transmitted per cycle; if FPC [22] is 1, it means 8bit is transmitted per cycle.

It should also be noted that table two is merely an example of one frame data packet definition, and has no limiting effect on the embodiments of the present disclosure. Other frame data packet definitions may be devised by those skilled in the art. For example, the frame data packet may be 8 bits, 32 bits, 64 bits, or the like.

For example, if the display sub-signals are provided to the source driver in the correct configuration mode, then for a time period t _HD Thereafter, the controller provides the logic inactive level to the source driver as a pattern recognition signal for correcting the configuration pattern. After providing the logically inactive level to the source driver, a correction signal is provided to the source driver. The logic inactive level lasts for the same length of time as the reset signal, for example. The length of time for which the logic inactive level is set may be set as desired by those skilled in the art.

Fig. 6A illustrates a timing diagram of display sub-signals provided in a row configuration mode according to at least one embodiment of the present disclosure.

As shown in fig. 6A, the timing chart includes a clock signal CLK, a data transfer control signal LOAD, a data polarity inversion control signal POL, and a low voltage differential signal. Only one signal transmission channel LV0 in the low voltage differential signal is shown in the figure.

As shown in fig. 6A, the controller provides the data transfer control signal LOAD and the data polarity inversion control signal POL as trigger signals to the source driver in a set timing relationship.

In-direction source driveAfter the trigger signal is provided by the actuator, the time interval t _HD Thereafter, the RESET signal RESET and the row mode Start signal LPC Start are supplied to the source driver as the mode identification signal of the row configuration mode. As shown in fig. 6A, the row mode Start signal LPC Start may be a digital logic signal 0, and in the embodiment of the present disclosure, the digital logic signal 0 is represented by a low level signal, for example.

As shown in fig. 6A, the controller may provide a RESET signal RESET to the source driver for N clock cycles, N > =1.

After the controller provides the RESET signal RESET and the row mode Start signal LPC Start to the source driver, the controller provides a row data packet, for example, including 16 bits, to the source driver.

After the controller provides the line data packet to the source driver, the controller provides line image data, such as image data D0, image data D1, image data D2, and image data D3, to the source driver.

Fig. 6B is a timing diagram of display sub-signals provided in a frame configuration mode according to at least one embodiment of the disclosure.

As shown in fig. 6B, the timing chart includes a clock signal CLK, a data transfer control signal LOAD, a data polarity inversion control signal POL, and a low voltage differential signal. Only one signal transmission channel LV0 in the low voltage differential signal is shown in the figure.

As shown in fig. 6B, the controller provides the data transfer control signal LOAD and the data polarity inversion control signal POL as trigger signals to the source driver in a set timing relationship.

After the trigger signal is provided to the source driver, a time interval length t _HD Thereafter, the RESET signal RESET and the frame mode Start signal FPC Start are supplied to the source driver as the mode identification signal of the frame configuration mode. As shown in fig. 6B, the frame mode Start signal FPC Start may be a digital logic signal 1, and in the embodiment of the present disclosure, the digital logic signal 1 is represented by a high level signal, for example.

As shown in fig. 6B, the controller may provide a RESET signal RESET to the source driver for N clock cycles, N > =1.

After the controller provides the RESET signal RESET and the frame mode Start signal FPC Start to the source driver, the controller provides a frame data packet, for example, including 256 bits, to the source driver.

After the controller provides the frame data packet to the source driver, the controller provides the invalid data IDLE0 to the source driver.

As shown in fig. 6B, after the controller provides the invalid data IDLE0 to the source driver, the controller provides at least one trigger sub-signal PSI to the source driver again to instruct the source driver to enter the low power consumption operation state.

In some embodiments of the present disclosure, a time length of the frame configuration data and the combination data for the invalid data IDLE0 is the same as a data length of the combination data provided in the row configuration mode.

In some embodiments of the present disclosure, the signal transmission method is applied to a display device. In the process of starting up the display device, the display signals transmitted between the controller and the source driver are the display sub-signals provided by the correction configuration mode and the display sub-signals provided by the frame configuration mode in sequence; and after the display device enters the working state, the display signals transmitted between the controller and the source driver are sequentially the display sub-signals provided by the row configuration mode, the display sub-signals provided by the frame configuration mode and the display sub-signals provided by the correction configuration mode.

In the process of starting up the display device, the controller firstly provides a correction signal to the source driver and then provides frame configuration data to the source driver, so that the controller prepares for image display in advance. During the power-on of the display device, no image display is performed, and thus it is not necessary to provide the display sub-signals to the source driver in the row configuration mode. After the source driver is configured according to the correction signal and configured according to the frame configuration data, the display apparatus enters an operating state. After the display device enters an operating state, the controller provides a plurality of display sub-signals to the source driver in a row configuration mode, a frame configuration mode, and a correction configuration mode.

For example, the controller first configures data and line image data to the source driver lines in a line configuration mode so that the display device sequentially displays the image data of each line to display a complete image of one frame. After the display device displays a complete image of one frame, a vertical blank period is entered. During the vertical blanking period, the controller first provides frame configuration data to the source driver in a frame configuration mode, so that the source driver performs frame configuration. For example, the source driver enters a low power consumption state according to the frame configuration data, and thereafter, the controller provides a logic inactive level to the source driver in the correct configuration mode. During the vertical blanking interval, the source driver is configured according to the frame configuration data and the correction configuration data to prepare for display of the next frame image.

Fig. 7A illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure.

As shown in fig. 7A, the signal transmission method includes steps S710 to S730. The signal transmission method shown in fig. 7A is performed by the source driver SD-IC in fig. 1A, for example. For example, the signal transfer method is for the source driver SD-IC to receive the display signal transferred from the timing controller TCON.

Step S710: and providing a display signal in one frame display period in at least two modes through the low-voltage differential signal interface receiving controller, wherein the display signal comprises a plurality of display sub-signals, and each display sub-signal comprises a mode identification signal.

Step S720: and determining the mode of each display sub-signal according to the mode identification signal aiming at each display sub-signal.

Step S730: and processing each display sub-signal according to the mode of each display sub-signal.

For step S710, for example, in the example of fig. 1B, the controller TCON transmits a display signal within one frame display period to the source driver SD #1, the source driver SD #2, and the like through its own low voltage differential signal interface. The source driver SD #1, SD #2, and the like receive the display signal from the controller TCON through their own low voltage differential signal interfaces. Please refer to the above description for at least two modes and one frame display period.

For the description of step S720, please refer to the above.

For example, if the pattern recognition signal is the pattern recognition signal a shown in fig. 3B, the pattern to which the sub-signal belongs is displayed as the row configuration pattern.

For example, if the pattern recognition signal is the pattern recognition signal B shown in fig. 3B, the mode to which the display sub-signal belongs is the frame configuration mode.

For example, if the pattern recognition signal is the pattern recognition signal C shown in fig. 3B, the pattern to which the sub-signal belongs is the calibration configuration pattern.

After determining the mode to which the display sub-signal belongs according to the mode identification signal, the source driver parses the display sub-signal according to the mode to which the display sub-signal belongs. For example, line configuration data and line image data obtained by analyzing the display sub-signals provided in the line configuration mode; analyzing the display sub-signals provided by the frame configuration mode to obtain frame configuration data; and a correction signal obtained by analyzing the display sub-signal provided in the correction configuration mode.

For example, the pattern recognition signal is extracted from the display signal. For example, if the pattern recognition signal is "RESET signal RESET + 000", the pattern to which the display sub-signal belongs is the column configuration pattern.

In step S730, for example, if the mode to which the display sub-signal belongs is the line configuration mode, the line configuration data and the line image data are acquired from the display sub-signal according to the signal format of the line configuration mode.

In some embodiments of the present disclosure, each display sub-signal further includes a data signal, and step S710 includes: the method comprises the steps that a plurality of display sub-signals are sequentially received through a low-voltage differential signal interface, and for each display sub-signal, after a mode identification signal is received through the low-voltage differential signal interface, a data signal is received through the low-voltage differential signal interface.

In some embodiments of the present disclosure, receiving, by the low voltage differential signal interface, a display signal provided by the controller in at least two modes within one frame display period further includes: before receiving each display sub-signal, a trigger signal is received to perform at least two modes of transmission operations in response to the trigger signal.

In some embodiments of the present disclosure, the trigger signal comprises at least one trigger sub-signal, and receiving the trigger signal comprises: and receiving the at least one trigger sub-signal in sequence, wherein each trigger sub-signal comprises a set time sequence relation between a data transmission control signal and a data polarity inversion control signal.

Fig. 7B illustrates a flowchart of another signal transmission method according to at least one embodiment of the disclosure. As shown in fig. 7B, the signal transmission method includes steps S701 to S709 and steps S711 to S713. Steps S701 to S709 and steps S711 to S713 may be performed by a source driver, for example.

Step S701: the source driver is powered up.

Step S702: and judging whether the trigger signal PSI is acquired or not. For example, it is determined whether the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transfer control signal LOAD in the same cycle. If the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD, the trigger signal PSI is acquired. If the rising edge of the data polarity inversion control signal POL is earlier than the rising edge of the data transmission control signal LOAD, a non-trigger signal (e.g., the single-mode indication signal described above) is acquired.

If the trigger signal PSI is acquired, executing step S703; if the trigger signal PSI is not acquired, the process jumps to step S711 to execute.

Step S703: and judging whether the display sub-signals comprise reset signals or not. If the display sub-signal does not include the reset signal, the display sub-signal is the display sub-signal provided in the calibration configuration mode. If the display sub-signal comprises a reset signal, whether the display sub-signal is provided in a frame configuration mode or a row configuration mode is continuously judged. That is, if the display sub-signal includes the reset signal, step S704 is executed; if the display sub-signal does not include the reset signal, the process jumps to step S711.

Step S704: it is determined whether the line mode Start signal LPC Start and the frame mode Start signal FPC Start are received. That is, it is determined whether the display sub-signal includes the line mode Start signal LPC Start or the frame mode Start signal FPC Start.

If the line mode Start signal LPC Start is received, go to step S708; if the frame mode Start signal FPC Start is received, step S705 is executed.

Step S705: and continuing to receive the frame configuration data by using the low-voltage differential signal interface.

Step S706: and judging whether the low-power-consumption working state is enabled or not. For example, the source driver enters a low power consumption operating state according to the frame configuration data.

If the frame configuration data enables the low power consumption operating state, executing step S707; if the frame configuration data does not enable the low power consumption operation state, the process returns to step S702.

Step S707: the source driver enters a low power consumption operating state. For example, in the low power consumption operating state, at least part of the circuit blocks of the source driver are powered down, thereby reducing the power consumption of the source driver at least during the vertical blanking period. At least some of the circuit blocks may be configured with frame configuration data.

Step S708: and continuing to receive the row configuration data by using the low-voltage differential signal interface.

Step S709: continuing to receive line image data by using low-voltage differential signal interface

Step S711: a correction signal provided by the controller in the correction configuration mode is received.

Step S712: a reset signal is received.

Step S713: image data is received.

For example, for steps S701 to S709 and step S711, the reset signal and the image data provided by the controller to the source driver conform to the first signal transmission protocol. For steps S712 and S713, for example, the controller provides the reset signal and the image data to the source driver in compliance with the second signal transmission protocol.

The signal transmission method performed by the source driver shown in fig. 7A and fig. 7B corresponds to the signal transmission method performed by the controller shown in fig. 1C, and the signal transmission method performed by the source driver refers to the signal transmission method performed by the controller described above, which is not repeated in this disclosure.

Fig. 8 illustrates a schematic block diagram of a controller 800 provided by at least one embodiment of the present disclosure. The controller 800 serves to transmit a display signal to the source driver.

For example, as shown in fig. 8, the controller 800 includes a display signal acquiring unit 810 and a low voltage differential signal interface 820.

The display signal acquisition unit 810 is configured to acquire a display signal. For example, the display signal acquisition unit 810 generates display signals provided to the source driver in at least two modes.

The display signal acquisition unit 810 may perform, for example, step S10 described in fig. 1C.

The low voltage differential signaling interface 820 is configured to provide the display signal to the source driver in at least two modes within one frame display period, the display signal includes a plurality of display sub-signals, each of the plurality of display sub-signals includes a mode identification signal, and the mode identification signal is used to indicate the mode to which the display sub-signal belongs to the source driver, so that the source driver processes the display sub-signal according to the mode to which the display sub-signal belongs.

The low voltage differential signal interface 820 may, for example, perform step S20 described in fig. 1C.

The controller 800 implements a multi-mode transmission operation between the controller and the source driver through the pattern recognition signal, thereby implementing multiplexing of the low voltage differential signal interface for providing both image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission and ensuring that various control functions can be flexibly embedded in the source driver.

Fig. 9 illustrates a schematic block diagram of a source driver 900 provided in at least one embodiment of the present disclosure. The source driver 900 is used to acquire display signals from the controller.

For example, as shown in fig. 9, the source driver 900 includes a low voltage differential signal interface 910, a mode determination unit 920, and a processing unit 930.

The low voltage differential signaling interface 910 is configured to receive a display signal provided by the controller in at least two modes for a frame display period, wherein the display signal includes a plurality of display sub-signals, and each display sub-signal includes a mode identification signal.

The low voltage differential signal interface 910 may, for example, perform step S710 depicted in fig. 7A.

The mode determining unit 920 is configured to determine, for each display sub-signal, a mode to which the each display sub-signal belongs according to the mode identifying signal.

The mode determination unit 920 may perform, for example, step S720 described in fig. 7A.

The processing unit 930 is configured to process each display sub-signal according to the mode to which the display sub-signal belongs.

The processing unit 930 may, for example, perform step S730 described in fig. 7A.

The source driver 900 recognizes the mode to which the display sub-signal belongs through the mode recognition signal, so that a multi-mode transmission operation can be performed between the controller and the source driver, thereby realizing multiplexing of a low voltage differential signal interface, which is used for providing both image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission, and ensuring that various control functions can be flexibly embedded in the source driver.

For example, the display signal acquiring unit 810, the mode determining unit 920 and the processing unit 930 may be hardware, software, firmware and any feasible combination thereof. For example, the display signal acquiring unit 810, the mode determining unit 920 and the processing unit 930 may be dedicated or general circuits, chips or devices, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the controller 800 and the source driver 900 corresponds to each step of the foregoing signal transmission method, and for specific functions of the controller 800 and the source driver 900, reference may be made to the related description about the signal transmission method, and details are not repeated here. The components and structures of the controller 800 shown in fig. 8 and the source driver 900 shown in fig. 9 are exemplary only and not limiting, and the controller 800 and the source driver 900 may include other components and structures as needed.

Fig. 10 illustrates a schematic block diagram of an electronic device 1000 provided by at least one embodiment of the present disclosure. As shown in fig. 10, the electronic device 1000 includes a controller 1010, a source driver 1020, and a display panel 1030.

The controller 1010 performs the signal transmission method described above in fig. 1C. The source driver 1020, for example, performs the signaling method described above in fig. 7A. The source driver 1020 is connected to the controller 1010 through a low voltage differential signal interface to receive the display signal. The display panel 1030 is, for example, a liquid crystal display panel, and receives a driving signal (i.e., a gray-scale voltage signal) supplied from the source driver 1020 to display an image, the driving signal being generated based on the display signal.

The electronic device 1000 may be various electronic devices with an image display function, including but not limited to a smart phone, a tablet computer, a notebook computer, a display, a television, and the like.

The electronic device realizes a multi-mode transmission operation between the controller and the source driver through the pattern recognition signal, thereby realizing multiplexing of a low voltage differential signal interface, enabling it to be used for providing both image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission, and ensuring that various control functions can be flexibly embedded in the source driver.

Although as mentioned above, there are several points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (20)

1. A signal transmission method for a controller to transmit a display signal to a source driver, the method comprising:

providing the display signal to the source driver through the low voltage differential signal interface in at least two modes during a frame display period, wherein the display signal includes a plurality of display sub-signals,

wherein each of the plurality of display sub-signals comprises a pattern identification signal, and the pattern identification signal is used for indicating the mode of the display sub-signal to the source driver so as to enable the source driver to process the display sub-signal according to the mode of the display sub-signal.

2. The method of claim 1, wherein each display sub-signal further comprises a data signal,

sequentially providing the display signals to the source driver in the at least two modes through the low voltage differential signal interface, including:

sequentially providing the plurality of display sub-signals to the source driver in the at least two modes using the low voltage differential signaling interface,

wherein, for each display sub-signal, after the pattern recognition signal is provided to the source driver through the low voltage differential signal interface, the data signal is provided to the source driver through the low voltage differential signal interface.

3. The method of claim 2, wherein the display signals are sequentially provided to the source driver in the at least two modes over the low voltage differential signaling interface, further comprising:

providing a trigger signal to the source driver to inform the source driver to perform the at least two modes of transmission operation before providing the each display sub-signal to the source driver.

4. The method of claim 3, wherein the trigger signal comprises at least one trigger sub-signal, the providing the trigger signal to the source driver comprising:

and sequentially providing at least one trigger sub-signal to the source driver, wherein each trigger sub-signal comprises a set timing relationship between a data transmission control signal and a data polarity inversion control signal.

5. A signal transmission method for a source driver to receive a display signal from a controller, the source driver including a low voltage differential signal interface, the method comprising:

receiving, by the low voltage differential signal interface, a display signal provided by the controller in at least two modes within one frame display period, wherein the display signal includes a plurality of display sub-signals, and each display sub-signal includes a mode identification signal;

for each display sub-signal, determining a mode to which each display sub-signal belongs according to the mode identification signal; and

and processing each display sub-signal according to the mode of each display sub-signal.

6. The method of claim 5, wherein each display sub-signal further comprises a data signal,

receiving, by the low voltage differential signal interface, a display signal provided by the controller in at least two modes within a frame display period, including:

sequentially receiving the plurality of display sub-signals by using the low voltage differential signal interface,

wherein, for each display sub-signal, after receiving the pattern recognition signal through the low voltage differential signal interface, the data signal is received through the low voltage differential signal interface.

7. The method of claim 6, wherein receiving, via the low voltage differential signaling interface, the display signal that the controller provides for a frame of a display period in at least two modes further comprises:

receiving a trigger signal before receiving each display sub-signal to perform the at least two modes of transmission operation in response to the trigger signal.

8. The method of claim 7, wherein the trigger signal comprises at least one trigger sub-signal, receiving the trigger signal comprising:

and receiving the at least one trigger sub-signal in sequence, wherein each trigger sub-signal comprises a set time sequence relation between a data transmission control signal and a data polarity inversion control signal.

9. The method of claim 4 or 8, wherein the setting a timing relationship between the data transfer control signal and the data polarity inversion control signal comprises:

the first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge is at least partially time coincident with a second transition state of the data transmission control signal after the second transition edge.

10. The method of any of claims 1-8, wherein the at least two transmission modes comprise:

at least two of a row configuration mode, a frame configuration mode and a correction configuration mode,

wherein the row configuration mode provides display sub-signals for configuring the source driver for display of a row of pixels,

the frame configuration mode provides a display sub-signal for configuring the source driver for display of a frame of an image,

the display sub-signals provided by the correction configuration mode are used for correcting the clock signals of the source driver and the timing of the display signals.

11. The method of claim 10, wherein,

the pattern recognition signal of the row configuration pattern includes a reset signal and a row pattern start signal,

the mode identification signal of the frame configuration mode includes the reset signal and a frame mode start signal,

the pattern recognition signal of the correction configuration pattern does not include the reset signal.

12. The method according to claim 10 or 11, wherein the display sub-signal provided by the line configuration mode further comprises line configuration data and line image data,

the line configuration data is used to configure the source driver to process the line image data.

13. The method of claim 12, wherein the line configuration data includes a start of frame indication signal indicating whether the line image data is a first image display line in a frame.

14. The method of claim 13, wherein the row configuration data further comprises: a data polarity inversion control signal and a charge sharing function control signal.

15. A method according to claim 10 or 11, wherein the display sub-signals provided by the frame configuration mode further comprise frame configuration data for configuring the source driver for display of a frame of an image.

16. The method of claim 15, wherein the frame configuration mode comprises a power consumption control sub-mode,

the power consumption control sub-mode is used for providing a processing signal of the source driver at least in a vertical blanking period.

17. The method according to claim 10 or 11, wherein the sub-signals provided by the correction configuration mode comprise correction signals for correcting the timing of the clock signals of the source drivers and the display signals.

18. A controller for transmitting display signals to a source driver, the controller comprising:

a low voltage differential signal interface configured to provide the display signals to the source driver in the at least two modes during a frame display period, wherein the display signals include a plurality of display sub-signals,

wherein each of the plurality of display sub-signals comprises a pattern identification signal, and the pattern identification signal is used for indicating the mode of the display sub-signal to the source driver so as to enable the source driver to process the display sub-signal according to the mode of the display sub-signal.

19. A source driver for acquiring display signals from a controller, the source driver comprising:

a low voltage differential signal interface configured to receive a display signal provided by the controller in at least two modes within a frame display period, wherein the display signal includes a plurality of display sub-signals, and each display sub-signal includes a mode identification signal;

the mode determining unit is configured to determine a mode to which each display sub-signal belongs according to the mode identification signal aiming at each display sub-signal; and

and the processing unit is configured to process each display sub-signal according to the mode of each display sub-signal.

20. An electronic device, comprising:

the controller of claim 18;

the source driver of claim 19, the source driver connected with the controller through the low voltage differential signal interface to receive the display signal; and

a display panel connected with the source driver to receive a driving signal provided by the source driver, wherein the driving signal is generated based on the display signal.

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