CN115798385A - Signal transmission method and device and electronic equipment - Google Patents

Abstract

The disclosure relates to a signal transmission method, a signal transmission device and an electronic device. The signal transmission method is used for transmitting a display signal to a source driver based on a clock signal, and comprises the following steps: providing a reset signal to a source driver; providing a first start signal to the source driver after providing the reset signal to the source driver, the first start signal including a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal; and providing the display signal to the source driver after the first start signal ends, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal. The method is beneficial to improving the frequency of signal transmission between the controller and the source driver.

Description

Signal transmission method and device and electronic equipment

Technical Field

The embodiment of the disclosure relates to a signal transmission method, a signal transmission device and electronic equipment.

Background

In the field of display technology, for example, a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines arranged to cross the gate lines. A timing controller (T-con) of the display panel needs to supply gate signals and data signals to a plurality of rows of gate lines and a plurality of columns of data lines through a gate driving circuit and a source driving circuit, respectively, so as to form gray voltages required for each gray scale required for displaying an image in pixel units of each row in a line-by-line scanning manner, for example, and further display an image of one frame.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal, the method including: providing a reset signal to the source driver; providing a first start signal to the source driver after providing the reset signal to the source driver, wherein the first start signal comprises a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal; and providing the display signal to the source driver after the first start signal ends, at least one additional trigger signal determined by the controller based on a clock frequency of the clock signal.

An embodiment of the present disclosure provides another signal transmission method for a source driver to receive a display signal provided by a controller based on a clock signal, the method including: acquiring a reset signal provided by the controller; and in response to receiving a first start signal provided by the controller after the reset signal is derived; receiving the display signal provided by the controller after the first start signal is ended, wherein the first start signal comprises a basic trigger signal and at least one additional trigger signal which is continuous after the basic trigger signal and is determined by the controller based on the clock frequency of the clock signal adopted by the display signal.

At least one embodiment of the present disclosure provides a signal transmission apparatus for a controller to transmit a display signal to a source driver based on a clock signal, the apparatus including: a signal providing unit configured to provide a reset signal to the source driver, provide a first start signal to the source driver after providing the reset signal to the source driver, the first start signal including a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal, and provide the display signal to the source driver after the first start signal ends, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

At least one embodiment of the present disclosure provides a signal transmission apparatus for a source driver to receive a display signal provided by a controller based on a clock signal, the apparatus including: a signal obtaining unit configured to obtain a reset signal provided by the controller, and in response to receiving a first start signal provided by the controller after obtaining the reset signal, receive the display signal provided by the controller after the first start signal ends, the first start signal including a base trigger signal and at least one additional trigger signal that is continuous after the base trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

At least one embodiment of the present disclosure provides an electronic device including a signal transmission apparatus provided in at least one embodiment of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel;

FIG. 1B shows a system architecture diagram of the timing controller TCON and source driver connections;

fig. 1C shows a timing diagram of signal transmission by the timing controller TCON and the source driver;

fig. 2 illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure;

fig. 3 illustrates a timing diagram of signal transmission by the timing controller TCON and the source driver according to at least one embodiment of the present disclosure;

fig. 4 illustrates another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 5A and 5B are schematic diagrams illustrating a signal format of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

fig. 6A illustrates a timing diagram of a mode trigger signal PSI according to at least one embodiment of the present disclosure;

fig. 6B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure;

fig. 7 is a flow chart illustrating another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 8 illustrates a schematic block diagram of a signal transmission apparatus provided in at least one embodiment of the present disclosure;

fig. 9 illustrates a schematic block diagram of another signal transmission apparatus provided in at least one embodiment of the present disclosure; and

fig. 10 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Various driving circuits for the display panel generally include a scan driving integrated circuit (also referred to as a gate driver or a G-IC), a data driving integrated circuit (also referred to as a source driver or an SD-IC), a controller, and the like. The controller is mainly used to convert image data signals, control signals, clock signals, and the like received from the outside (e.g., a signal source such as a storage device, a network modem, and the like) into image data signals, gate signals, control signals, clock signals, and the like suitable for a source driver and a gate driver, so as to implement image display driving of the display panel. For example, the Controller may be a Timing Controller (TCON). The source driver is mainly used for receiving the digital signals (display signals or image signals) and control signals and the like provided by the controller, converting the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and inputting the analog gray scale voltage signals into each row of pixel units of a pixel array of the display panel. The gate driver is mainly used for enabling pixel units of each row of the pixel array to be started up line by line (or interlaced), for example, and is matched with the source driver under the action of the control signal, and a required image data signal is input into the corresponding pixel unit for the started pixel unit row, so that the pixel unit can display according to the image data signal.

In the display process of the display panel, the video and the animation are formed by combining a plurality of pictures which are sequentially displayed according to time sequence (for example, the frame rate is 60Hz or 120Hz, and the like), each picture is a frame, namely, one frame of image refers to a complete picture displayed by the display panel. During the display of one frame of image, the gate driver turns on each row of pixel units in the pixel array in turn from the first row to the last row for scanning, and during the scanning, the source driver inputs image data signals required by each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required by one frame of picture. For example, due to the process of the pixel units of the display panel, the display screen needs to be continuously refreshed to obtain a clear and complete display effect with good quality, each time the display screen needs to display one frame of image, and the multiple frames of continuously displayed images form a static screen or a dynamic screen in visual effect. When the gate driver finishes scanning one frame of image, it is necessary to go back to the first row to start scanning a new frame. The period from the end of scanning the last line by the gate driver to the return to the first line is a vertical blank period. Preparation is made for display of the next frame image during the vertical blank period during which the display panel does not display an image.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel. As shown in FIG. 1A, the circuit driving system architecture includes a timing controller TCON, a gate driver G-IC, a source driver SD-IC, and a display panel. The circuit driving system architecture further includes a power management integrated circuit PMIC, a Gamma (Gamma) circuit, a common electrode voltage (Vcom) circuit, and the like.

The input terminal voltage Vin of the power management integrated circuit is, for example, 5V or 12V, and the output voltages include a digital operating voltage DVDD supplied to each IC, an analog voltage AVDD supplied to the Gamma circuit and the Vcom circuit, a gate-on voltage VGH supplied to the gate driver G-IC, a gate-off voltage VGL, and the like. A common electrode voltage (Vcom) circuit is used to supply a common voltage to the pixel array.

The control signals output from the timing controller TCON include control signals supplied to the gate driver G-IC and control signals supplied to the source driver SD-IC. For example, the control signals supplied to the source driver SD-IC include a Start Horizontal (STH) signal at which data transmission starts, a line Clock (CPH) signal, a data transmission control signal Load, and a data polarity inversion signal POL. For example, the control signals supplied to the gate driver G-IC include a frame Start Signal (STV) representing scan on of one frame, a scan Clock signal (CPV), an Enable signal (Enable), and the like.

For example, the input digital interface type of the timing controller TCON may be, for example, a Low-Voltage Differential Signaling (LVDS), an Embedded Display signal (eDP) interface, a V-by-One (Vx 1) interface, and the like. The type of digital interface at the output of the timing controller TCON may be mini-LVDS, for example, for communication with the source driver SD-IC.

The LVDS interface transmits signals in a line pair form including one clock line pair and several signal line pairs. For example, the LVDS signal line pair includes three control signals: a field sync signal, a line sync signal, and an enable signal. The mini-LVDS interface is similar to the LVDS interface, and signals are transmitted by a differential signal line pair; unlike the LVDS signal line pair, the signal transmitted by the mini-LVDS signal line pair of the mini-LVDS interface does not contain control signals, which are transmitted through a signal line or a signal differential pair independent of the mini-LVDS signal line pair.

Embodiments are illustrated in this disclosure by taking the example where the source driver and controller communicate over a mini-LVDS interface.

Fig. 1B shows a system architecture diagram of the connection of the timing controller TCON and the source driver.

As shown in fig. 1B, the system architecture includes a timing controller TCON and a plurality of source drivers. The plurality of source drivers include, for example, a source driver SD #1, a source driver SD #2, and the like, and the number of source drivers is related to the physical resolution of the display panel, and may need tens or even hundreds for one display panel. For example, each source driver is connected through a clock signal line pair for transmitting a clock signal, a mini-LVDS signal line pair for transmitting an image data signal, and a control signal line for transmitting a plurality of control signals. The mini-LVDS signal line pair may be 3 pairs of signal lines or 6 pairs of signal lines. The control signal lines may or may not be differential signal pairs. The mini-LVDS signal line and the plurality of control signal lines are independent of each other.

For example, the timing controller TCON and each of the source drivers (e.g., the source driver SD #1, SD #2 … …) are connected through a LOAD control signal line transmitting a data transmission control signal LOAD, a POL control signal line transmitting a control signal POL, a POL2 control signal line transmitting a control signal POL2, and the like, in addition to being connected through a mini-LVDS signal line pair.

Other control signal lines, such as a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, a POLC control signal line, etc., may also be included between each source driver and the TCON.

Fig. 1C shows a timing diagram of signal transmission by the timing controller TCON and the source driver.

As shown in fig. 1C, the clock signal CLK and the data signal LV0 are included in this timing. The clock signal CLK is, for example, a signal transmitted on the clock signal line pair CLK in fig. 1B. The mini-LVDS signal line pair in fig. 1B includes, for example, 3 pairs of signal lines, and the data signal LV0 may be a signal transmitted on a low voltage differential signal line pair LV0 of the 3 pairs of signal lines. The low-voltage differential signal line pair LV0 is any one of the 3 pairs of signal lines.

In this embodiment the signal line and the signal transmitted by the signal line are indicated by the same reference numeral. For example, the clock signal and the clock signal line pair are both represented by CLK.

As shown in fig. 1C, before one frame image is displayed, the controller supplies a reset signal re to each source driver, so that the source driver is reset.

In the example of fig. 1C, the reset signal is, for example, a digital signal "1". In the embodiment of the present disclosure, for example, a high level signal represents a digital signal "1", and a low level signal represents a digital signal "0".

For example, the controller provides the reset signal re to the source driver for a plurality of consecutive clock cycles of the clock signal. After the reset signal re is supplied, the controller supplies a start signal st to the source driver according to a reset active edge P of the clock signal. The reset active edge P is the first active edge following the last active edge Q of the clock signal in the plurality of consecutive clock cycles described above. The start signal st is, for example, a digital signal "0" to indicate that the source driver is ready to receive a subsequent display signal. The display signal is used for displaying one frame of image and may include, for example, a control signal and an image data signal.

For example, the source driver starts performing operations such as reset and configuration in response to a high signal being acquired at a plurality of active edges of the clock signal and a low signal being acquired at a reset active edge.

The timing relationship between the reset signal re and the start signal st and the clock signal CLK satisfies the setup time and the hold time, respectively.

As shown in fig. 1C, after the controller supplies the start signal st to the source driver, the controller starts to supply the display signal to the source driver, and makes the clock signal CLK and the data signal LV0 satisfy the setup time and the hold time. For example, the source driver collects the signals transmitted on the low voltage differential signal line pair LV0 at and after the active edge M of the clock signal, which is the first active edge of the clock signal after the reset active edge P, to obtain the display signal.

In this example, the source driver performs operations such as resetting and configuring in preparation for subsequent receipt of the display signal, for example, within a time period tStart between a reset active edge P and a display signal active edge M.

If the frequency of the clock signal is high, it is difficult for the source driver to completely perform the operations of resetting, configuring, etc. within the time period tStart between the reset active edge P and the display signal active edge M, and to sufficiently prepare for subsequently receiving the display signal, affecting the transmission of the subsequent display signal. If the frequency of the clock signal is low, the signal transmission efficiency between the source driver and the controller is low, and the display panel has a poor effect of displaying images.

In the above embodiments, the active edge of the clock signal is, for example, the rising edge of the clock signal. For example, the reset active edge P and the display signal active edge M are both rising edges of the clock signal. In other embodiments of the present disclosure, the active edge of the clock signal is, for example, a falling edge of the clock signal. In the following description, the embodiments provided by the present disclosure are described only by taking an effective edge of a clock signal as an example, for example, a rising edge of the clock signal.

Note that the reset signal may be another type of signal, and the start signal is a signal different from the reset signal. The present disclosure does not limit the reset signal to be a high level signal and the start signal to be a low level signal. For example, the reset signal is a low level signal and the start signal is a high level signal. In the following description, the embodiments provided in the present disclosure are described by taking only the reset signal as a high level signal and the start signal as a low level signal as an example.

To this end, an embodiment of the present disclosure provides a signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal, the method including: providing a reset signal to a source driver; providing a first start signal to the source driver after providing the reset signal to the source driver, the first start signal including a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal; and providing the display signal to the source driver after the first start signal ends, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal. The method is beneficial to improving the frequency of signal transmission between the controller and the source driver, and the source driver has enough time to execute operations such as resetting and configuration and the like so as to make full preparation for the transmission of the display signal.

Fig. 2 shows a flow chart of a signal transmission method according to at least one embodiment of the present disclosure. For example, the signal transmission method provided by the embodiment of the disclosure is suitable for both an LVDS interface and a mini-LVDS interface.

As shown in fig. 2, the signal transmission method includes steps S10 to S30. This embodiment is for the controller to transmit a display signal to the source driver based on the clock signal. The signal transmission method illustrated in fig. 2 is performed by the timing controller TCON in fig. 1B, for example. For example, the signal transfer method is used for the timing controller TCON to transfer the display signal to the source driver SD #1, the source driver SD #2, and the like based on the clock signal.

Step S10: a reset signal is provided to the source driver.

Step S20: after providing the reset signal to the source driver, a first start signal is provided to the source driver, the first start signal including a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal.

Step S30: after the first start signal ends, a display signal is supplied to the source driver.

In an embodiment of the disclosure, the at least one additional trigger signal is determined by the controller based on a clock frequency of the clock signal.

In this embodiment, by increasing the time length of the start signal (i.e., the first start signal) by at least one additional trigger signal, the source driver can sufficiently perform operations such as reset and configuration even if the frequency of the clock signal is increased, so that the frequency of signal transmission by the controller and the source driver can be increased.

In some embodiments of the present disclosure, the display signal provided by the controller to the source driver may comprise only an image data signal, i.e., only the image data signal is transmitted by the mini-LVDS signal line pair, for example.

In an example where the display signal includes only the image data signal, the control signal is transmitted through various control signal lines described in fig. 1B. As shown in fig. 1B, the mini-LVDS signal line pair is used only for transmitting image data signals and is not used for transmitting control signals such as polarity inversion configuration information, data transmission control information, and the like. Therefore, there are a plurality of signal lines and a plurality of signal line interfaces between the timing controller and the source drivers, which results in occupying a large signal routing space in the display panel, and this problem is more pronounced particularly when the number of source drivers is large. Some commonly used control functions cannot be flexibly embedded in the source driver if the available signal routing space in the display panel is not sufficient to accommodate the plurality of data lines.

In other embodiments of the present disclosure, the display signal includes both the image data signal and the configuration data signal. That is, the mini-LVDS signal line pair transmits both the image data signal and the configuration data signal.

In this example, the timing controller TCON and the source driver may be connected only through the mini-LVDS signal line pair, the clock signal line pair, the LOAD control signal line, and the POL control signal line. In this embodiment, the mini-LVDS transmits, in addition to the image data signal, a configuration data signal that controls the source driver, such as the above-described control signal POL2, the horizontal dot inversion control signal, the bias voltage control signal, and the like. This enables multiplexing of low voltage differential signal interfaces for both providing image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission, saving cost, and ensuring that multiple control functions can be flexibly embedded in the source driver. The image data signal is a signal for image display, and includes, for example, RGB (red, green, and blue) data. The configuration data is used to configure the source driver.

For example, in addition to the data transmission control signal LOAD being transmitted through the LOAD control signal line and the control signal POL being transmitted through the POL control signal line, other control signals are also transmitted through the mini-LVDS signal line pair. That is, the configuration data signal includes other control signals, such as a horizontal dot inversion control signal, a bias voltage control signal, a POLC control signal, etc., in addition to the data transfer control signal LOAD and the control signal POL.

The signal transmission method described in fig. 2 is explained below with reference to fig. 3.

Fig. 3 illustrates a timing diagram of signal transmission by the timing controller TCON and the source driver according to at least one embodiment of the present disclosure.

As shown in fig. 3, the clock signal CLK 'and the data signal LV0' are included in this timing. The clock signal CLK' is, for example, a signal transmitted on the clock signal line pair CLK in fig. 1B. The mini-LVDS signal line pair in fig. 1B includes, for example, 3 pairs of signal lines, and the data signal LV0' may be a signal transmitted on a low voltage differential signal line pair LV0 of the 3 pairs of signal lines, and the low voltage differential signal line pair is any one of the 3 pairs of signal lines.

The frequency of the clock signal CLK' is, for example, greater than the frequency of the clock signal CLK in fig. 1C.

As shown in fig. 3, for example, with respect to step S10, before one frame image display, the controller first supplies a reset signal re' to each source driver so that the source driver is reset.

In the example of fig. 3, the reset signal re' is, for example, the same as the reset signal re in fig. 1C, for example, a digital signal "1". Alternatively, the reset signal re' may be different from the reset signal re in fig. 1C.

For example, the controller provides a reset signal re' to the source driver for a plurality of consecutive clock cycles of the clock signal. For step S20, the controller provides the start signal st 'to the source driver, for example, after providing the reset signal re'. The start signal st' is an example of a first start signal. The start signal st' includes a base trigger signal BT and AT least one additional trigger signal AT that follows the base trigger signal.

In some embodiments of the present disclosure, the base trigger signal BT and each additional trigger signal AT are both digital signals "0", for example.

The base trigger signal BT and each additional trigger signal AT are determined by the controller based on the clock frequency of the clock signal.

For example, the setup and hold times of the clock signal CLK 'and the data signal LV0' in each clock cycle determine the base trigger signal BT and each additional trigger signal AT, so that the source controller can accurately and stably acquire the base trigger signal BT and each additional trigger signal AT the active edge of the clock signal.

In some embodiments of the present disclosure, at least two consecutive rising edges of the clock signal CLK' correspond to the base trigger signal and the at least one additional trigger signal, respectively.

The source driver acquires the base trigger signal BT provided by the controller at a first active edge P1 (i.e., a reset active edge) following a last active edge Q' of the clock signal in a plurality of consecutive clock cycles (clock cycles providing the reset signal), and acquires at least one additional trigger signal provided by the controller at an active edge (e.g., active edge P2) of at least one clock signal following the first active edge P1 in a series. Each additional trigger signal is respectively acquired at the active edge of the clock signal after the first active edge P1.

As shown in fig. 3, after the controller supplies the start signal st ' to the source driver, the controller starts to supply the display signal to the source driver such that the clock signal CLK ' and the data signal LV0' satisfy the setup time and the hold time. For example, the source driver acquires signals transmitted on the low-voltage differential signal line pair LV0 at the display signal effective edge M 'and the following effective edge of the clock signal to obtain the display signal, where the display signal effective edge M' is the first effective edge after the last effective edge of the clock signal corresponding to the start signal, that is, the first effective edge after the effective edge corresponding to the last additional trigger signal. In the example of fig. 3, the last additional trigger signal corresponds to an active edge, for example, active edge P2.

In this embodiment, the source driver performs reset and configuration operations, etc., in preparation for subsequent receipt of the display signal, during a time period tStart ' between the first active edge P1 following the active edge Q ' of the clock signal and the display signal active edge M '.

In the example of fig. 3, only one additional trigger signal is shown, but in practical applications, the number of additional trigger signals may be set according to practical requirements.

In some embodiments of the present disclosure, the number of the at least one additional trigger signal may be determined according to a frequency of the clock signal and a length of time required for the source driver to perform the resetting and configuring.

For example, the longer the length of time required for the source driver to perform reset and configuration, the greater the number of additional trigger signals.

In the example of fig. 3, since the frequency of the clock signal CLK' is greater than the frequency of the clock signal CLK, if the start signal and the display signal are still supplied to the source driver at the timing shown in fig. 1C, the source driver does not have enough time to perform the operations of reset and configuration, etc. In the embodiment shown in fig. 3, the length of time between the active edge from the reset and the active edge of the display signal is extended by the additional trigger signal, and the additional trigger signal and the base trigger signal may be the same, which does not require the controller and the source driver to perform additional operations, and is simple and easy to implement.

In some embodiments of the present disclosure, the signal transmission method further comprises obtaining a reset format, the reset format comprising a first format and a second format. Step S20 includes supplying a first start signal to the source driver after supplying the reset signal to the source driver in response to the reset format being the first format.

For example, the reset format may be set by those skilled in the art according to actual requirements. The first format corresponds to providing a first start signal to the source driver, and the second format corresponds to providing a second start signal to the source driver, the second start signal being different from the first start signal.

For example, if the reset format is the first format, a first start signal is supplied to the source driver after the reset signal is supplied to the source driver; if the reset format is the second format, a second start signal is provided to the source driver after the reset signal is provided to the source driver.

For example, the first start signal is the start signal st' shown in fig. 3, and the second start signal is the start signal st shown in fig. 1C. That is, the first start signal includes the base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal, and the second start signal includes only the base trigger signal.

It should be noted that, although fig. 1C and fig. 3 each take the display signal as the digital signal "0" as an example, this does not limit the disclosure, and the display signal may be any signal.

Fig. 4 illustrates another signal transmission method provided by at least one embodiment of the present disclosure.

As shown in fig. 4, the signal transmission method includes steps S401 to S405.

Step S401: a reset format is obtained. The reset format includes a first format and a second format.

Step S402: in response to the reset format being the first format, a first start signal is provided to the source driver after the reset signal is provided to the source driver.

Step S403: after the first start signal ends, a display signal is supplied to the source driver.

Step S404: in response to the reset format being the second format, after providing the reset signal to the source driver, providing a second start signal to the source driver, the second start signal including only the base trigger signal.

Step S405: after the second start signal ends, a display signal is provided to the source driver.

The method can provide a first start signal or a second start signal to the source driver based on a preset reset format (a first format or a second format) according to different clock frequencies, wherein the first start signal or the second start signal respectively corresponds to different clock frequencies, so that the method is suitable for signal transmission at different clock frequencies.

For step S401, in some embodiments of the present disclosure, for example, a clock frequency is obtained, and a reset format is obtained according to the clock frequency.

For example, the reset format is determined to be the first format in response to the clock frequency being greater than a preset frequency, or the reset format is determined to be the second format in response to the clock frequency being less than or equal to the preset frequency.

For example, the predetermined frequency is 330Mhz, and if the clock frequency is greater than 330Mhz, the reset format is the first format; if the clock frequency is less than or equal to 330Mhz, the reset format is the second format.

The preset frequency can be set by those skilled in the art according to actual needs, and the preset frequency is not limited by the disclosure. For example, the preset frequency may be 48 Mhz.

In other embodiments of the present disclosure, the reset format may be preset or re-updated by one skilled in the art.

For the reset format, refer to the above description.

For steps S402 and S403, for example, if the reset format is the first format, after the reset signal is supplied to the source driver, the start signal st' shown in fig. 3 is supplied to the source driver. After the start signal st' ends, a display signal is supplied to the source driver. The timing relationship between the timing signal and the data signal in the embodiments of step S402 and step S403 is, for example, the example shown in fig. 3.

As shown in fig. 4, the signal transmission method includes steps S404 and S405 in addition to steps S401 to S403.

For step S404, the second start signal may be the start signal st shown in fig. 1C, for example. The start signal st includes only the basic trigger signal. That is, there is only one reset active edge P between the active edge M of the display signal and the last active edge Q of the clock signal in a number of consecutive clock cycles.

For step S405, as shown in fig. 1C, after the start signal st ends, a display signal is supplied to the source driver.

The timing relationship between the timing signal and the data signal in the embodiments of step S404 and step S405 is, for example, the example shown in fig. 1C.

In the above embodiment, a suitable reset format may be selected according to different clock frequencies, so that the signal transmission method may adopt different reset formats for different clock frequencies, and the method has stronger applicability, and is beneficial to improving the frequency of signal transmission performed by the controller and the source driver.

In some embodiments of the present disclosure, for example, the controller sequentially provides the reset signal, the first start signal, and the display signal to the source driver through the low voltage differential signal interface.

In at least one embodiment of the present disclosure, the low voltage differential signaling interface includes a plurality of pairs of transmission lines, each pair of transmission lines including two complementary differential signals through which image data and configuration data are transmitted. For example, the low voltage differential signal interface may be a mini-LVDS interface, an LVDS interface, or the like.

As described above, in some embodiments the display signal includes only the image data signal, and the control signal for display is transmitted through the control signal line.

In still other embodiments of the present disclosure, there is provided a signal transmission method in which the display signal includes a configuration data signal in addition to the image data signal.

For example, the controller provides display signals to the source driver in at least two modes, the display signals including an image data signal and a configuration data signal.

For example, the configuration data signal may be generated by a timing control block in the timing controller. The configuration data signal is used to configure the source driver such that the source driver processes the image data signal according to the configuration data signal. For example, the source driver outputs image data signals to the pixel array according to the timing provided by the configuration data signals.

In some embodiments of the present disclosure, the configuration data signals include control signals required in the process of displaying the RGB data by the pixel array. For example, if the display panel is a liquid crystal display panel and the liquid crystal display panel needs to control the polarity of liquid crystal molecules during the RGB data display process, the control signal may include a data polarity inversion control signal (e.g., a POL control signal, a POL2 control signal, and a POLC control signal). For another example, a start signal of line data is required in the process of displaying RGB data by the pixel array, and the control signal may include a start signal STH of line data. For another example, in the embodiments of the present disclosure, the display panel may also be an OLED display panel or the like, and the embodiments of the present disclosure are not limited thereto.

For example, the configuration data signal may be set by those skilled in the art according to actual needs, and the present disclosure does not limit the configuration data, and the data polarity inversion control signal, the frame scanning start signal, and the start signal of the line data are merely examples.

The one-Frame display Period includes, for example, an image display Period (Active Frame) and a Vertical Blanking Period (VBP). During image display, for example, pixels in the pixel array display image data line by line, and during the vertical blanking interval, preparation is made for display of the next frame of image data.

For example, the display signal comprises a plurality of display sub-signals, at least one display sub-signal being provided for each of the at least two modes. The at least two modes include a frame configuration mode in which the display sub-signal includes frame configuration data for display of a frame of an image, the frame configuration data including a power consumption flag signal.

In some embodiments of the disclosure, the at least two modes further include a line configuration mode in addition to the frame configuration mode, the configuration data includes line configuration data, and the display sub-signal provided by the line configuration mode includes the line configuration data and line image data.

The row configuration mode provides display sub-signals for the display of image data for a row of pixels. The line image data is, for example, RGB data corresponding to the line in the pixel array. The row configuration data is used to configure the source driver so that the source driver outputs the row image data and timing control signals, etc. to the row of pixels in response to the row configuration data.

In some embodiments of the disclosure, the at least two modes further include a correction configuration mode, and the correction configuration mode provides the display sub-signal including a timing relationship for correcting the clock signal and the data signal.

Fig. 5A and 5B are schematic signal formats of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure.

As shown in fig. 5A, in one frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 501 supplied in a line configuration mode, a display sub-signal 502 supplied in a frame configuration mode, and a display sub-signal 503 supplied in a correction configuration mode.

For example, the plurality of display sub-signals 501 are provided in a line configuration mode during image display, the display sub-signals 502 are provided in a frame configuration mode during vertical blanking and the display sub-signals 503 are provided in a correction configuration mode.

As shown in fig. 5A, providing display signals to the source driver in at least two modes through the low voltage differential signal interface during one frame display period includes: and sequentially providing the display signals to the source driver in at least two modes by using the low voltage differential signal interface during one frame display period, and sequentially providing one or more display sub-signals to the source driver by using the low voltage differential signal interface for each mode.

For example, in the example of fig. 5A, the low voltage differential signaling interface is utilized to provide a plurality of display sub-signals 501 to the source drivers in a row configuration mode, then provide the display sub-signals 502 to the source drivers in a frame configuration mode, and then provide the display sub-signals 503 to the source drivers in a correction configuration mode. For example, for a row configuration mode comprising a plurality of display sub-signals 501, the plurality of display sub-signals 501 are provided to the source driver in sequence using a low voltage differential signaling interface. That is, in the example of fig. 5A, the plurality of display sub-signals 501 are provided to the source driver by using the low voltage differential signal interface, the display sub-signals 502 are provided to the source driver by using the low voltage differential signal interface, and the display sub-signals 503 are provided to the source driver by using the low voltage differential signal interface.

As shown in fig. 5A, each display sub-signal 501 provided in the line arrangement mode includes line data LPC and image data (e.g., RGB data). As shown in fig. 5B, the line data LPC includes a pattern recognition signal a and line configuration data. For example, the mode identification signal a includes a reset signal RE and a line mode Start signal LPC Start. For example, the row mode start signal may be a logic inactive level, e.g., "000 000", and thus the display signals shown in fig. 1C and 3 are both row mode start signals.

In some embodiments of the present disclosure, the row configuration data may be, for example, a row data packet including 16 bits, for example, the row data packet includes a 0 th bit data LPC [0], a 1 st bit data LPC [1], and a 15 th bit data LPC [15].

Table one below illustrates an exemplary definition of a row data packet provided by at least one embodiment of the present disclosure.

Watch 1

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a start of frame indication signal. For example, bit 0 LPC [0] of a row of data packets is a start of frame indicator. In the row configuration data of the first display row of each frame, LPC [0] is, for example, high level.

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a data polarity inversion control signal. For example, the 1 st bit LPC [1] of the row data packet is the data polarity inversion control signal POL; the 2 nd bit LPC 2 of the line data packet is a data polarity reversal control signal POLC; the 3 rd bit LPC [3] of the row data packet is the data polarity inversion control signal POL2.

As shown in table one, in a row configuration data provided by the present disclosure, the row configuration data includes a charge sharing function control signal. For example, bits 4 through 7 of the row data packet, i.e., LPC [4:7], are charge-sharing control bits used to control charge sharing.

As shown in table one, in a row configuration data provided in the present disclosure, a reserved bit is further included for flexibly adding some row configurations, so as to improve configuration flexibility. For example, bits 8 to 15, i.e., LPC [ 8.

It should be noted that table one is merely an example of a row packet definition, and has no limiting effect on the embodiments of the present disclosure. Other definitions of a row of data packets may be devised by those skilled in the art. For example, the row data packet may be 8 bits, 32 bits, 64 bits, etc.

As shown in fig. 5A, each display sub-signal 502 provided in the frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The invalid data IDLE0 and the invalid data IDLE1 may be the same signal, for example, a low level signal, and the distinction is made here because the data lengths of the IDLE0 and the IDLE1 are different. In the embodiment of the present disclosure, for example, the invalid data may be a low-level signal, or may be a signal of another form.

The controller is providing a logic inactive level to the source driver during the low power consumption operating state to reduce power consumption during vertical blanking. As shown in fig. 5B, the frame data FPC includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the frame data FPC is a reset signal RE and a frame pattern Start signal FPC Start. For example, the frame mode start signal may be different from the row mode start signal, e.g., a logic active level such as "111", to distinguish between the frame configuration mode and the row configuration mode.

Table two below illustrates an exemplary definition of a frame data packet provided by at least one embodiment of the present disclosure.

Watch 2

As shown in table two, the frame data packet includes 28 bits. The 0 th bit of the frame configuration data FPC [0] is a vertical blanking state bit. For example, if the 0 th bit data FPC [0] of the frame configuration data is 1 (i.e., high), the source driver enables a low power consumption operation state.

FPC [ 1. FPC [26 ] of frame configuration data is low power consumption configuration information defining a circuit block in which a power supply block is turned off during vertical blanking. For example, if FPC [26 ] =00, the receiver is powered down, i.e., the power supply of the receiver in the source driver is turned off. If FPC [26 ] =01, the receiver and the outputter are powered down, i.e., the power supplies of the receiver and the outputter in the source driver are simultaneously turned off.

In some embodiments of the present disclosure, during the transmission operation performed in the frame configuration mode, a mode trigger signal is provided to the source driver, so that the source driver starts to enter a low power consumption operation state in response to the mode trigger signal.

In some embodiments of the present disclosure, the display sub-signal provided in the frame configuration mode includes the data signal 512 provided in the power consumption control sub-mode.

The data signal provided in the power consumption control sub mode may include, for example, invalid data IDLE0 and invalid data IDLE1.

As shown in fig. 5A, before the invalid data IDLE0 is supplied to the source driver in the power consumption configuration sub-mode, the controller supplies the mode trigger signal PSI to the source driver again to instruct the source driver to enter the low power consumption operation state.

During the period that the controller provides the invalid data IDLE0 and the invalid data IDLE1 to the source driver in the power consumption configuration sub-mode, at least part of the circuit modules in the source driver are in a power-down state to save power consumption.

As shown in fig. 5A, each display sub-signal 503 provided in the correction configuration mode includes correction data ASC. As shown in fig. 5B, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C may be, for example, a logic inactive level. The correction signal is used, for example, to correct the timing of the clock signal and the data signal transmitted on the low-voltage differential signal line pair. The pattern recognition signal C does not include a reset signal, and thus the timing of the display sub-signals provided in the correction configuration mode may be different from the timing relationship shown in fig. 3.

As shown in fig. 5A, after the display signal for one frame display period is transmitted to the source driver, the transmission of the display signal for the next frame display period to the source driver is continued.

As shown in fig. 5A, before each display sub-signal is supplied to the source driver, a mode trigger signal PSI is supplied to the source driver, the mode trigger signal PSI being used to inform the source driver whether to perform a transfer operation for at least two modes or a single-mode transfer operation. The single mode transmission operation is, for example, the above-described embodiment in which the display signal transmitted by using the low voltage differential signaling interface such as mini-LVDS includes only the image data signal, and the control signal is transmitted through the control signal line.

In this embodiment, the mode trigger signal PSI informs the source driver of the at least two modes of transmission operations performed, which facilitates the source driver and the controller to be compatible with other transmission operations besides the at least two modes of transmission operations, providing compatibility. For example, a single mode transfer operation may be compatibly performed between the controller and the source driver in addition to the transfer operation through at least two modes. For example, the display signals that may be transmitted in at least two modes conform to a first signaling protocol, and the display signals that may also be transmitted to the source driver in a single mode conform to a second signaling protocol. If the controller and the source driver execute the transmission operation of at least two modes, the controller firstly provides a mode trigger signal PSI to the source driver as an indication signal of the transmission operation of at least two modes; if the controller and the source driver execute the single-mode transmission operation, the controller firstly provides a single-mode indication signal different from the mode trigger signal PSI to the source driver. The second signal transfer protocol may be some different protocol than the first signal transfer protocol, such as some transfer protocols in the related art. The signal line multiplexing can be realized by setting the mode trigger signal, so that the chip has multiple functions, and the difficulty of popularization of the first signal transmission protocol is reduced.

In some embodiments of the present disclosure, providing the mode trigger signal to the source driver comprises: the data transfer control signal and the data polarity inversion control signal are provided to the source driver, and the mode trigger signal is obtained based on a relative timing relationship between the data transfer control signal and the data polarity inversion control signal provided by the source driver. The first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge is at least partially time coincident with a second transition state of the data transmission control signal after the second transition edge.

For example, the data polarity inversion control signal controls the polarity inversion of the data signal output by the source driver by switching between high and low levels to realize the ac driving of the liquid crystal. The data transfer control signal is used to latch data and a data polarity inversion signal input to the source driver at a rising edge, and the falling edge controls the release of the data to the panel.

In this example, the controller and the source driver may be connected through a mini-LVDS signal line, a POL signal line, and a LOAD signal line, and thus other lines such as a POL2 control signal line and a POLC control signal line, a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, and the like may be omitted entirely or partially. Therefore, this example can not only reduce the number of signal lines between the controller and the source driver, but also inform the source driver which kind of transfer operation is performed to be compatible with the transfer operation of the single mode.

Fig. 6A illustrates a timing diagram of a mode trigger signal PSI according to at least one embodiment of the present disclosure.

As shown in fig. 6A, the mode trigger signal PSI includes a data transmission control signal LOAD and a data polarity inversion control signal POL, and a first transition edge (e.g., a rising edge) of the data polarity inversion control signal POL is later than a second transition edge (e.g., a rising edge) of the data transmission control signal LOAD, and a first transition state (e.g., a high state) of the data polarity inversion control signal POL after the first transition edge is at least partially time coincident with a second transition state (e.g., a high state) of the data transmission control signal LOAD after the second transition edge.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL is later than the data transmission control signal LOAD by a time length tS2 in the same period of the data transmission control signal LOAD and the data polarity inversion control signal POL, so that the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD. The data polarity inversion control signal POL and the data transmission control signal LOAD are simultaneously in a high state for a time length tH2 after the rising edge.

Fig. 6B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure.

As shown in fig. 6B, the single mode indication signal includes the data transmission control signal LOAD 'and the data polarity inversion control signal POL', and a first transition edge (e.g., a rising edge) of the data polarity inversion control signal POL 'is earlier than a second transition edge (e.g., a rising edge) of the data transmission control signal LOAD', and a first transition state (e.g., a high state) of the data polarity inversion control signal POL 'after the first transition edge coincides at least partially in time with a second transition state (e.g., a high state) of the data transmission control signal LOAD' after the second transition edge.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL 'is earlier than the data transmission control signal LOAD' by the time length tS1 in the same period of the data transmission control signal LOAD 'and the data polarity inversion control signal POL', so that the rising edge of the data polarity inversion control signal POL 'is earlier than the rising edge of the data transmission control signal LOAD'.

The embodiment of fig. 6A and 6B can distinguish between the single mode transmission operation and the at least two modes of transmission operation by the data transmission control signal and the data polarity inversion control signal, and is easy to implement without modifying the hardware circuit of the interface. In this way, the same set of controller and source driver can selectively implement the first signaling protocol or the second signaling protocol as needed without providing a set of controller and source driver for the first signaling protocol and the second signaling protocol, respectively, and thus the cost of design, development, manufacturing, and management can be reduced for the supplier.

Fig. 7 shows a flowchart of another signal transmission method according to at least one embodiment of the present disclosure.

As shown in fig. 7, the signal transmission method includes steps S710 to S730. The signal transmission method shown in fig. 7 is performed by a source driver, for example. For example, the signal transmission method is used for a source driver to receive a display signal provided by a controller based on a clock signal.

Step S710: a reset signal provided by the controller is obtained.

Step S720: a first start signal provided by the controller is received after the reset signal is obtained. The first start signal includes a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of a clock signal employed by the display signal.

Step S730: after the first start signal is ended, a display signal provided by the controller is received.

The signal transmission method is beneficial to improving the frequency of signal transmission between the controller and the source driver.

With step S710, for example, in the example of fig. 1B, the timing controller TCON transmits the display signal within one frame display period to the source driver SD #1, the source driver SD #2, and the like through its own low voltage differential signal interface. The source driver SD #1, SD #2, and the like receive the display signals from the timing controller TCON through their own low voltage differential signal interfaces.

The timing controller TCON supplies a reset signal to the source driver SD #1, the source driver SD #2, and the like before the timing controller TCON and the source driver SD #1, the source driver SD #2, and the like perform the transmission of the display signal. Each source driver receives a reset signal provided by the control. For the reset signal, refer to the above description.

For step S720, the first start signal is, for example, the start signal st 'shown in fig. 3, and the start signal st' includes the base trigger signal BT and AT least one additional trigger signal AT that is consecutive after the base trigger signal.

For example, as shown in fig. 3, the basic trigger signal is a low level signal collected by a first active edge after the last active edge Q 'of the clock signal in a plurality of consecutive clock cycles for providing the reset signal, and the additional trigger signal is a low level signal collected by a second active edge after the last active edge Q' of the clock signal and a later active edge in the plurality of consecutive clock cycles.

Reference is made to the above description with respect to the base trigger signal and the additional trigger signal AT.

For example, the source driver and the controller communicate through a low voltage differential signaling interface to transmit a reset signal, a first start signal, and a display signal. Step S720 includes: after obtaining the reset signal, sampling the differential signal output by the low-voltage differential signal interface for multiple times at multiple rising edges of the clock signal, wherein the multiple times of sampling obtain a first initial signal, and the first initial signal comprises a basic trigger signal and at least one additional trigger signal.

In this example, the plurality of rising edges of the clock signal are active edges of the clock signal. The signal transmitted on the low voltage differential signal line pair is sampled on the rising edge of the clock signal. For example, the number of additional trigger signals is N, and after the reset signal is acquired, if a low-level signal is acquired at a rising edge of the clock signal, the low-level signal is the basic trigger signal, and the low-level signals acquired at N rising edges after the rising edge are N additional trigger signals.

For step S730, for example, signals collected from the first active edge of the clock signal after the end of the additional trigger signal are all display signals of one frame image until a reset signal for the next frame image is received again.

As shown in fig. 7, the signal transmission method may further include steps S740 to S750 in addition to steps S710 to S730.

Step S740: the second start signal provided by the controller is received after the reset signal is obtained. The second start signal comprises only the base trigger signal.

Step S750: and receiving a display signal provided by the controller after the second starting signal.

For step S740, the source driver receives a second start signal provided by the controller after getting the reset signal, for example. The second start signal is, for example, the start signal st shown in fig. 1C. For example, the basic trigger signal is a low level signal collected at the first active edge after the reset signal is obtained. If the low level signal is only acquired at the first active edge after the reset signal, the start signal only includes the basic trigger signal, and the start signal is the second start signal.

For step S750, the signal collected at the second active edge after the reset signal is the display signal.

In the above embodiment, a suitable reset format may be selected according to different requirements, so that the signal transmission method may adopt different reset formats for different clock frequencies, and the method has stronger applicability, and is beneficial to improving the frequency of signal transmission performed by the controller and the source driver.

The signal transmission method performed by the source driver corresponds to the signal transmission method performed by the controller, and is not described in detail.

Fig. 8 illustrates a schematic block diagram of a signal transmission apparatus 800 according to at least one embodiment of the present disclosure. The signal transmission apparatus 800 may be used to transmit a display signal to a source driver in a display apparatus.

For example, as shown in fig. 8, the signal transmission apparatus 800 includes a signal acquisition unit 810 and a signal providing unit 820.

The signal acquiring unit 810 is configured to acquire a reset signal, a first start signal, and a display signal. For example, the signal acquiring unit 810 may be, for example, an input interface for receiving a reset signal, a first start signal, and a display signal from an external device.

The signal providing unit 820 is configured to provide a reset signal to the source driver, and to provide a first start signal to the source driver after providing the reset signal to the source driver.

The first start signal includes a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal, and the display signal is provided to the source driver after the first start signal ends. The at least one additional trigger signal is determined by the controller based on a clock frequency of the clock signal.

The signal providing unit 820 is, for example, a low voltage differential signal interface.

The signal providing unit 820 may perform, for example, steps S10 to S30 described in fig. 2.

The signal transmission device 800 is advantageous in that the frequency of signal transmission between the controller and the source driver is increased, and the source driver has sufficient time to perform operations such as resetting and configuration to sufficiently prepare for transmission of the display signal.

Fig. 9 illustrates a schematic block diagram of a signal transmission apparatus 900 according to at least one embodiment of the present disclosure. The signal transmission device 900 is used for acquiring display signals from the controller.

For example, as shown in fig. 9, the signal transmission apparatus 900 includes a signal acquisition unit 910.

The signal acquiring unit 910 is configured to acquire a reset signal provided by the controller and receive a display signal provided by the controller after the first start signal ends in response to receiving the first start signal provided by the controller after the reset signal is obtained.

The first start signal includes a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

The signal providing unit 910 is, for example, a low voltage differential signal interface.

The signal acquisition unit 910 may perform, for example, steps S710 to S730 described in fig. 7.

The signal transmission apparatus 900 is advantageous in that the frequency of signal transmission between the controller and the source driver is increased, and the source driver has sufficient time to perform operations such as resetting and configuring to sufficiently prepare for transmission of the display signal.

For example, the signal obtaining unit 810, the signal providing unit 820, and the signal obtaining unit 910 may be hardware, software, firmware, or any feasible combination thereof. For example, the signal obtaining unit 810, the signal providing unit 820 and the signal obtaining unit 910 may be a dedicated or general circuit, a chip or a device, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the signal transmission apparatus 800 and the signal transmission apparatus 900 corresponds to each step of the foregoing signal transmission method, and for specific functions of the signal transmission apparatus 800 and the signal transmission apparatus 900, reference may be made to the description related to the signal transmission method, and details are not repeated here. The components and configurations of the signal transmission device 800 shown in fig. 8 and the signal transmission device 900 shown in fig. 9 are exemplary only, and not limiting, and the signal transmission device 800 and the signal transmission device 900 may include other components and configurations as needed.

At least one embodiment of the present disclosure provides an electronic device 1000. The electronic device 1000 comprises the signal transmission device provided by any embodiment of the disclosure. For example, the signal transmission apparatus may be the signal transmission apparatus 800 shown in fig. 8 or the signal transmission apparatus 900.

For another example, the electronic device includes the signal transmission device 800 and the signal transmission device 900. For the description of the electronic device, please refer to the signal transmission apparatus 800 and the signal transmission apparatus 900 above.

Fig. 10 illustrates a schematic block diagram of an electronic device 1000 provided by at least one embodiment of the present disclosure. As shown in fig. 10, the electronic device 1000 includes a controller 1010, a source driver 1020, and a display panel 1030.

The controller 1010 includes, for example, the signal transmission apparatus 800 to perform the signal transmission method described above with reference to fig. 2. The source driver 1020 includes, for example, a signal transmission apparatus 900 to perform the signal transmission method described above with reference to fig. 7. The display panel 1030 is, for example, a liquid crystal display panel, and receives a driving signal (i.e., a gray-scale voltage signal) supplied from the source driver 1020 to display an image.

The electronic device 1000 may be various electronic devices with an image display function, including but not limited to a smart phone, a tablet computer, a notebook computer, a display, a television, and the like.

The electronic device is advantageous in that the frequency of signal transmission between the controller and the source driver is increased, and the source driver has sufficient time to perform operations such as resetting and configuration to sufficiently prepare for transmission of the display signal.

Although as described above, there are the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (13)

1. A signal transmission method for a controller to transmit a display signal to a source driver based on a clock signal, the method comprising:

providing a reset signal to the source driver;

providing a first start signal to the source driver after providing the reset signal to the source driver, wherein the first start signal comprises a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal; and

providing the display signal to the source driver after the first start signal ends,

wherein the at least one additional trigger signal is determined by the controller based on a clock frequency of the clock signal.

2. The method of claim 1, further comprising:

acquiring a reset format, wherein the reset format comprises a first format and a second format;

providing the first start signal to the source driver after providing the reset signal to the source driver, comprising:

in response to the reset format being the first format, providing the first start signal to the source driver after providing the reset signal to the source driver.

3. The method of claim 2, further comprising:

in response to the reset format being the second format, providing a second start signal to the source driver after providing the reset signal to the source driver; and

providing the display signal to the source driver after the second start signal ends,

wherein the second start signal comprises only the base trigger signal.

4. The method of claim 2 or 3, wherein obtaining the reset format comprises:

acquiring the clock frequency; and

determining the reset format to be the first format in response to the clock frequency being greater than a preset frequency, or determining the reset format to be the second format in response to the clock frequency being less than or equal to the preset frequency.

5. The method of claim 1, wherein the base trigger signal and the at least one additional trigger signal are respectively corresponded at least two consecutive rising edges of the clock signal.

6. The method of claim 1, wherein the controller sequentially provides the reset signal, the first start signal, and the display signal to the source driver through a low voltage differential signal interface.

7. A signal transmission method for a source driver to receive a display signal provided from a controller based on a clock signal, the method comprising:

acquiring a reset signal provided by the controller; and

in response to receiving a first start signal provided by the controller after the reset signal is derived;

receiving the display signal provided by the controller after the first start signal is ended,

wherein the first start signal comprises a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of a clock signal employed by the display signal.

8. The method of claim 7, further comprising:

in response to receiving a second start signal provided by the controller after the reset signal is derived,

receiving the display signal provided by the controller after the second start signal,

wherein the second start signal comprises only the base trigger signal.

9. The method of claim 1 or 7, wherein the source driver and the controller communicate over a low voltage differential signal interface to transmit the reset signal, the first start signal, and the display signal.

10. The method of claim 9, wherein receiving the first start signal provided by the controller after deriving the reset signal comprises:

after the reset signal is obtained, sampling the differential signal output by the low-voltage differential signal interface for multiple times on multiple rising edges of the clock signal;

the plurality of samples results in the first start signal, wherein the first start signal comprises a base trigger signal and the at least one additional trigger signal.

11. A signal transmission apparatus for a controller to transmit a display signal to a source driver based on a clock signal, the apparatus comprising:

a signal providing unit configured to provide a reset signal to the source driver, provide a first start signal to the source driver after providing the reset signal to the source driver, wherein the first start signal includes a base trigger signal and at least one additional trigger signal consecutive after the base trigger signal, and provide the display signal to the source driver after the first start signal ends,

wherein the at least one additional trigger signal is determined by the controller based on a clock frequency of the clock signal.

12. A signal transmission apparatus for a source driver to receive a display signal provided from a controller based on a clock signal, the apparatus comprising:

a signal acquisition unit configured to acquire a reset signal provided by the controller and, in response to receiving a first start signal provided by the controller after obtaining the reset signal, receive the display signal provided by the controller after the first start signal ends,

wherein the first start signal comprises a base trigger signal and at least one additional trigger signal that is consecutive after the base trigger signal, the at least one additional trigger signal being determined by the controller based on a clock frequency of the clock signal.

13. An electronic device, comprising:

a signal transmission arrangement according to claim 11 or 12.

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