KR101630335B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display capable of reducing a cost and a size by generating a common voltage using a data driver, and more particularly to a liquid crystal display which receives digital image data necessary for pixels of a horizontal line from a system, A timing controller for directly outputting the input digital image data based on the level of the digital common voltage data to be used as a reference for determining the logic level of the input digital image data or inverting the logic of all bits constituting the input digital image data and outputting the inverted logic; And supplying the digital common voltage data and the digital image data from the timing controller, selecting an analog common voltage corresponding to the gradation of the digital common voltage data as a common voltage transmission line, And a data driver for selecting and supplying corresponding analog pixel voltages to the data lines of the liquid crystal panel; Each of the pixels on the horizontal line displays an image according to a pixel voltage from the corresponding data line and a common voltage from the common voltage transmission line.

Liquid crystal display, common voltage, data driver, digital common voltage data

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of reducing cost and size by eliminating a common voltage generator for generating and outputting a common voltage.

The liquid crystal display device is supplied with a common voltage to maintain the pixel voltage for one frame period. This common voltage is supplied from the common voltage generator. Conventionally, a common voltage generator is necessarily required to generate a common voltage, which is a problem in reducing the size of a liquid crystal display device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display capable of reducing a cost and a size by generating a common voltage using a data driver.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of pixels arranged in a matrix, A timing controller for directly outputting the input digital image data based on the level of the input digital image data or inverting logic of all bits constituting the input digital image data and outputting the inverted logic; And supplying the digital common voltage data and the digital image data from the timing controller, selecting an analog common voltage corresponding to the gradation of the digital common voltage data as a common voltage transmission line, And a data driver for selecting and supplying corresponding analog pixel voltages to the data lines of the liquid crystal panel; Each of the pixels on the horizontal line displays an image according to a pixel voltage from the corresponding data line and a common voltage from the common voltage transmission line.

A gate line and a common branch line commonly connected to the pixels of the horizontal line; And a common voltage switching unit for supplying a common voltage from the common voltage transmission line to the pixels of the horizontal line through the common branch line in response to a scan pulse from the gate line.

Each pixel includes a pixel electrode and a common electrode facing each other with a liquid crystal layer interposed therebetween; A data switching element for supplying a pixel voltage from the corresponding data line to the pixel electrode in accordance with a scan pulse from the gate line; A liquid crystal capacitance capacitor formed between the pixel electrode and the common electrode; And an auxiliary capacitance capacitor formed between the pixel electrode and the common branch line.

Wherein the common voltage switching unit includes: a common voltage switching element for supplying a common voltage from a common voltage transmission line to the common branch line in response to a scan pulse from the gate line; And a common capacitor formed between the common branch line and the ground terminal.

A gate line and a common branch line commonly connected to the pixels of the horizontal line; A common voltage switching circuit for supplying a common voltage from the common voltage transmission line to each of the pixels of the one horizontal line through the common branch line in response to a previous scan pulse outputted at a time earlier than a scan pulse supplied to the gate line, And further comprising:

Each pixel includes a pixel electrode and a common electrode facing each other with a liquid crystal layer interposed therebetween; A data switching element for supplying a pixel voltage from the corresponding data line to the pixel electrode in accordance with a scan pulse from the gate line; A liquid crystal capacitance capacitor formed between the pixel electrode and the common electrode; And an auxiliary capacitance capacitor formed between the pixel electrode and the common branch line.

Wherein the common voltage switching unit includes: a common voltage switching device for supplying a common voltage from a common voltage transmission line to the common branch line in response to a scan pulse from the previous gate line; And a common capacitor formed between the common branch line and the ground terminal.

The level of the digital common voltage data has a level corresponding to a highest gradation value of the digital image data and a level corresponding to a lowest gradation value of the digital image data.

Wherein the timing controller outputs the input digital image data as it is when the digital common voltage data has a level corresponding to the lowest gray level value; When the digital common voltage data has a level corresponding to the highest gray level value, the bit of the input digital image data is inverted and output.

The level of the digital common voltage data changes in units of one of a horizontal period, a one-frame period, and an n-frame period.

The data driver including a plurality of data drive integrated circuits driving the data lines in a divided manner; The analog common voltage is output from the first output pin of the first data drive IC connected to the data lines including the first data line among the plurality of data drive ICs; And the first output pin of the first data drive IC is connected to the common voltage transmission line.

The data driver including a plurality of data drive integrated circuits driving the data lines in a divided manner; The analog common voltage is output from a dummy output pin of a last data drive IC connected to data lines including a last data line among the plurality of data drive ICs; And a dummy output pin of the last data drive IC is connected to the common voltage transmission line.

The liquid crystal display device according to the present invention has the following effects.

First, a common voltage is generated by using a data driver, so that an existing common voltage generator is not needed, thereby reducing the cost.

Second, the space occupied by the common voltage generator is reduced, which is advantageous for thinning the liquid crystal display device.

Third, since the polarity of the pixel voltage is changed by changing the magnitude of the common voltage, the magnitude of the reference voltage required to generate the pixel voltage can be reduced by 50% compared with the conventional one. Accordingly, the size of the data drive IC can be reduced, and the liquid crystal display device can be driven with low power.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display device according to an exemplary embodiment of the present invention includes a liquid crystal panel PN in which a plurality of pixels PXL and a plurality of common voltage switching units VSW are arranged in a matrix form, A gate driver GD for sequentially driving the gate lines GL1 to GLn of the liquid crystal panel PN and a gate driver GD for simultaneously driving the analog pixels PXL A data driver DD for supplying the analog common voltages to the common voltage transmission line VL and a timing controller TC for controlling the driving of the gate driver GD and the data driver DD do.

The pixels PXL are formed on the display portion DP of the liquid crystal panel PN and the common voltage switching portions VSW are formed on the non-display portion of the liquid crystal panel PN.

The timing controller TC generates a data control signal DCS and a gate control signal GCS using a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync and a dot clock DCLK input from the system, And supplies it to the driver DD and the gate driver GD. The data control signal DCS includes a dot clock, a source shift clock, a source enable signal, a polarity inversion signal, and the like, and the data control signal is supplied to the data driver. The gate control signal GCS includes a gate start pulse, a gate shift clock, a gate output enable, and the like, and the gate control signal is input to the gate driver GD. In particular, the timing controller TC receives the digital image data (R / G / B Data) necessary for the pixels (PXL) of one horizontal line from the system and receives the digital image data (R / G / B Data) (R / G / B Data) based on the level of the digital common voltage data (Data_Vcom) as a reference for determining the polarity of the input digital image data Data) is inverted to determine whether to output the logic of all the bits.

The level of the digital common voltage data Data_Vcom has a level corresponding to the highest gradation of the digital image data R / G / B Data and a level corresponding to the lowest gradation of the digital image data. For example, if the digital image data is 8-bit data, the digital image data (R / G / B Data) is converted from the lowest gradation (0 gradation) corresponding to the digital code 00000000 to the highest gradation 255 And the digital common voltage data Data_Vcom described above has a digital code corresponding to two of the 256 gradations. Specifically, the digital common voltage data Data_Vcom may have a digital code 00000000 corresponding to the lowest gradation or a digital code 11111111 corresponding to the highest gradation.

When the digital common voltage data Data_Vcom has a level corresponding to the lowest gradation, the timing controller TC directly outputs the digital image data (R / G / B Data) inputted thereto, whereas the timing controller TC) inverts and outputs the bit of the digital image data (R / G / B Data) inputted thereto when the digital common voltage data Data_Vcom has a level corresponding to the highest gradation.

For example, when the digital code of the digital common voltage data (Data_Vcom) is 00000000 corresponding to the lowest gradation (0 gradation), and the digital image data related to the digital common voltage data (Data_Vcom) input from the system to the timing controller (R / G / B Data) is 00000011 corresponding to three gradations, the digital video data (R / G / B Data) is not modulated, that is, the video data of 00000011 is directly output. At this time, the timing controller TC first transfers the digital common voltage data Data_Vcom to the data driver, and supplies the digital video data Data_DSP synchronized with the digital common voltage data Data_Vcom to the data driver DD. Lt; / RTI > On the other hand, the digital code of the digital common voltage data Data_Vcom is 11111111 corresponding to the highest gradation (256 gradations), and the digital image data (R / G / B) related to the digital common voltage input from the system to the timing controller TC Data) is 00000011 corresponding to three gray levels, the timing controller TC reverses the logic of all bits constituting the video data to convert the digital video data (R / G / B Data) to 252 gray scales It is changed to the corresponding 11111100 and output. At this time, the timing controller TC first transfers the digital common voltage data Data_Vcom to the data driver DD, and then supplies the digital video data Data_DSP synchronized with the digital common voltage data Data_Vcom to the data driver DD (DD).

The reason why the timing controller TC inverts all the bits of the digital image data when the digital common voltage data Data_Vcom has the highest gradation is because the pixel PXL voltage having different gradations and showing different polarities is applied to the common voltage So that the same value is always maintained with respect to the change of the level.

2 shows the relationship between the common voltage and the pixel (PXL) voltage.

2 (a) shows the analog common voltage of the lowest gray level generated by the lowest common gray level digital common voltage data (Data_Vcom). Since the analog common voltage corresponds to the lowest gradation as shown in FIG. 2A, the analog pixel (PXL) voltages have values equal to or larger than the common voltage. Therefore, when the digital common voltage data Data_Vcom has a digital code corresponding to the lowest gradation, the pixel PXL voltages have positive polarity.

On the other hand, FIG. 2 (b) shows the analog common voltage of the highest gradation generated by the digital common voltage data Data_Vcom of the highest gradation. As shown in FIG. 2B, the analog common voltage corresponds to the highest gradation, so that the analog pixel (PXL) voltages have the same or smaller value as the common voltage. Therefore, when the digital common voltage data Data_Vcom has a digital code corresponding to the highest gradation, the pixel PXL voltages have a negative polarity.

In the present invention, since the polarity of the voltage of the pixel (PXL) is changed by changing the magnitude of the common voltage, the magnitude of the reference voltage (Vdd) required to generate the voltage of the pixel (PXL) can be reduced by 50%. Accordingly, the size of the data drive IC can be reduced, and the liquid crystal display device can be driven with low power.

3 is a timing chart of digital common voltage data Data_Vcom and digital image data transmitted from a timing controller TC to a data driver according to an embodiment of the present invention.

First, digital common voltage data (Data_Vcom) and digital video data (Data_DSP) from the timing controller (TC) in the present invention are transmitted to a data driver (DD) through an interface unit including a mini-LVDS transmitter and a mini-LVDS receiver do.

3A and 3B, the reset signal RST for resetting the mini-LVDS transmitting unit and the mini-LVDS receiving unit is output from the timing controller TC to the interface unit And the second interval T2 is a period corresponding to a period during which the timing controller TC transmits a start signal ST to the interface unit for instructing the interface unit to prepare to receive data And the third period T3 is a period corresponding to the period during which the digital common voltage data Data_Vcom is transmitted from the timing controller TC and the fourth and fifth periods T5 and T6 are the periods corresponding to the timing controller TC (Data_DSP) synchronized with the digital common voltage data (Data_Vcom) are transmitted. The fourth period T4 corresponds to the transmission period of the first digital image data and the fifth period T5 corresponds to the transmission period of the second digital image data.

When the timing controller TC receives digital image data (R / G / B Data) corresponding to the fourth section of FIG. 3A from the system, as shown in FIG. 3A, , And the digital common voltage data (Data_Vcom) corresponds to the lowest gradation, the timing controller (TC) outputs the input digital image data as it is.

3 (b), when the digital common voltage data Data_Vcom corresponds to the highest gradation, the timing controller TC outputs the logic of the input digital image data R / G / B Data And outputs the inverted signals.

The data driver DD samples the digital common voltage data Data_Vcom and the digital image data according to the data control signal DCS from the timing controller TC and then outputs the sampled digital common voltage data Data_Vcom and one horizontal line Latches the image data for each of the pixels PXL arranged in each horizontal period (1H, 2H, ...) and selects an analog common voltage corresponding to the gradation of the latched digital common voltage data Data_Vcom And supplies the analog pixel (PXL) voltages corresponding to the gradations of the latched digital image data to the data lines DL1 to DLm. That is, the data driver DD outputs the digital common voltage data Data_Vcom and the digital image data Data_DSP from the timing controller TC to the analog common voltage and the pixel PXL using the gamma voltage input from the power generator, And supplies them to the common voltage transmission line (VL) and the data lines (DL1 to DLm).

The gate driver GD includes a shift register for sequentially generating scan pulses in response to a gate start pulse of a gate control signal from the timing controller TC and a shift register for shifting the voltage of the scan pulse to a voltage level suitable for driving the liquid crystal cell And a level shifter. The gate driver GD sequentially supplies the scan pulses to the gate lines GL1 to GLn in response to the gate control signal.

A plurality of common branch lines parallel to the gate lines GL1 to GLn are formed in the liquid crystal panel PN. Each common branch line is formed to cross the pixels PXL of the respective horizontal lines HL1 to HLn. In other words, k (k is a natural number) th common branch line is formed to cross the pixels PXL of one horizontal line arranged along the k-th horizontal line, (PXLs) are commonly connected to the k-th common branch line.

The common voltage switching unit VSW supplies a common voltage from the common voltage transmission line VL to each of the pixels PXL of the one horizontal line via the common branch line in response to the scan pulse from the corresponding gate line.

4 is a detailed configuration diagram of a common voltage switching unit VSW and a pixel PXL according to the first embodiment of the present invention.

The pixel PXL includes a pixel electrode PE, a common electrode CE, a data switching device Tr_DSP, a liquid crystal capacitance capacitor Clc, and a storage capacitance capacitor Cst, as shown in FIG.

The pixel electrode PE and the common electrode CE face each other, and a liquid crystal layer is formed therebetween. The data switching element Tr_DSP supplies a pixel (PXL) voltage from the data line to the pixel electrode PE in accordance with a scan pulse from the gate line. A liquid crystal capacitance capacitor Clc is formed between the pixel electrode PE and the common electrode CE. The storage capacitance capacitor Cst is formed between the pixel electrode PE and the common branch line. The pixel PXL voltage is stored in the liquid crystal capacitance capacitor Clc and the storage capacitance capacitor Cst and is held for one frame period.

The common voltage switching unit VSW includes a common voltage switching element Tr_Vcom and a common capacitor Cvcom.

The common voltage switching element Tr_Vcom supplies a common voltage from the common voltage transmission line VL to the common branch line in response to the scan pulse from the gate line. A common capacitor Cvcom is formed between the common branch line and the ground terminal. The common voltage is stored in the common capacitor Cvcom and held for one frame period.

The operations of the common voltage switching unit VSW and the pixel PXL configured as above will be described in detail with reference to FIGS. 4 and 5. FIG.

5 is a view showing a waveform of a scan pulse supplied to the gate line of FIG.

As shown in FIG. 5, the scan pulses SC1 to SCn are sequentially supplied from the first gate line GL1 to the nth gate line GLn.

The data driver DD supplies the common voltage to the common voltage transmission line VL and supplies the pixel (PXL) voltages for one horizontal line to the data lines DL1 to DLm.

In this case, the common voltage switching element Tr_Vcom of the j-th common voltage switching unit VSW connected to the j-th gate line and the data switching element Tr_Vcom of the j- Are all turned on.

Each turn-on data switching element supplies a pixel (PXL) voltage from each data line to each pixel electrode PE. At this time, the common voltage from the common voltage transmission line (VL) is supplied to the jth common branch line through the jth common voltage switching element turned on. Therefore, each of the pixels PXL of the j-th horizontal line maintains the image by the common voltage from the j-th common branch line and the pixel (PXL) voltage supplied to each pixel electrode PE.

6 is a detailed configuration diagram of the common voltage switching unit VSW and the pixel PXL according to the second embodiment of the present invention.

The common voltage switching unit VSW and the pixel PXL according to the second embodiment of the present invention are substantially the same as the structure of the common voltage switching unit VSW and the pixel PXL of the first embodiment shown in FIG. But differs in the connection relationship between the common voltage switching unit VSW and the pixel PXL.

6, the common voltage switching unit VSW supplies the common voltage from the common voltage transmission line VL to the common branch line in response to the previous scan pulse outputted at a time earlier than the scan pulse supplied to the gate line To the pixels PXL of the horizontal line. For example, the j-th common voltage switching unit VSW switches the common voltage from the common voltage transmission line VL to the j-th common branch line when the scan pulse is supplied to the j-th gate line, And supplies the voltage to the pixels PXL of the (j + 1) -th horizontal line.

On the other hand, in the present invention, the level of the digital common voltage data (Data_Vcom) described above is changed in units of one period of one horizontal period, one frame period, and n frame period, thereby driving the liquid crystal display device in the line inversion and frame inversion have. For example, by changing the level of the digital common voltage data (Data_Vcom) every horizontal period, the lowest gray level common voltage is supplied to the pixels PXL of the odd-numbered horizontal lines, and the pixels PXL of the odd- The common voltage of the highest gray level can be supplied. In such a case, the pixels PXL of the odd-numbered horizontal lines display an image using the pixel PXL of the positive polarity, and the pixels PXL of the odd-numbered horizontal lines display the image using the pixel PXL of the negative polarity And displays an image.

7 is a view for explaining the position of the common voltage transmission line VL according to the first embodiment of the present invention.

As shown in Fig. 7, the data driver DD includes a plurality of data drive ICs (DD-ICs) driving the data lines DL1 to DLm in a divided manner.

At this time, a first data drive IC (DD-IC) connected to the data lines including the first data line among the plurality of data drive ICs (DD- The analog common voltage is output from the first output pin P of the first analog-to-digital converter (DD-IC). The first output pin (P) of the first data drive IC (DD-IC) is connected to the common voltage transmission line (VL).

8 is a view for explaining the position of the common voltage transmission line VL according to the second embodiment of the present invention.

As shown in Fig. 7, the data driver DD includes a plurality of data drive ICs (DD-ICs) driving the data lines DL1 to DLm in a divided manner.

At this time, from the dummy output pin (P) of the last data drive IC (DD-IC) connected to the data lines including the last data line among the plurality of data drive ICs (DD- Is output. According to the number of data lines, a dummy output pin (P) which is not connected to the data line among the output pins (P) of the last data drive IC (DD-IC) (P). A dummy output pin (P) of the last data drive IC (DD-IC) is connected to the common voltage transmission line (VL).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention;

2 is a diagram showing a relationship between a common voltage and a pixel voltage

3 is a timing diagram of digital common voltage data and digital image data transmitted from a timing controller to a data driver according to an embodiment of the present invention

4 is a detailed configuration diagram of a common voltage switching unit and a pixel according to the first embodiment of the present invention

5 is a view showing a waveform of a scan pulse supplied to the gate line of FIG. 4

6 is a detailed configuration diagram of a common voltage switching unit and a pixel according to a second embodiment of the present invention

7 is a view for explaining the position of a common voltage transmission line according to the first embodiment of the present invention;

8 is a view for explaining a position of a common voltage transmission line according to a second embodiment of the present invention;

Claims (12)

And supplies the digital image data required for the pixels of one horizontal line from the system and outputs the inputted digital image data as it is based on the level of the digital common voltage data as a reference for determining the polarity of the digital image data, A timing controller for inverting and outputting logic of all bits constituting the input digital image data; And Wherein the timing controller supplies digital common voltage data and digital image data, selects an analog common voltage corresponding to the gradation of the digital common voltage data, and supplies the selected analog common voltage to the common voltage transmission line, And a data driver for selecting and supplying analog pixel voltages to the data lines of the liquid crystal panel; And, Wherein each of the pixels of the horizontal line displays an image in accordance with a pixel voltage from the corresponding data line and a common voltage from the common voltage transmission line. The method according to claim 1, A gate line and a common branch line commonly connected to the pixels of the horizontal line; And a common voltage switching unit for supplying a common voltage from the common voltage transmission line to each of the pixels of the one horizontal line through the common branch line in response to a scan pulse from the gate line. 3. The method of claim 2, In each pixel, A pixel electrode and a common electrode facing each other with a liquid crystal layer therebetween; A data switching element for supplying a pixel voltage from the corresponding data line to the pixel electrode in accordance with a scan pulse from the gate line; A liquid crystal capacitance capacitor formed between the pixel electrode and the common electrode; And And a storage capacitor formed between the pixel electrode and the common branch line. The method of claim 3, Wherein the common voltage switching unit includes: A common voltage switching element for supplying a common voltage from a common voltage transmission line to the common branch line in response to a scan pulse from the gate line; And And a common capacitor formed between the common branch line and the ground terminal. The method according to claim 1, A gate line and a common branch line commonly connected to the pixels of the horizontal line; A common voltage switching circuit for supplying a common voltage from the common voltage transmission line to each of the pixels of the one horizontal line through the common branch line in response to a previous scan pulse outputted at a time earlier than a scan pulse supplied to the gate line, The liquid crystal display device further comprising: 6. The method of claim 5, In each pixel, A pixel electrode and a common electrode facing each other with a liquid crystal layer therebetween; A data switching element for supplying a pixel voltage from the corresponding data line to the pixel electrode in accordance with a scan pulse from the gate line; A liquid crystal capacitance capacitor formed between the pixel electrode and the common electrode; And And a storage capacitor formed between the pixel electrode and the common branch line. The method according to claim 6, Wherein the common voltage switching unit includes: A common voltage switching element for supplying a common voltage from the common voltage transmission line to the common branch line in response to the previous scan pulse; And And a common capacitor formed between the common branch line and the ground terminal. The method according to claim 1, Wherein the level of the digital common voltage data has one of a level corresponding to a highest gradation value of the digital image data and a level corresponding to a lowest gradation value of the digital image data. 9. The method of claim 8, The timing controller includes: When the digital common voltage data has a level corresponding to the lowest gradation value, outputs the inputted digital image data as it is; And, And inverts and outputs the bits of the input digital image data when the digital common voltage data has a level corresponding to the highest gradation value. The method according to claim 1, Wherein the level of the digital common voltage data changes in units of one of a horizontal period, one frame period, and n frame period. The method according to claim 1, The data driver including a plurality of data drive integrated circuits driving the data lines in a divided manner; The analog common voltage is output from the first output pin of the first data drive IC connected to the data lines including the first data line among the plurality of data drive ICs; And the first output pin of the first data drive IC is connected to the common voltage transmission line. The method according to claim 1, The data driver including a plurality of data drive integrated circuits driving the data lines in a divided manner; The analog common voltage is output from a dummy output pin of a last data drive IC connected to data lines including a last data line among the plurality of data drive ICs; And a dummy output pin of the last data drive IC is connected to the common voltage transmission line.

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