CN115938266A - Signal transmission method and device and electronic equipment - Google Patents

Abstract

The disclosure relates to a signal transmission method, a signal transmission device and electronic equipment. The signal transmission method is used for a plurality of electronic devices in cascade connection, each of the plurality of electronic devices has a corresponding sequencing serial number in the cascade connection, each of the plurality of electronic devices is communicated with a controller to receive a data stream and a clock signal from the controller, the data stream comprises a plurality of parts corresponding to the plurality of electronic devices, and the method comprises the following steps: enabling a plurality of electronic devices to count based on a clock signal to obtain a current count value of each electronic device; the plurality of electronic devices are each caused to receive a portion corresponding to itself from the data stream in response to its current count value matching its own rank number. The method is beneficial to improving the frequency of signal transmission.

Description

Signal transmission method and device and electronic equipment

Technical Field

The embodiment of the disclosure relates to a signal transmission method, a signal transmission device and electronic equipment.

Background

With the development of integrated circuits and electronic technologies, a plurality of electronic devices are often cascaded to transmit signals. For example, in the field of liquid crystal display panels or Organic Light Emitting Diode (OLED) display panels, a plurality of cascaded source driving chips provide image data of a row of pixel units with the image data, so that gray voltages required for displaying gray scales required for displaying an image are formed in the pixel units of each row in a progressive scanning manner, for example, and one frame of image is displayed.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal transmission method for a plurality of electronic devices in a cascade, each of the plurality of electronic devices having a corresponding sequencing number in the cascade, each of the plurality of electronic devices in communication with a controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices, the method comprising: enabling the plurality of electronic devices to count based on the clock signal to obtain current count values of the electronic devices; causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its current count value matching its own sorting sequence number.

For example, in a signal transmission method provided in an embodiment of the present disclosure, the method further includes: causing each of the plurality of electronic devices to acquire a sequencing indication signal; and each electronic device determines the sequencing serial number of the electronic device according to the sequencing indication signal of the electronic device.

For example, in a signal transmission method provided by an embodiment of the present disclosure, the plurality of electronic devices include a master device arranged at a first position in the cascade and at least one slave device arranged at a subsequent position of the master device in the cascade in sequence, and causing each of the plurality of electronic devices to acquire the ordering indication signal includes: the at least one slave device each obtains the ordering indication signal for each slave device from a superior device.

For example, in a signal transmission method provided in an embodiment of the present disclosure, the method further includes: enabling each electronic device at the current stage to update the sequencing indication signal of the electronic device at the current stage obtained from the electronic device at the previous stage; and providing the updated sequencing indication signal for the next-stage electronic device in the cascade.

For example, in a signal transmission method provided by an embodiment of the present disclosure, the sorting indication signal includes at least one pulse signal.

For example, in a signal transmission method provided in an embodiment of the present disclosure, each electronic device determines its own sequencing serial number according to its own sequencing indication signal, including: and each electronic device determines the sequencing serial number of the electronic device according to the number of the received at least one pulse signal.

For example, in a signal transmission method provided by an embodiment of the present disclosure, enabling each electronic device at a current stage to update a sorting indication signal obtained from an electronic device at a previous stage includes: incrementing each current stage electronic device by the number of the at least one pulse signal received from the previous stage device.

For example, in a signal transmission method provided by an embodiment of the present disclosure, causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to matching of its own current count value with its own sorting order number includes: acquiring an expected count value of a clock signal corresponding to each electronic device according to the self sequencing serial number of each electronic device; and causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its current count value coinciding with its expected count value.

For example, in a signal transmission method provided in an embodiment of the present disclosure, the connecting each electronic device and the controller through a low-voltage differential signal line pair, and acquiring an expected count value of a clock signal corresponding to each electronic device according to a sequence number of each electronic device itself includes: acquiring the number of data channels of each electronic device, the number of low-voltage differential signal line pairs and the number of data input ports of the electronic device; and calculating the expected count value of the clock signal corresponding to each electronic device based on the sorting serial number, the number of the data channels, the number of the low-voltage differential signal line pairs and the number of the data input ports.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the calculation formula of the expected count value is as follows: CV = (CN/IDP) × SSN/(P/NB), CV representing the expected count value, CN representing the number of data lanes, IDP representing the number of periodically processed data lanes, SSN representing the sort number, P representing the number of pairs of low voltage differential signal lines, and NB representing the number of input ports of the electronic device.

For example, in a signal transmission method provided by an embodiment of the present disclosure, the plurality of electronic devices include a plurality of source driving chips, the controller includes a timing controller, and the data stream includes image data.

For example, in a signal transmission method provided by an embodiment of the present disclosure, a sequence number of each source driving chip is acquired during a vertical blank period of scanning controlled by the timing controller.

For example, in a signal transmission method provided by an embodiment of the present disclosure, a timing controller provides a display signal through a low voltage differential signal interface according to at least two modes, the display signal includes a plurality of display sub-signals, the at least two modes respectively provide the display sub-signals, the at least two modes include a line configuration mode and a frame configuration mode, the image data is provided in the line configuration mode during an image display period, and the frame configuration data is provided in at least the frame configuration mode during a vertical blanking period.

For example, in a signal transmission method provided in an embodiment of the present disclosure, a master source driver chip in a plurality of source driver chips provides the ordering indication signal to a slave source driver chip that is arranged at a subsequent bit of the master source driver chip in the cascade and is adjacent to the master source driver chip in response to receiving the frame configuration data, and the master source driver is a source driver chip that is arranged at a head in the cascade.

At least one embodiment of the present disclosure provides a signal transmission apparatus comprising a cascade of a plurality of electronic devices, each having a respective sequencing number in the cascade, each in communication with a controller to receive a data stream and a clock signal from the controller, the data stream comprising a plurality of portions corresponding to the plurality of electronic devices, the apparatus comprising: a counting unit configured to cause each of the plurality of electronic devices to count based on the clock signal; a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting order number.

At least one embodiment of the present disclosure provides an electronic device comprising a controller, and a signal transmission apparatus comprising a cascade of a plurality of electronic devices, each of the plurality of electronic devices having a respective sequencing number in the cascade, each of the plurality of electronic devices in communication with the controller to receive a data stream and a clock signal from the controller, the data stream comprising a plurality of portions corresponding to the plurality of electronic devices, the signal transmission apparatus comprising: a counting unit configured to count each of the plurality of electronic devices based on the clock signal; a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting number.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 shows a schematic diagram of a signal transmission method applied to a source driver;

fig. 2 illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure;

fig. 3 illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 4 illustrates a schematic diagram of each slave device acquiring a sorting indicator signal from a higher-level device according to at least one embodiment of the present disclosure;

fig. 5 is a flow chart illustrating another signal transmission method provided by at least one embodiment of the present disclosure;

fig. 6 illustrates a flowchart of a method of step S20 in fig. 2 according to at least one embodiment of the present disclosure;

fig. 7A and 7B are schematic signal formats of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

FIG. 7C illustrates a schematic diagram of transmitting a sequencing indication signal between a plurality of electronic devices provided by at least one embodiment of the present disclosure;

fig. 8 illustrates a schematic block diagram of a signal transmission apparatus 800 according to at least one embodiment of the present disclosure; and

fig. 9 illustrates a schematic block diagram of an electronic device 900 provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are within the scope of protection of the disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1 shows a schematic diagram of a signal transmission method applied to a source driver.

As shown in fig. 1, the source driver 101 includes a plurality of source-driving chips which are cascaded, for example, the plurality of source-driving chips include a master device SIC1 arranged at the head in the cascade, and a slave device SIC2, a slave device SIC3, and the like arranged at the subsequent bits of the master device SIC1 in sequence.

Each source driver chip is coupled to the controller 102 to receive a data stream and a clock signal CLK from the controller. The controller may be, for example, a timing controller, and the data stream may include, for example, image data for the pixel unit to display an image. The source driving chips are respectively connected with the pixel units in the pixel array. For example, the master device SIC1, the slave device SIC2, and the slave device SIC3 connect the plural columns of pixel cells 103, the plural columns of pixel cells 104, and the plural columns of pixel cells 105, respectively, to supply image data to the plural columns of pixel cells 103, the plural columns of pixel cells 104, and the plural columns of pixel cells 105, respectively.

The source driver, controller, and pixel array shown in fig. 1 are applied to a display panel, for example. Various driving circuits for the display panel generally include a scan driving integrated circuit (also referred to as a gate driver or G-IC) and the like in addition to a source driver and a controller. The controller is mainly used to convert data signals, control signals, clock signals, and the like received from the outside (e.g., a signal source such as a storage device, a network modem, and the like) into data signals, gate signals, control signals, clock signals, and the like suitable for a source driver and a gate driver for implementing image display driving of the display panel. For example, the Controller may be a Timing Controller (TCON). The source driver is mainly used for receiving the digital signals (display signals or image signals) and control signals and the like provided by the controller, converting the digital signals into corresponding analog gray scale voltage signals through analog-to-digital conversion, and inputting the analog gray scale voltage signals into each row of pixel units of the pixel array of the display panel. The gate driver is mainly used for starting pixel units of each row of the pixel array line by line (or interlaced line), for example, and is matched with the source driver under the action of the control signal, and a required data signal is input into the corresponding pixel unit for the started pixel unit line, so that the pixel unit can display according to the data signal.

In the process that the controller 102 provides the data stream to each source driver chip, the source driver determines whether to receive the data stream from the controller 102 according to the start indication signal EIO to obtain a partial data signal corresponding to itself in the data stream.

For example, each slave source driver chip receives a partial data signal from the controller 102 according to a clock signal in response to receiving the start indication signal EIO.

In some embodiments, for example, each source driver chip transmits a start indication signal to its next source driver chip, and the next source driver chip receives a partial data signal according to the frequency of the clock signal in response to the start indication signal. As shown in fig. 1, each source driver chip includes an indication signal input port EIO1 and an indication signal output port EIO2. The indication signal input port EIO1 is configured to receive a start indication signal, and the indication signal output port EIO2 is configured to provide a start indication signal for a next source driver chip to the next source driver chip.

As shown in fig. 1, for example, the data stream provided by the controller 102 includes a reset signal, image data (e.g., RGB data) applied to the respective source driving chips, and invalid data.

For example, after each source driver chip receives a reset signal, the master device acquires RGB data of the master device from the controller 102 in response to acquisition of the start instruction signal from its own instruction signal input port EIO 1. For example, the master SIC1 supplies the start instruction signal EIO2_1 for the first slave SIC2 to the first slave SIC2 through its own instruction signal output port EIO2 in response to the completion of receiving the RGB data of the master, and the first slave SIC2 receives the RGB data of the first slave supplied from the controller 102 in response to the start instruction signal EIO2_1. After the first slave SIC2 receives the RGB data of the first slave, a start indication signal EIO2_2 for the second slave SIC3 is supplied to the second slave SIC3 through its own indication signal output port EIO2, and the second slave SIC3 receives the RGB data of the second slave supplied from the controller 102 in response to the start indication signal EIO2_ 2.

The indication signal input EIO1 of the master device SIC1 can be connected, for example, to a controller or other device to start receiving the partial data stream provided by the controller 102 in response to control by the controller or other device and to provide a start indication signal EIO2_1 for the first slave device SIC2 to the first slave device SIC2.

As the frequency of signal transmission between the controller and the source driver increases, the delay of the start indication signal EIO in sequentially transmitting from the master device to the plurality of slave devices becomes critical. If the delay of the start indication signal EIO is large, the source driver chip cannot receive the complete or correct image data. Therefore, the delay of the start indication signal EIO seriously affects the frequency of signal transmission between the controller and the source driver.

To mitigate the effect of, for example, a delay of the start indication signal EIO on the signal transmission frequency, the present disclosure proposes a method of signal transmission. The signal transmission method distributes sequencing serial numbers to each electronic device in the cascade connection, so that each electronic device counts based on clock signals to obtain a current counting value of the electronic device; the plurality of electronic devices are each caused to receive a portion corresponding to itself from the data stream in response to their current count value matching their own rank number. The signal transmission method ensures that the transmission of the data stream does not depend on the initial indication signal, thereby avoiding the influence caused by the delay of the initial indication signal in the transmission process and being beneficial to improving the frequency of signal transmission.

It should be noted that, although the source driver is taken as an example in the present disclosure to describe the signal transmission method of the present disclosure, this does not have a limiting effect on the present disclosure, that is, the signal transmission method provided by the present disclosure is not only applied to the source driver, but also applied to any scenario in which signal transmission is performed in a cascade manner. Such as for typical Serial Peripheral Interface (SPI) daisy-chained signal transmission.

Fig. 2 illustrates a flow chart of a signal transmission method according to at least one embodiment of the present disclosure.

As shown in fig. 2, the signal transmission method includes steps S10 and S20. The signal transmission method is applied to a plurality of electronic devices in a cascade, each of the plurality of electronic devices having a corresponding sequencing number in the cascade, each of the plurality of electronic devices being in communication with a controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices.

Step S10: and enabling each electronic device to count based on the clock signal to obtain the current count value of the electronic device.

Step S20: the plurality of electronic devices are each caused to receive a portion corresponding to itself from the data stream in response to their current count value matching their own rank number.

For example, the signal transmission method shown in fig. 2 may be applied to the controller 102 and the source driver 101 described in fig. 1. For example, in the source driver 101, each source driver chip has a corresponding sort order number. In some embodiments of the present disclosure, for example, a sort number is written to each electronic device, so that each electronic device stores its own sort number in advance. In other embodiments of the present disclosure, the sequence number may be determined by each electronic device according to the obtained sequence indication signal, please refer to fig. 3 below.

For example, the master device SIC1 has a ranking number of 0 by default, the first slave device SIC2 has a ranking number of 1, and the second slave device SIC3 has a ranking number of 2.

The master device SIC1, the first slave device SIC2, and the second slave device SIC3 receive a clock signal and respective image data from the controller 102, respectively. For example, the data stream includes image data, and the master device SIC1, the first slave device SIC2, and the second slave device SIC3 receive RGB data of the master device, RGB data of the first slave device, and RGB data of the second slave device, respectively, from the controller 102.

The RGB data of the master device is used for display of the multi-column pixel unit 103, for example, the RGB data of the first slave device is used for display of the multi-column pixel unit 104, and the RGB data of the second slave device is used for display of the multi-column pixel unit 105.

In some embodiments of the present disclosure, the controller transmits the amount of data according to a clock signal, and each electronic device receives the data stream according to the clock signal. For example, the controller transmits 6 bits of image data per clock cycle, and each electronic device receives a partial data stream on the rising edge of the clock signal.

For step S10, each electronic device includes a counter for counting the period of the clock signal to obtain the current count value, for example. For example, the counter starts counting cycles of the clock signal in response to a count instruction. The count command is triggered, for example, when the controller starts providing a data stream to the source driver.

For example, the current count value indicates a length of time for which the controller provides the data stream to the source driver or a number of clock cycles for which.

In step S20, for example, the current count value matches the own sorting number, and a portion corresponding to itself is received from the data stream.

In other embodiments of the present disclosure, for example, each sort number corresponds to an expected count value, and each electronic device receives a portion corresponding to itself from the data stream when the current count value of each electronic device is consistent with the expected count value corresponding to the sort number of the electronic device.

For example, the sorting sequence number of a certain slave device SICi is i-1, the expected count value corresponding to the sorting sequence number i-1 is P, and when the current count value of the counter of the slave device SICi is P, the partial data stream provided by the controller is received, wherein i is an integer greater than 1, and P is an integer greater than 1.

The signal transmission method does not use a starting indication signal to prompt the electronic devices to receive partial data streams, but assigns a sequencing serial number to each electronic device in advance, counts clock signals and starts to receive the data streams when the current counting value is matched with the sequencing serial number. The signal transmission method ensures that the transmission of the data stream does not depend on the initial indication signal, thereby avoiding the influence caused by the delay of the initial indication signal in the transmission process and being beneficial to improving the frequency of signal transmission.

Fig. 3 is a flowchart illustrating another signal transmission method according to at least one embodiment of the disclosure.

As shown in fig. 3, the signal transmission method further includes a step S30 and a step S40 in addition to the step S10 and the step S20.

Step S30: the plurality of electronic devices are each caused to acquire the sequencing indication signal.

Step S40: and each electronic device determines the sequencing serial number of the electronic device according to the sequencing indication signal of the electronic device.

The method provides the sequencing serial number of each electronic device through the sequencing indication signal, so that the sequencing serial number of each electronic device can be flexibly adjusted and set.

For step S30, the sorting indication signal is used to indicate to each electronic device the sorting order of the electronic device in the cascade.

In some embodiments of the present disclosure, the sequencing indication signal comprises at least one pulse signal. For example, the number of pulse signals represents the sort order number. For example, 5 pulse signals represent a sequence number of 5.

In other embodiments of the present disclosure, the ordering indication signal may comprise, for example, a voltage signal. For example, different voltage values of the voltage signal represent different sequencing indication signals respectively. For example, a voltage value of 1V represents a sequence number of 1V.

In some embodiments of the present disclosure, for example, each electronic device is directly connected to an interface for providing a sequencing indication signal to directly obtain the sequencing indication signal from the interface.

In other embodiments of the present disclosure, for example, where the plurality of electronic devices includes a master device that is first arranged in the cascade and at least one slave device that is sequentially arranged in a bit subsequent to the master device in the cascade, step S30 includes: at least one slave device each obtains a sorting indication signal for the slave device from a previous device.

Fig. 4 illustrates a schematic diagram of each slave device acquiring a sorting indication signal from a device at a higher level according to at least one embodiment of the present disclosure.

As shown in fig. 4, the method provided by this embodiment is applied to the source driver 101 shown in fig. 1.

For example, the master device SIC1 provides the sorting indication signal PL1 to the first slave device SIC2 through its own start signal output port, and the first slave device SIC2 receives the sorting indication signal PL1 provided by the master device SIC1 through its own start signal input port. Next, the second slave device SIC3 acquires the sorting indication signal PL2 for the second slave device SIC3 from the first slave device SIC2, and so on, each slave device receiving the sorting indication signal from the previous device.

It should be noted that the ordering indication signal for each slave device is different, for example, the ordering indication signal PL1 for the first slave device SIC2 and the ordering indication signal PL2 for the second slave device SIC3 are different.

The method can utilize the initial signal input port and the initial signal output port of the source driving chip shown in fig. 1 to transmit the sequencing indication signal in a plurality of source driving chips, does not need to modify the hardware of the source driving chips, has good compatibility and is easy to realize.

For step S40, for example, if the sorting indication signal is at least one pulse signal, each electronic device may determine its own sorting number according to the number of the received at least one pulse signal. For another example, if the sorting indicator signal is a voltage signal, each electronic device may determine its own sorting number according to the voltage value of the received voltage signal.

Fig. 5 is a flowchart illustrating another signal transmission method according to at least one embodiment of the disclosure.

As shown in fig. 5, the signal transmission method further includes step S50 and step S60 in addition to step S10 to step S40.

Step S50: each electronic device of the current stage is caused to update the sorting indication signal of the electronic device of the current stage obtained from the device of the previous stage.

Step S60: and providing the updated sequencing indication signal for the next-stage electronic device in the cascade.

For step S50, the electronic device of the current stage is the electronic device to which the sorting indication signal is transferred. For example, in the example of fig. 4, the ordering indication signal PL1 is passed from the master device SIC1 to the first slave device SIC2, i.e. the first slave device SIC2 receives the ordering indication signal PL1, while the slave device arranged after the first slave device SIC2 has not received the ordering indication signal, when the electronic device at the present stage is the first slave device SIC2. For another example, the ordering indication signal is passed from the first slave device SIC2 to the second slave device SIC3, i.e., the second slave device SIC3 receives the ordering indication signal PL2 provided from the first slave device SIC2, while the slave device arranged after the second slave device SIC3 has not received the ordering indication signal, when the electronic device of the present stage is the second slave device SIC3.

For example, the electronic device at the present stage is the first slave device SIC2, and the first slave device SIC2 updates the sorting indication signal PL1 after receiving the sorting indication signal PL1 from the master device SIC 1. For example, the first slave device SIC2 updates the sorting indication signal PL1 to the sorting indication signal PL2.

In some embodiments of the present disclosure, the sequencing indication signal is, for example, at least one pulse signal, and step S50 includes incrementing each current stage electronic device by the number of the at least one pulse signal received from the previous stage device.

For example, each of the electronic devices of the current stage increments the number of at least one pulse signal received from the device of the previous stage by a step size. The step size may be 1, for example, and the number of pulse signals output from each electronic device at the current stage to the next stage is 1 added to the number of pulse signals received by the electronic device at the current stage.

For example, in the example of fig. 4, the electronic device at the present stage is the first slave device SIC2, the sorting indication signal PL1 received by the first slave device SIC2 from the master device SIC1 is 1 pulse signal, the first slave device SIC2 increases the number of pulse signals by step 1 by 2, and thus the sorting indication signal PL2 provided by the first slave device SIC2 to the second slave device SIC3 is 2 pulse signals.

The present disclosure does not limit the value of the step size, the step size of 1 is only an example, and a person skilled in the art can set the step size as needed.

If the sequencing indication signal is a voltage signal, each electronic device of the current stage may be incremented by the voltage value of the voltage signal received from the device of the previous stage.

For step S60, for example, the electronic device at the present stage is the first slave device SIC2, and after the first slave device SIC2 updates the sorting indication signal PL1 to the sorting indication signal PL2, the sorting indication signal PL2 is supplied to the electronic device at the next stage positioned after the first slave device SIC2, the second slave device SIC3.

Fig. 6 illustrates a flowchart of a method of step S20 in fig. 2 according to at least one embodiment of the present disclosure.

As shown in fig. 6, step S20 includes step S21 and step S22.

Step S21: and calculating the expected count value of the clock signal corresponding to each electronic device according to the self sequencing serial number of each electronic device.

Step S22: the plurality of electronic devices are each caused to receive a portion corresponding to itself from the data stream in response to its current count value coinciding with its expected count value.

The method can flexibly set the mapping relation between the sequencing sequence number and the expected count value according to the requirement, thereby having stronger applicability and being easy to realize.

For step S21, for example, a person skilled in the art may set a mapping relationship between the sorting order and the expected count value according to actual situations. For example, the mapping relationship is represented by a correspondence table, and the expected count value of the clock signal corresponding to each electronic device is determined by looking up the correspondence table. For another example, the mapping relationship is expressed in the form of a formula, and the expected count value of the clock signal corresponding to each electronic device is calculated by substituting the sorting number into the formula.

In some embodiments of the present disclosure, for example for a source driver, step S21 includes obtaining the number of data lanes, the number of low voltage differential signal line pairs, and the number of data input ports of the electronic device for each electronic device; and calculating an expected count value of the clock signal corresponding to each electronic device based on the sorting serial number, the number of the data channels, the number of the low-voltage differential signal line pairs and the number of the data input ports.

For example, the number of data lanes per electronic device is how many data lanes the electronic device provides data to other devices. For example, the electronic device is a source driver chip that provides image data to 960 columns of pixel cells, which may include 960 data channels, each of which provides image data to one column of pixel cells.

For example, each source driver chip is connected to the controller low voltage differential signal interface, and the low voltage differential signal interface of the source driver chip and the low voltage differential signal interface of the controller are connected by 3 low voltage differential signal line pairs or 6 low voltage differential signal line pairs. Each low-voltage differential signal line pair comprises two low-voltage differential signal lines which are respectively used for transmitting two complementary low-voltage differential signals, and image data are transmitted through the two complementary differential signals. For example, the Low Voltage Differential Signaling interface may be an LVDS (Low-Voltage Differential Signaling) interface, a mini-LVDS interface, or the like.

The number of data lanes per electronic device, the number of low voltage differential signal line pairs, and the number of data input ports of the electronic device are, for example, parameters inherent to the electronic device itself.

For example, the expected count value is calculated as follows:

CV＝(CN/IDP)×SSN/(P/NB)，

CV represents an expected count value, CN represents a number of data lanes, IDP represents a number of periodically processed data lanes, SSN represents a sort number, P represents a number of pairs of low voltage differential signal lines, and NB represents a number of data input ports of the electronic device.

For example, IDP means that data is periodically processed in several data channels. For example, it is defined inside the electronic device to process data with 6 data lanes and 1 clock cycle with 6 data lanes, i.e. to process data using 6 data lanes per clock cycle.

For example, the electronic device is a source driver, and the source driver includes 6 data input ports (ports), and the 6 data input ports are connected to the timing controller to receive image data from the timing controller.

For example, in the example of fig. 4, the number CN of data channels of each source driving chip is 960, the idp is 6, the controller and each source driving chip are connected by 6 low voltage differential signal pairs, NB is 6, the expected count value of the master device SIC1 is 0, the expected count value CV1 of the first slave device SIC2 = (960/6) × 1/(6/6) =160, and the expected count value CV1 of the second slave device SIC3 = (960/6) × 2/(6/6) =320.

Step S22: for example, each of the plurality of electronic devices receives a portion corresponding to itself from the data stream in response to its current count value coinciding with its expected count value.

The current count value is, for example, a count of clock cycles of a clock signal supplied from the controller to the source driver chip. For each electronic device, receiving a portion of the data stream provided by the controller is commenced in response to the current count value coinciding with the expected count value.

In some embodiments of the present disclosure, the sequence number of each source driving chip is acquired during a vertical blank period of scanning controlled by the timing controller.

In the display process of the display panel, the video and the animation are formed by combining a plurality of pictures which are sequentially displayed according to time sequence (for example, the frame rate is 60Hz or 120Hz, and the like), each picture is a frame, namely, one frame of image refers to a complete picture displayed by the display panel. During the display of one frame of image, the gate driver sequentially turns on each row of pixel units in the pixel array from the first row to the last row to scan, and during the scanning, the source driver inputs the data signals required by each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required by one frame of image. For example, due to the process of the pixel units of the display panel, the display screen needs to be continuously refreshed for obtaining a clear and complete display effect with good quality, each time the display screen needs to display one frame of image, and multiple frames of continuously displayed images form a static screen or a dynamic screen in visual effect. When the gate driver finishes scanning one frame of image, it is necessary to go back to the first row to start scanning a new frame. A Period from the end of scanning of the last line by the gate driver to the return to the first line is a Vertical Blanking Period (VBP). The one-Frame display period includes, for example, an image display period (Active Frame) and a vertical blanking period. During an image display period, for example, pixels in the pixel array display image data line by line, and during a vertical blanking period, preparation is made for display of image data of the next frame, without displaying image data.

The acquisition of the sorting order number by each source drive chip during the vertical blanking period does not affect the acquisition of image data during image display, and therefore does not affect image display, and is robust against electrostatic discharge noise.

In some embodiments of the present disclosure, the timing controller provides the display signal through the low voltage differential signal interface according to at least two modes, the display signal includes a plurality of display sub-signals, the at least two modes respectively provide the display sub-signals, the at least two modes include a line configuration mode and a frame configuration mode, the image data is provided in the line configuration mode during an image display period, and the frame configuration data is provided in at least the frame configuration mode during a vertical blank period.

For example, the display signal may include, for example, image data and configuration data. The configuration data includes, for example, row configuration data and frame configuration data. The row configuration data is used to configure the source drivers (i.e., the respective source drive chips) so that the source drivers output the row image data and timing control signals, etc. to the row of pixels in response to the row configuration data. The row configuration data includes, for example, a data polarity inversion control signal, a start signal of image data, and the like. The frame configuration data is used, for example, to configure the source driver (i.e., the respective source drive chip) so that the source driver outputs a control signal for the frame image. The frame configuration data may include, for example, a Gamma (Gamma) setting signal, an Amplification (AMP) offset control signal, a shift direction selection signal, and the like.

In some embodiments of the present disclosure, for example, the row configuration data and the frame configuration data of each source driver chip are the same. Since the timing controller can simultaneously provide the line configuration data and the frame configuration data to each source driving chip, each source driving chip is configured. Each source driver chip is hereinafter referred to as a source driver.

Fig. 7A and 7B are schematic signal formats of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure.

As shown in fig. 7A, in one frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 701 supplied in a line configuration mode, a display sub-signal 702 supplied in a frame configuration mode, and a display sub-signal 703 supplied in a correction configuration mode.

For example, the plurality of display sub-signals 701 are provided in a line configuration mode during image display, the display sub-signals 702 are provided in a frame configuration mode during vertical blanking, and the display sub-signals 703 are provided in a correction configuration mode.

As shown in fig. 7A, providing display signals to the source driver in at least two modes through the low voltage differential signal interface during one frame display period includes: and sequentially providing the display signals to the source driver in at least two modes by using the low voltage differential signal interface during one frame display period, and sequentially providing one or more display sub-signals to the source driver by using the low voltage differential signal interface for each mode.

For example, in the example of fig. 7A, the plurality of display sub-signals 701 are provided to the source driver in the row configuration mode, the display sub-signals 702 are provided to the source driver in the frame configuration mode, and the display sub-signals 703 are provided to the source driver in the correction configuration mode by using the low voltage differential signaling interface. For example, for a row configuration mode including a plurality of display sub-signals 701, the plurality of display sub-signals 701 are sequentially provided to the source driver using a low voltage differential signal interface. That is, in the example of fig. 7A, the plurality of display sub-signals 701 are provided to the source driver by using the low voltage differential signal interface, the display sub-signals 702 are provided to the source driver by using the low voltage differential signal interface, and the display sub-signals 703 are provided to the source driver by using the low voltage differential signal interface.

As shown in fig. 7A, each display sub-signal 701 provided in the line arrangement mode includes line data LPC and image data (e.g., RGB data). As shown in fig. 7B, the line data LPC includes a pattern recognition signal a and line configuration data. For example, the mode identification signal a includes a RESET signal RESET and a row mode Start signal LPC Start. For example, the row mode start signal may be a logic inactive level, e.g., "000". For the pattern identification signal and the row configuration data of the row configuration pattern, refer to the above description.

As shown in fig. 7A, each display sub-signal 702 supplied in the frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The display sub-signals provided in the frame configuration mode include data signals 712 provided in the power consumption control sub-mode. As shown in fig. 7B, the frame data FPC includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the frame data FPC is a RESET signal RESET and a frame pattern Start signal FPC Start. For example, the frame mode start signal may be different from the row mode start signal, e.g., a logic active level such as "111", to distinguish between the frame configuration mode and the row configuration mode. For the pattern recognition signal and the frame configuration data of the frame configuration pattern, refer to the above description.

As shown in fig. 7A, each display sub-signal 703 provided in the correction configuration mode includes correction data ASC. As shown in fig. 7B, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C may be, for example, a logic inactive level. For the correction signal, refer to the above description.

As shown in fig. 7A, after the display signal for one frame display period is transmitted to the source driver, the transmission of the display signal for the next frame display period to the source driver is continued.

As shown in fig. 7A, before each display sub signal is supplied to the source driver, a trigger signal PSI for notifying the source driver to perform a transfer operation for at least two modes is supplied to the source driver.

In some embodiments of the present disclosure, the controller may transmit the display signal to the source driver through a single mode in addition to transmitting the display signal to the source driver in at least two modes.

In this embodiment, the at least two modes of transmission operation performed by the source driver are informed by the trigger signal PSI, which facilitates the source driver and the controller to be compatible with other transmission operations besides the at least two modes of transmission operation, thereby providing compatibility. For example, a single mode transfer operation may be compatibly performed between the controller and the source driver in addition to the transfer operation through at least two modes. For example, the display signals that may be transmitted in at least two modes conform to a first signaling protocol, and the display signals that may also be transmitted to the source driver in a single mode conform to a second signaling protocol. If the controller and the source driver execute the transmission operation of at least two modes, the controller firstly provides a trigger signal PSI to the source driver as an indication signal of the transmission operation of at least two modes; if the controller and the source driver execute the single-mode transmission operation, the controller firstly provides a single-mode indication signal different from the trigger signal PSI to the source driver. The second signal transfer protocol may be some different protocol than the first signal transfer protocol, such as some transfer protocols in the related art. The multiplexing of the signal lines can be realized by setting the trigger signal, so that the chip has multiple functions, and the difficulty in popularization of the first signal transmission protocol is reduced.

In some embodiments of the present disclosure, a master source driver chip of the plurality of source driver chips provides an ordering indication signal to slave source drivers that are arranged in a cascade at a subsequent bit of the master source driver chip and adjacent to the master source driver chip in response to receiving the frame configuration data. The main source driving chip is a source driving chip arranged at the head in the cascade.

Fig. 7C illustrates a schematic diagram of transmitting a sequencing indication signal between a plurality of electronic devices provided by at least one embodiment of the present disclosure.

As shown in fig. 7C, the plurality of electronic devices are, for example, a plurality of cascaded master devices SIC1, first slave devices SIC2, second slave devices SIC3, and the like shown in fig. 4.

The electronic devices such as the master device SIC1, the first slave device SIC2, and the second slave device SIC3 are, for example, source driving chips. For example, each source driving chip and the timing controller are connected through a mini-LVDS interface.

In this example, the timing controller provides the display signal through the low voltage differential signal interface in at least two modes. The at least two modes include, for example, a line configuration mode in which image data is supplied during image display and a frame configuration mode in which frame configuration data is supplied at least during vertical blanking.

As shown in fig. 7C, in the frame configuration mode, after the controller provides the trigger signal PSI to each source driver chip, the controller provides the frame configuration data FPC to each source driver chip.

In the example of fig. 7C, the main device SIC1 is arranged at the head of the plurality of devices in cascade, and the main device SIC1 is a main source driving chip. The master device SIC1, i.e. the master source driver chip, transmits at least one pulse signal PL1 for the first slave device SIC2 to the first slave device SIC2 through the start signal output port EIO2 in response to receiving the frame configuration data FPC, e.g. at least one pulse signal PL1 contains 1 pulse. The first slave device SIC2 increments the number of the at least one pulse signal PL1 by a step size in response to receiving the at least one pulse signal PL1, and transmits the incremented at least one pulse signal PL2 to the second slave device SIC3 through its own start signal output port EIO2. As shown in fig. 7C, step size is 1 in this example, which facilitates the calculation. The second slave device SIC3 increments the number of the at least one pulse signal PL2 by a step size to obtain at least one pulse signal PL3 in response to receiving the at least one pulse signal PL2, and supplies the at least one pulse signal PL3 to a subsequent slave device through its own start signal output port EIO2.

At least one electronic device sequentially arranged at a subsequent bit of the second slave device SIC3 performs operations similar to the first slave device SIC2 and the second slave device SIC3, and detailed description thereof is omitted.

It should be noted that the present disclosure does not limit the number of the electronic devices, and although the number of the electronic devices is shown as 3 in the above embodiments, in practice, the number of the electronic devices may be more than, equal to, or less than 3.

Fig. 8 illustrates a schematic block diagram of a signal transmission apparatus 800 according to at least one embodiment of the present disclosure. The signal transmission apparatus 800 includes a plurality of electronic devices cascaded in a cascade, each of the plurality of electronic devices having a respective sequencing number in the cascade, each of the plurality of electronic devices in communication with a controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices.

For example, as shown in fig. 8, the signal transmission apparatus 800 includes a counting unit 810 and a receiving unit 820.

The counting unit 810 is configured to count the plurality of electronic devices each based on a clock signal.

The counting unit 810 may, for example, perform step S10 described in fig. 2.

The receiving unit 820 is configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting order number.

The receiving unit 820 may perform step S20 described in fig. 2, for example.

The signal transmission method ensures that the transmission of the data stream does not depend on the initial indication signal, thereby avoiding the influence caused by the delay of the initial indication signal in the transmission process and being beneficial to improving the frequency of signal transmission.

For example, the counting unit 810 and the receiving unit 820 may be hardware, software, firmware, or any feasible combination thereof. For example, the counting unit 810 and the receiving unit 820 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the signal transmission apparatus 800 corresponds to each step of the foregoing signal transmission method, and for the specific function of the signal transmission apparatus 800, reference may be made to the related description about the signal transmission method, which is not described herein again. The components and configuration of signal transmission device 800 shown in fig. 8 are exemplary only, and not limiting, and signal transmission device 800 may include other components and configurations as desired.

Fig. 9 illustrates a schematic block diagram of an electronic device 900 provided by at least one embodiment of the present disclosure. As shown in fig. 9, the electronic device 900 includes a controller 910 and a signal transmission device 920.

The signal transmission device 920 is, for example, a source driver. The signal transmission device 920 includes a plurality of electronic devices in a cascade, each of the plurality of electronic devices having a corresponding sorting number in the cascade. A plurality of electronic devices are each in communication with the controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices. The signal transmission device 920 includes: a counting unit configured to count each of the plurality of electronic devices based on the clock signal; a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting order number.

As shown in fig. 9, the electronic device 900 may also include a display panel 930.

The signal transmission device 920 performs, for example, the signal transmission method described above with respect to fig. 2. The display panel 930 is, for example, a liquid crystal display panel, and receives a driving signal (i.e., a gray scale voltage signal) supplied from the source driver 920 to display an image.

The electronic device 900 may be any of various electronic devices with image display functions, including but not limited to a smart phone, a tablet computer, a notebook computer, a display, a television, and the like.

The electronic equipment can enable the transmission of the data stream to be independent of the initial indication signal, thereby avoiding the influence caused by the delay of the initial indication signal in the transmission process and being beneficial to improving the frequency of signal transmission.

Although as described above, there are the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (16)

1. A signal transmission method for a plurality of electronic devices in a cascade, wherein each of the plurality of electronic devices has a corresponding sequencing number in the cascade, each of the plurality of electronic devices is in communication with a controller to receive a data stream and a clock signal from the controller, the data stream includes a plurality of portions corresponding to the plurality of electronic devices,

the method comprises the following steps:

enabling the plurality of electronic devices to count based on the clock signal to obtain current count values of the electronic devices;

causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its current count value matching its own sorting sequence number.

2. The method of claim 1, further comprising:

causing each of the plurality of electronic devices to acquire a sequencing indication signal; and

and each electronic device determines the sequencing serial number of the electronic device according to the sequencing indication signal of the electronic device.

3. The method of claim 2, wherein the plurality of electronic devices includes a master device that is first ranked in the cascade and at least one slave device that is sequentially ranked in the cascade subsequent to the master device,

causing each of the plurality of electronic devices to acquire the sequencing indication signal comprises:

the at least one slave device each obtains the ordering indication signal for each slave device from a previous device.

4. The method of claim 3, further comprising:

enabling each electronic device at the current stage to update the sequencing indication signal of the electronic device at the current stage obtained from the electronic device at the previous stage; and

providing the updated ordering indication signal for the next-stage electronic device in the cascade.

5. The method of claim 4, wherein the sequencing indication signal comprises at least one pulse signal.

6. The method of claim 5, wherein each electronic device determines its own ranking number according to its own ranking indication signal, comprising:

and each electronic device determines the sequencing serial number of the electronic device according to the number of the received at least one pulse signal.

7. The method of claim 6, wherein causing each current stage electronic device to update the ranking indication signal obtained from a previous stage device for the current stage electronic device comprises:

each current stage electronic device is incremented by the number of the at least one pulse signal received from the previous stage device.

8. The method of claim 1, wherein causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its current count value matching its own sorting sequence number comprises:

acquiring an expected count value of a clock signal corresponding to each electronic device according to the self sequencing serial number of each electronic device; and

causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its current count value coinciding with its expected count value.

9. The method of claim 8, wherein each electronic device is connected to the controller by a low voltage differential signal line pair,

obtaining an expected count value of a clock signal corresponding to each electronic device according to the sequencing serial number of each electronic device, including:

acquiring the number of data channels of each electronic device, the number of low-voltage differential signal line pairs and the number of data input ports of the electronic device; and

calculating the expected count value of the clock signal corresponding to each electronic device based on the sorting sequence number, the number of the data channels, the number of the low-voltage differential signal line pairs and the number of the data input ports.

10. The method of claim 9, wherein the expected count value is calculated as follows:

CV＝(CN/IDP)×SSN/(P/NB)，

wherein CV represents the expected count value, CN represents the number of data lanes, IDP represents the number of periodically processed data lanes, SSN represents the sequencing number, P represents the number of low voltage differential signal line pairs, and NB represents the number of data input ports of the electronic device.

11. The method of any of claims 1-10, wherein the plurality of electronic devices comprise a plurality of source driver chips, the controller comprises a timing controller, and the data stream comprises image data.

12. The method of claim 11, wherein the sequence number of each source driving chip is acquired during a vertical blank period of the scan controlled by the timing controller.

13. The method of claim 12, wherein the timing controller provides a display signal through a low voltage differential signal interface in at least two modes, the display signal including a plurality of display sub-signals, the at least two modes providing the display sub-signals, respectively,

the at least two modes include a row configuration mode and a frame configuration mode,

providing the image data in the line configuration mode during display of an image,

providing frame configuration data in at least the frame configuration mode during the vertical blanking interval.

14. The method of claim 13, wherein a master source driver chip of the plurality of source driver chips provides the ordering indication signal to slave source driver chips that are next-in-sequence to and adjacent to the master source driver chip in the cascade in response to receiving the frame configuration data,

wherein the main source driver is a source driver chip arranged at the head in the cascade.

15. A signal transmission arrangement comprising a plurality of electronic devices in a cascade, wherein each of the plurality of electronic devices has a respective sequencing number in the cascade, wherein each of the plurality of electronic devices is in communication with a controller to receive a data stream and a clock signal from the controller, wherein the data stream comprises a plurality of portions corresponding to the plurality of electronic devices,

the device comprises:

a counting unit configured to cause each of the plurality of electronic devices to count based on the clock signal;

a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting order number.

16. An electronic device, comprising:

a controller; and

a signal transmission arrangement comprising a plurality of electronic devices in a cascade, wherein each of the plurality of electronic devices has a respective sequencing number in the cascade, each of the plurality of electronic devices in communication with the controller to receive a data stream and a clock signal from the controller, the data stream comprising a plurality of portions corresponding to the plurality of electronic devices,

the signal transmission device includes:

a counting unit configured to count each of the plurality of electronic devices based on the clock signal;

a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to its own current count value matching its own sorting order number.

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