JP6990516B2 - Pixel data writing method and image display device - Google Patents

Description

The present invention relates to a pixel data writing method and an image display device capable of extending the data writing time and reliably writing data.

In recent years, in a display panel, an RGBW display panel having a W (white) sub-pixel in addition to the usual R (red), G (green), and B (blue) sub-pixels has been used. Then, by adding W to the sub-pixel, it is possible to improve the brightness and suppress the power consumption. For example, Patent Document 1 discloses a display device using an RGBW panel.

Korean Publication No. 10-2011-0077899

The resolution is increasing from FHD (Full HD) to UHD (Ultra HD) 4K, and the refresh cycle of images is also required to be faster. Along with this, the data writing time in the RGBW display panel is also becoming shorter. In this case, the drive of the sub-gate line may be insufficient and the data writing may be uncertain.

Therefore, an object of the present invention is to provide a pixel data writing method and an image display device capable of extending the data writing time and reliably writing data even if the refresh cycle is short.

In order to solve the above-mentioned problems and achieve the object, the pixel data writing method in the present invention has four types of sub-pixels, and a set of two types of sub-pixels among the four types of sub-pixels is used. A display panel in which two types of sub-pixel sets that are connected to different sub-gate lines and different from the two types of sub-pixel sets that are connected to the sub-gate line are connected to different data lines, and the four types of RGBW. A data drive unit that generates a data voltage for displaying the sub-pixels of the above and applies the data voltage to the data line, and a gate signal for writing the data voltage applied to the data line to the four types of sub-pixels is applied to the sub-gate line. In an image display device comprising a gate drive unit and having at least three sub-gate lines, a separate gate signal is applied to the sub-gate lines, and the data voltage applied to the data lines is the four types. It includes writing to the sub-pixel and simultaneously applying the same gate signal to the sub-gate line and writing the data voltage applied to the data line to the four types of sub-pixels, and is applied to the data line. The number of times the data voltage is written to the four types of sub-pixels is less than the number of times the sub-gate lines are written.

Further, in one embodiment of the present invention, when the total number of the sub-gate lines is 6 × n (n is an integer), a separate gate signal is applied to at least n of the sub-gate lines, and the data line is used. The data voltage applied to the four types of sub-pixels is written to the four types of sub-pixels, and the same gate signal is simultaneously applied to at least 2 × n lines of the sub-gate lines, and the data voltage applied to the data lines is the four types. It is characterized by writing to the sub-pixel of and including.

Further, one embodiment of the present invention is characterized in that a separate gate signal is applied to 2 × n lines of the sub-gate line.

Further, one embodiment of the present invention is characterized in that a separate gate signal is applied to 3 × n lines of the sub-gate line.

Further, one embodiment of the present invention is characterized in that the same gate signal is applied to 3 × n lines of the sub gate line.

Further, one embodiment of the present invention is characterized in that zero is applied as a data voltage to the data line corresponding to the sub-gate line to which the same gate signal is applied.

Further, one embodiment of the present invention is characterized in that the sub-gate line to which the same gate signal is applied is changed for each pixel frame as the sub-gate line to which a separate gate signal is applied.

Further, one embodiment of the present invention is characterized in that the time for writing the data voltage applied to the data line to the four types of sub-pixels is 1.5 times.

Further, in one embodiment of the present invention, when the display panel has (3840 × 3) columns × 2160 rows = 8,294,400 × 3 sub-pixels and the refresh period is 120 Hz, the data lines. It is characterized in that the time for applying the data voltage applied to one of the sub-gate lines is about 2.9 μs.

Further, in one embodiment of the present invention, the four types of sub-pixels are four types of sub-pixels of R (red), G (green), B (blue), and W (white). do.

Further, the image display device in the present invention has four types of sub-pixels, and a set of two types of sub-pixels among the four types of sub-pixels is connected to different sub-gate lines and the sub-gate line. A display panel in which a set of two types of sub-pixels different from the set of two types of sub-pixels connected to is connected to different data lines, and a data voltage for displaying the four types of sub-pixels of RGBW are generated and data is generated. In an image display device including a data drive unit that applies data to a line and a gate drive unit that applies a gate signal for writing a data voltage applied to the data line to the four types of sub-pixels to the sub-gate line. The gate drive unit applies a gate signal to all of the sub-gate lines less than the total number of the sub-gate lines, and writes the data voltage applied to the data lines to the four types of sub-pixels. It is characterized by that.

Further, in one embodiment of the present invention, the gate drive unit is characterized by being composed of a plurality of D-type flip-flops and a plurality of OR gates.

Further, in one embodiment of the present invention, the plurality of D-type flip-flops function as shift registers.

Further, in one embodiment of the present invention, the gate driving unit is characterized in that the same gate signal is applied to an arbitrary number of sub-gate lines among the sub-gate lines.

Further, in one embodiment of the present invention, the data driving unit is characterized in that zero is applied as a data voltage to the data lines corresponding to the arbitrary number of sub-gate lines.

Further, in one embodiment of the present invention, the gate driving unit is characterized in that an arbitrary number of sub-gate lines to which the same gate signal is applied are changed for each pixel frame.

Further, in one embodiment of the present invention, when the total number of the sub-gate lines is 6 × n (n is an integer), the number of the sub-gate lines to which the same gate signal is applied is 3 × n (n is an integer). ) It is characterized by being a book.

Further, in one embodiment of the present invention, a gate signal is applied to all of the sub-gate lines at a number of times corresponding to 4 × n (n is an integer), and the data voltages applied to the data lines are the four types. It is characterized by writing to the sub-pixel of.

Further, one embodiment of the present invention is characterized in that the time for writing the data voltage applied to the data line to the four types of sub-pixels is 1.5 times.

Further, in one embodiment of the present invention, when the display panel has (3840 × 3) columns × 2160 rows = 8,294,400 × 3 sub-pixels and the refresh period is 120 Hz, the data lines. It is characterized in that the time for applying the data voltage applied to one of the sub-gate lines is about 2.9 μs.

Further, in one embodiment of the present invention, the four types of sub-pixels are four types of sub-pixels of R (red), G (green), B (blue), and W (white). do.

According to the present invention, since the data writing time can be extended, it is possible to write reliable data, and it is possible to prevent deterioration of the display image quality.

It is a block diagram of the image display device which concerns on 1st Embodiment. It is a figure which shows the structure of the gate drive part. It is a figure explaining the case where the sub-gate line is driven in order in the Nth frame, and the sub-pixel data is sequentially written in each sub-pixel. In the Nth frame, it is a figure explaining the method that the image display apparatus which concerns on this Embodiment performs the zigzag-shaped interlace writing, and writes the sub-pixel data to each sub-pixel. It is a figure explaining the method that the image display apparatus which concerns on this embodiment performs the zigzag-shaped interlace writing in the N + 1th frame, and writes the sub-pixel data to each sub-pixel. It is a block diagram of the image display device which concerns on 2nd Embodiment. It is a figure which shows the structure of the gate drive part which concerns on 2nd Embodiment. It is a figure explaining the method of performing the normal interlace writing by the image display apparatus which concerns on this Embodiment in the Nth frame, and writing the sub-pixel data to each sub-pixel. It is a figure explaining the method which the image display apparatus which concerns on this Embodiment performs the normal interlace writing in the N + 1th frame, and writes the sub-pixel data to each sub-pixel.

Hereinafter, the pixel data writing method and the embodiment for implementing the image display device according to the present invention will be described with reference to the accompanying drawings.

The objectives, advantages and novel features of the present invention will become more apparent from the following detailed description associated with the accompanying drawings. In different drawings, the same reference numerals are used to indicate the same or functionally similar elements. Please understand that the drawings are schematic and the scale of the drawings is not accurate.

(First Embodiment)
The first embodiment will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of an image display device according to the first embodiment. As shown in FIG. 1, the image display device 1 includes a display panel 2, a grayscale voltage generator 3, a signal control unit 4, a data drive unit 5, a gate drive unit 6, and a backlight unit 7.

The display panel 2 displays an RGB image. The display panel 2 has a plurality of sub-gate lines GLn, a to GLn + 5, b for receiving a gate signal (scanning signal) from the gate drive unit 6, and a plurality of data lines DLm to receive data voltage from the data drive unit 5. Includes DLm + 5. The sub-gate lines GLn, a to GLn + 5, b extend in the column direction substantially parallel to each other, and the data lines DLm to DLm + 5 extend in the row direction substantially parallel to each other.

Further, the display panel 2 is connected to the sub-gate lines GLn, a to GLn + 5 and the data lines DLm to DLm + 5, and includes a plurality of sub-pixels arranged in a matrix. For the sake of the present invention, the display panel 2 is premised on having 12 columns × 6 rows = 72 sub-pixels, but in reality, it has a 4K resolution (3840 × 3) columns × 2160. Rows = 8,294,400 × 3 sub-pixels or more sub-pixels may be provided. The display panel 2 includes four types of sub-pixels, R (red), G (green), B (blue), and W (white).

In the present embodiment, the four types of sub-pixels are arranged in the order of WRGB in the first row and in the order of GBWR in the second row. The third line is arranged in the order of WRGB again, and the same arrangement is repeated thereafter. It should be noted that this arrangement is arbitrary, and it is sufficient that the four types of WRGB sub-pixels are cyclically arranged. The display panel 2 can be applied to any display regardless of an LCD display, an OLED display, or the like, as long as it has a specification in which four types of WRGB sub-pixels are arranged.

The display panel 2 includes a switching element TR. The sub-pixels {W, G} and the sub-pixels {R, B} have sub-gate lines GLn, a to GLn + 5, b that are different for each sub-pixel pair of the sub-pixels {W, G} and the sub-pixels {R, B}. , Connected via the switching element TR. For example, the sub-gate pixels {W, G} are connected to the sub-gate lines GLn, a via the switching element TR, and the sub-pixels {R, B} are connected to the gate lines GLn, b via the switching element TR. It is connected. Further, in the display panel 2, the sub-pixels {W, R} and {G, B} share the data lines DLm to DLm + 5, respectively, and each sub-pixel shares the data lines DLm to DLm + 5 via the switching element TR. Is connected to. For example, the data line DLm is connected to the sub-pixels {W, R} via the switching element TR, and the data line DLm + 1 is connected to the sub-pixels {G, B} via the switching element TR. Therefore, the display panel 2 has twice the number of gate lines (secondary gate lines) as compared with the normal RGBW display panel, while the number of data lines is halved as compared with the normal RGBW display panel. ..

The grayscale voltage generator 3 generates an all grayscale voltage corresponding to all grayscales that can be represented by each subpixel, or a reference grayscale voltage corresponding to a part of all grayscales.

The signal control unit 4 controls the operations of the data drive unit 5, the gate drive unit 6, and the backlight unit 7. The signal control unit 4 receives an input video signal RGB and an input control signal for controlling the display of the input video signal RGB from an external graphic controller (not shown).

The input image signal RGB contains information on the luminance of each sub-pixel, which can be represented, for example, in a grayscale of 4096 ⁽ 214). The input control signal includes a vertical sync signal VSYNC, a horizontal sync signal HSYNC, a main clock signal MCLK, and a data enable signal DE.

The signal control unit 4 processes the input video signal RGB and the input video signal RGB based on the input control signal so as to meet the operating conditions of the display panel 2, and the video signal DATA, the gate control signal CONT1, and Generates the data control signal CONT2. The gate control signal CONT1 is supplied to the gate drive unit 6, and the data control signal CONT2 and the video signal DATA are supplied to the data drive unit 5.

The gate control signal CONT1 includes a scan start signal instructing the start of the scan operation and at least one clock signal for controlling the output period of the gate-on voltage. The gate control signal CONT1 may further include an output enable signal that limits the duration of the gate-on voltage.

The data control signal CONT2 has a horizontal start time for notifying the data drive unit 5 of the start of transmission of the image signal DATA to the row of sub-pixels, and a load for instructing the application of the data voltage to the data lines DLm to DLm + 5. It may include a signal. The data control signal CONT2 may further include an inverting signal RVS for inverting the polarity of the data voltage with respect to the common voltage.

The data drive unit 5 is connected to the data lines DLm to DLm + 5 of the display panel 2, receives the video signal DATA, selects the gray scale voltage corresponding to the video signal DATA, generates an analog data voltage, and generates the data line DLm. It is applied to ~ DLm + 5. However, when the grayscale voltage generator 3 supplies the reference grayscale voltage to the data drive unit 5, the data drive unit 5 divides the reference grayscale voltage to generate a desired data voltage.

The gate drive unit 6 is connected to the sub-gate lines GLn, a to GLn + 5, b of the display panel 2, and applies a gate signal including a combination of a gate-on voltage and a gate-off voltage to each sub-gate line. Then, when displaying an image, a gate-on voltage is applied to the sub-gate lines GLn, a to GLn + 5, b of the display panel 2 according to the gate control signal CONT1 transmitted from the signal control unit 4, and the sub-gate line GLn. , A to GLn + 5, b, the switching element TR connected to is turned on. The data voltage applied to the data lines DLm to DLm + 5 via the turned-on switching element TR is applied to each sub-pixel WRGB.

By repeating these operations in units of one horizontal period (which coincides with one period of the horizontal synchronization signal HSYNC and the data enable signal DE), the gate-on voltage is reduced to all the sub-gate lines GLn, a to GLn + 5,. A frame of image is displayed by sequentially applying the data voltage to b and applying the data voltage to all the sub-pixels WRGB.

FIG. 2 is a diagram showing the configuration of the gate drive unit 6. In this figure, among the functions of the gate drive unit 6, only the part related to the on (turn-on of the switching element TR) of the sub-gate lines GLn, a to GLn + 5, b related to the present invention is shown. As shown in FIG. 2, the gate drive unit 6 is composed of a plurality of D-type flip-flops (D-FF (A to P)) and a plurality of OR gates 8 (A to L). The plurality of D-FFs (A to P) function as shift registers. The method of writing data using the gate drive unit 6 is hereinafter referred to as a zigzag-shaped interlaced writing method.

Next, the operation of the gate drive unit 6 will be described in detail below. Consider the case where the sub-gate lines GLn, a to GLn + 5, b are turned on in the Nth frame. First, the control signal from CTL0 and the rising clock signal from CK0 are input to D-FF (A). As a result, the output of D-FF (A) becomes H. The output H of the D-FF (A) is input to the OR gate 8 (A). As a result, the output of the OR gate 8 (A) becomes H, and the sub-gate lines GLn and a are turned on.

Next, the output H of the D-FF (A) and the clock signal of the next rising edge from the CK0 are input to the D-FF (B). As a result, the output of D-FF (B) becomes H. The output H of the D-FF (B) is input to the OR gate 8 (B). The output of the OR gate 8 (B) becomes H, and the sub-gate lines GLn + 1, b are turned on.

Next, the output H of the D-FF (B) and the clock signal of the next rising edge from the CK0 are input to the D-FF (C). As a result, the output of D-FF (C) becomes H. The output H of the D-FF (C) is input to the OR gate 8 (C). The output of the OR gate 8 (C) becomes H, and the sub-gate line GLn + 2, a is turned on.

Next, the output H of the D-FF (C) and the clock signal of the next rising edge from the CK0 are input to the D-FF (D). As a result, the output of D-FF (D) becomes H. The output H of the D-FF (D) is simultaneously input to the OR gate 8 (D), the OR gate 8 (E), and the OR gate 8 (F). The outputs of the OR gate 8 (D), the OR gate 8 (E), and the OR gate 8 (F) are H, and the sub-gate lines GLn, b, GLn + 1, a, and GLn + 2, b are turned on at the same time.

Hereinafter, similarly, the sub-gate lines GLn + 3, b, GLn + 4, a, GLn + 5, b are turned on in sequence, and then the sub-gate lines GLn + 3, a, GLn + 4, b, GLn + 5, a are turned on at the same time.

Further, consider the case where the sub-gate lines GLn, a to GLn + 5, b are turned on in the N + 1th frame. First, the control signal from CTL1 and the rising clock signal from CK1 are input to D-FF (E). As a result, the output of D-FF (E) becomes H. The output H of the D-FF (E) is input to the OR gate 8 (D). As a result, the output of the OR gate 8 (D) becomes H, and the sub-gate lines GLn and b are turned on.

Next, the output H of the D-FF (E) and the clock signal of the next rising edge from the CK1 are input to the D-FF (F). As a result, the output of D-FF (F) becomes H. The output H of the D-FF (F) is input to the OR gate 8 (E). The output of the OR gate 8 (E) becomes H, and the sub-gate lines GLn + 1, a are turned on.

Next, the output H of the D-FF (F) and the clock signal of the next rising edge from the CK1 are input to the D-FF (G). As a result, the output of D-FF (G) becomes H. The output H of the D-FF (G) is input to the OR gate 8 (F). The output of the OR gate 8 (F) becomes H, and the sub-gate line GLn + 2, b is turned on.

Next, the output H of the D-FF (G) and the clock signal of the next rising edge from the CK1 are input to the D-FF (H). As a result, the output of D-FF (H) becomes H. The output H of the D-FF (H) is simultaneously input to the OR gate 8 (A), the OR gate 8 (B), and the OR gate 8 (C). The outputs of the OR gate 8 (A), the OR gate 8 (B), and the OR gate 8 (C) are H, and the sub-gate lines GLn, a, GLn + 1, b, and GLn + 2, a are turned on at the same time.

Hereinafter, similarly, the sub gate lines GLn + 3, a, GLn + 4, b, GLn + 5, a are sequentially turned on, and then the sub gate lines GLn + 3, b, GLn + 4, a, GLn + 5, b are turned on at the same time.

Therefore, the gate drive unit 6 turns on the sub-gate lines GLn, a to GLn + 5, b at eight clock timings per frame. A method of writing pixel data by a zigzag-shaped interlaced writing method using the gate drive unit 6 will be described in detail later.

The backlight unit 7 supplies light to the display panel 2. The backlight unit 7 includes a backlight (not shown) that supplies light to the display panel 2 and an inverter (not shown) that supplies current to the backlight. The inverter drive signal can be synchronized with the image synchronization signal.

The signal control unit 4, the data drive unit 5, and the gate drive unit 6 may be mounted directly on the display panel 2 in the form of at least one IC chip, or may be mounted directly on the display panel 2 in the form of a tape carrier package (TCP). It may be mounted on a flexible printed circuit film (not shown) attached to. Further, the signal control unit 4, the data drive unit 5, and the gate drive unit 6 may be mounted on another printed circuit board (not shown).

Further, the data drive unit 5 and the gate drive unit 6 are integrated on the display panel 2 together with the data lines DLm to DLm + 5, the sub-gate lines GLn, a to GLn + 5, b, and the switching element TR by the thin film process. It may be converted. The signal control unit 4, the data drive unit 5, and the gate drive unit 6 may be integrated in the form of a single chip. At least one of the signal control unit 4, the data drive unit 5, and the gate drive unit 6, or a circuit element including the signal control unit 4, a circuit element including the data drive unit 5, and the gate drive unit 6. The including circuit element may be provided outside a single chip.

(Pixel data writing method)
In the image display device 1 according to the present embodiment, as described above, the display panel 2 shares the data lines DLm to DLm + 5 with the sub-pixels of {W, R} and {G, B}, respectively. Each sub-pixel is connected to the data lines DLm to DLm + 5 via the switching element TR. Therefore, the display panel 2 is composed of half the number of data lines as compared with a normal RGBW display panel.

When the image display device 1 according to the present embodiment does not have the configuration of the gate drive unit 6 described with reference to FIG. 2, the sub-gate lines are driven in the order of GLn, a to GLn + 5, b, and each of them is driven in this order. Sub-pixel data is written to the sub-pixel. Hereinafter, a method of driving the sub-gate lines in order and writing the sub-pixel data to each sub-pixel in order will be described. FIG. 3 is a diagram illustrating a case where sub-gate lines are sequentially driven in the Nth frame and sub-pixel data is sequentially written to each sub-pixel. In FIG. 3, “−” represents the sub-pixel data written in the N-1 frame.

In the Nth frame, the following 12 steps are required to write the sub-pixel data to all the sub-pixels.
-First step: Driving the sub-gate lines GLn, a, and writing data to the sub-pixels {W, G} in the first line via the data lines DLm to DLm + 5.
-Second step: Driving the sub-gate lines GLn and b, and writing data to the sub-pixels {R, B} in the first line via the data lines DLm to DLm + 5.
-Third step: Driving the sub-gate lines GLn + 1, a, and writing data to the sub-pixels {W, G} in the second line via the data lines DLm to DLm + 5.
-Fourth step: Driving the sub-gate lines GLn + 1 and b, and writing data to the sub-pixels {R, B} in the second line via the data lines DLm to DLm + 5.
Fifth step: Driving the sub-gate line GLn + 2, a and writing data to the sub-pixel {W, G} in the third line via the data lines DLm to DLm + 5.
-Sixth step: Driving the sub-gate line GLn + 2, b and writing data to the sub-pixel {R, B} in the third line via the data lines DLm to DLm + 5.
7th step: Driving the sub gate line GLn + 3, a and writing data to the sub pixel {W, G} on the 4th line via the data lines DLm to DLm + 5.
Eighth step: Driving the sub-gate line GLn + 3, b and writing data to the sub-pixel {R, B} on the fourth line via the data lines DLm to DLm + 5.
9th step: Driving the sub gate line GLn + 4, a and writing data to the sub pixel {W, G} on the fifth line via the data lines DLm to DLm + 5.
10th step: Driving the sub-gate line GLn + 4, b and writing data to the sub-pixel {R, B} on the fifth line via the data lines DLm to DLm + 5.
11th step: Driving the sub-gate line GLn + 5, a and writing data to the sub-pixel {W, G} on the 6th line via the data lines DLm to DLm + 5.
12th step: Driving the sub-gate line GLn + 5, b and writing data to the sub-pixel {R, B} on the 6th line via the data lines DLm to DLm + 5.

This ends the writing operation of the Nth frame. Then, in the subsequent frames (N + 1, N + 2, ...), the above-mentioned 12 steps are repeated. On the other hand, a type that has a gate line instead of a sub-gate line, has six lines, which is half of the sub-gate line, and has sub-pixels {W, R, G, B} connected to each gate line. In the RGBW display panel, it is possible to write sub-pixel data to all sub-pixels in half of 6 steps. Therefore, the RGBW display panel of the type provided with 12 sub-gate lines has a shorter time for writing data by 1/2 as compared with the RGBW display panel of the type provided with 6 gate lines. Instead, the number of data lines can be reduced from 12 to 6, so the number of external data driver ICs can be reduced, and costs can be reduced by downsizing the PCB and reducing the number of T-CONT pins. It is possible. As for the data drive unit, since it is configured by GIP (Gate-in-Panel), there is no problem such as cost increase.

(Zigzag-shaped interlaced writing method)
As mentioned above, the resolution is increasing from FHD (Full HD) to UHD (Ultra HD) 4K. Therefore, the refresh cycle of the image is also required to be increased, specifically, from 60 Hz to 120 Hz, and therefore the data writing time in the RGBW display panel is also becoming shorter. Specifically, the time that can be spent for writing per sub-gate line is very short, about 1.9 μs in the case of 4K resolution and a refresh period of 120 Hz. In this case, the drive of the sub-gate line may be insufficient and the data writing may be uncertain.

On the other hand, the image display device 1 according to the present embodiment has the configuration of the gate drive unit 6 described with reference to FIG. 2, performs zigzag-shaped interlace writing, and writes sub-pixel data to each sub-pixel. The zigzag-shaped interlaced writing method will be described below. FIG. 4 is a diagram illustrating a method in which the image display device 1 according to the present embodiment performs zigzag-shaped interlaced writing in the Nth frame and writes sub-pixel data to each sub-pixel. In FIG. 4, “−” represents the sub-pixel data written in the N-1 frame.

In the Nth frame, the following eight steps are required to write the sub-pixel data to all the sub-pixels.
-First step: Driving the sub-gate lines GLn, a, and writing data to the sub-pixels {W, G} in the first line via the data lines DLm to DLm + 5.
-Second step: Driving the sub-gate lines GLn + 1 and b, and writing data to the sub-pixels {R, B} in the second line via the data lines DLm to DLm + 5.
-Third step: Driving the sub-gate line GLn + 2, a and writing data to the sub-pixel {W, G} in the third line via the data lines DLm to DLm + 5.
-Fourth step: Simultaneous drive of sub-gate lines GLn, b, GLn + 1, a, and GLn + 2, b, and sub-pixels {R, B} in the first line via data lines DLm to DLm + 5, second line. Writing of data "0" to the sub-pixels {W, G} and the sub-pixels {R, B} in the third row.
Fifth step: Driving the sub-gate line GLn + 3, b and writing data to the sub-pixel {R, B} on the fourth line via the data lines DLm to DLm + 5.
-Sixth step: Driving the sub-gate line GLn + 4, a and writing data to the sub-pixel {W, G} on the fifth line via the data lines DLm to DLm + 5.
7th step: Driving the sub-gate line GLn + 5, b and writing data to the sub-pixel {R, B} on the 6th line via the data lines DLm to DLm + 5.
Eighth step: Simultaneous drive of sub-gate lines GLn + 3, a, GLn + 4, b, and GLn + 5, a, and sub-pixels {W, G} in the fourth line via data lines DLm to DLm + 5, fifth line. Writing of data "0" to the sub-pixels {R, B} and the sub-pixels {W, G} in the third row.
This ends the writing operation of the Nth frame.

In the image display device 1 according to the present embodiment, sub-pixel data is written to each sub-pixel in eight steps. Therefore, the sub-gate line is driven in the order of GLn, a to GLn + 5, b, and the writing step is 8/12 = 2 /, as compared with the case where the sub-pixel data is written to each sub-pixel in 12 steps. It decreases by 3. As a result, the data writing time per time can be extended by 3/2 = 1.5 times, and the time that can be spent for writing per sub-gate line is about 1.9 μs in the case of 4K and 120 Hz. → It is about 2.9 μs, and it is possible to prevent writing problems.

In the present invention, the data writing time is extended by thinning out the number of sub-pixels for which data is written in each frame in units of sub-gate lines. However, if the data of the previous frame remains in the sub-pixels that have not been written, false colors will be derived at the edges of the objects and textures in the displayed image, and the lines will be broken, resulting in deterioration of the display image quality. .. Therefore, in the present invention, after writing to a plurality of sub-gate lines in a plurality of lines, "0" data is simultaneously written to the plurality of sub-gate lines that were not written in the line, thereby causing image deterioration. I'm preventing it.

On the other hand, in the N + 1th frame, the sub-gate line, that is, the sub-pixel that normally writes data in the N-th frame, and the sub-gate line, that is, the sub-pixel that collectively writes “0” data at the same time are exchanged to perform the same writing operation. conduct. FIG. 5 is a diagram illustrating a method in which the image display device 1 according to the present embodiment performs zigzag-shaped interlaced writing in the N + 1th frame and writes sub-pixel data to each sub-pixel. In FIG. 5, “−” represents pixel data written in the N frame.

In the N + 1th frame, the following eight steps are required to write the sub-pixel data to all the sub-pixels.
-First step: Driving the sub-gate lines GLn and b, and writing data to the sub-pixels {R, B} in the first line via the data lines DLm to DLm + 5.
-Second step: Driving the sub-gate lines GLn + 1, a, and writing data to the sub-pixels {W, G} in the second line via the data lines DLm to DLm + 5.
-Third step: Driving the sub-gate line GLn + 2, b and writing data to the sub-pixel {R, B} in the third line via the data lines DLm to DLm + 5.
-Fourth step: Simultaneous drive of sub-gate lines GLn, a, GLn + 1, b, and GLn + 2, a, and sub-pixels {W, G} in the first line via data lines DLm to DLm + 5, second line. Writing of data "0" to the sub-pixels {R, B} and the sub-pixels {W, G} in the third row.
Fifth step: Driving the sub-gate line GLn + 3, a and writing data to the sub-pixel {W, G} in the fourth line via the data lines DLm to DLm + 5.
-Sixth step: Driving the sub-gate line GLn + 4, b and writing data to the sub-pixel {R, B} on the fifth line via the data lines DLm to DLm + 5.
7th step: Driving the sub-gate line GLn + 5, a and writing data to the sub-pixel {W, G} on the 6th line via the data lines DLm to DLm + 5.
Eighth step: Simultaneous drive of sub-gate lines GLn + 3, b, GLn + 4, a, and GLn + 5, b, and sub-pixels {R, B} in the fourth line via data lines DLm to DLm + 5, fifth line. Writing of data "0" to the sub-pixels {W, G} and the sub-pixels {R, B} on the third row.
This ends the writing operation of the N + 1th frame.

In this way, in the Nth frame and the N + 1th frame, the sub-gate line, that is, the sub-pixel that performs normal data writing, and the sub-gate line, that is, the sub-pixel that collectively writes “0” data at the same time are exchanged to perform the writing operation. Thereby, image deterioration can be prevented.

According to the first embodiment, in an image display device having four types of RGBW sub-pixels, a set of two types of sub-pixels out of the four types of sub-pixels is connected to different sub-gate lines, and By connecting two types of sub-pixel sets that are different from the two types of sub-pixel sets that are connected to the sub-gate lines to different data lines, the number of gate lines (sub-gate lines) is the same as that of a normal RGBW display panel. Even if the number of data lines is double that of a normal RGBW display panel and the number of data lines is half that of a normal RGBW display panel, the number of times pixel data is written can be reduced to extend the data writing time per time. Therefore, it is possible to write reliable data. As a result, deterioration of display image quality can be prevented.

(Second embodiment)
Next, a second embodiment of the image display device according to the present invention will be described. In the second embodiment described below, the same reference numerals are given in the drawings to the configurations common to those of the first embodiment, and the description thereof will be omitted. In the second embodiment, the order in which the data is written is different from that in the first embodiment, and this is realized by making the configuration of the gate line driver different.

FIG. 6 is a block diagram of the image display device according to the second embodiment. As shown in FIG. 2, the image display device 11 includes a display panel 2, a grayscale voltage generator 3, a signal control unit 4, a data drive unit 5, a gate drive unit 16, and a backlight unit 7.

The display panel 2 displays an RGB image. The display panel 2 has a plurality of sub-gate lines GLn, a to GLn + 5, b for receiving a gate signal (scanning signal) from the gate drive unit 6, and a plurality of data lines DLm to receive data voltage from the data drive unit 5. Includes DLm + 5. The sub-gate lines GLn, a to GLn + 5, b extend in the row direction substantially parallel to each other, and the data lines DLm to DLm + 5 extend in the column direction substantially parallel to each other.

Further, the display panel 2 is connected to the sub-gate lines GLn, a to GLn + 5 and the data lines DLm to DLm + 5, and includes a plurality of sub-pixels arranged in a matrix. The display panel 2 includes four types of sub-pixels, R (red), G (green), B (blue), and W (white).

The display panel 2 includes a switching element TR. The sub-pixels {W, G} and the sub-pixels {R, B} have sub-gate lines GLn, a to GLn + 5, b that are different for each sub-pixel pair of the sub-pixels {W, G} and the sub-pixels {R, B}. , Connected via the switching element TR. Further, in the display panel 2, the sub-pixels {W, R} and {G, B} share the data lines DLm to DLm + 5, respectively, and each sub-pixel shares the data lines DLm to DLm + 5 via the switching element TR. Is connected to. Therefore, the display panel 2 has twice the number of gate lines (secondary gate lines) as compared with the normal RGBW display panel, while the number of data lines is halved as compared with the normal RGBW display panel. ..

The grayscale voltage generator 3 generates an all grayscale voltage corresponding to all grayscales that can be represented by each subpixel, or a reference grayscale voltage corresponding to a part of all grayscales.

The signal control unit 4 controls the operations of the data drive unit 5, the gate drive unit 6, and the backlight unit 7. The signal control unit 4 receives an input video signal RGB and an input control signal for controlling the display of the input video signal RGB from an external graphic controller (not shown), and based on these signals, the video signal DATA, The gate control signal CONT1 and the data control signal CONT2 are generated.

The data drive unit 5 is connected to the data lines DLm to DLm + 5 of the display panel 2, receives the video signal DATA, selects the gray scale voltage corresponding to the video signal DATA, generates an analog data voltage, and generates the data line DLm. It is applied to ~ DLm + 5. However, when the grayscale voltage generator 3 supplies the reference grayscale voltage to the data drive unit 5, the data drive unit 5 divides the reference grayscale voltage to generate a desired data voltage.

The backlight unit 7 supplies light to the display panel 2.

The gate drive unit 16 is connected to the sub-gate lines GLn, a to GLn + 5, b of the display panel 2, and applies a gate signal including a combination of a gate-on voltage and a gate-off voltage to each sub-gate line. Then, when displaying an image, a gate-on voltage is applied to the sub-gate lines GLn, a to GLn + 5, b of the display panel 2 according to the gate control signal CONT1 transmitted from the signal control unit 4, and the sub-gate line GLn. , A to GLn + 5, b, the switching element TR connected to is turned on. The data voltage applied to the data lines DLm to DLm + 5 via the turned-on switching element TR is applied to each sub-pixel WRGB.

FIG. 7 is a diagram showing the configuration of the gate drive unit 16. The circuit configuration of the gate drive unit 16 is the same as that of the gate drive unit 6 according to the first embodiment, but the correspondence between each output and the sub gate line is different. In this figure, among the functions of the gate drive unit 16, only the part related to the on (turn-on of the switching element TR) of the sub-gate lines GLn, a to GLn + 5, b related to the present invention is shown. As shown in FIG. 7, the gate drive unit 6 is composed of a plurality of D-type flip-flops (D-FF (A to P)) and a plurality of OR gates 8 (A to L). The plurality of D-FFs (A to P) function as shift registers. The method of writing data using the gate drive unit 16 is hereinafter referred to as a normal interlaced writing method.

Next, the operation of the gate drive unit 16 will be described in detail below. Consider the case where the sub-gate lines GLn, a to GLn + 5, b are turned on in the Nth frame. First, the control signal from CTL0 and the rising clock signal from CK0 are input to D-FF (A). As a result, the output of D-FF (A) becomes H. The output H of the D-FF (A) is input to the OR gate 8 (A). As a result, the output of the OR gate 8 (A) becomes H, and the sub-gate lines GLn and a are turned on.

Next, the output H of the D-FF (A) and the clock signal of the next rising edge from the CK0 are input to the D-FF (B). As a result, the output of D-FF (B) becomes H. The output H of the D-FF (B) is input to the OR gate 8 (B). The output of the OR gate 8 (B) becomes H, and the sub-gate lines GLn and b are turned on.

Next, the output H of the D-FF (B) and the clock signal of the next rising edge from the CK0 are input to the D-FF (C). As a result, the output of D-FF (C) becomes H. The output H of the D-FF (C) is input to the OR gate 8 (C). The output of the OR gate 8 (C) becomes H, and the sub-gate line GLn + 2, a is turned on.

Next, the output H of the D-FF (C) and the clock signal of the next rising edge from the CK0 are input to the D-FF (D). As a result, the output of D-FF (D) becomes H. The output H of the D-FF (D) is simultaneously input to the OR gate 8 (D), the OR gate 8 (E), and the OR gate 8 (F). The outputs of the OR gate 8 (D), the OR gate 8 (E), and the OR gate 8 (F) are H, and the sub-gate lines GLn + 1, a, GLn + 1, b, and GLn + 3, a are turned on at the same time.

Hereinafter, similarly, the sub-gate lines GLn + 2, b, GLn + 4, a, GLn + 4, b are sequentially turned on, and then the sub-gate lines GLn + 3, b, GLn + 5, a, GLn + 5, b are turned on at the same time.

Further, consider the case where the sub-gate lines GLn, a to GLn + 5, b are turned on in the N + 1th frame. First, the control signal from CTL1 and the rising clock signal from CK1 are input to D-FF (E). As a result, the output of D-FF (E) becomes H. The output H of the D-FF (E) is input to the OR gate 8 (D). As a result, the output of the OR gate 8 (D) becomes H, and the sub-gate lines GLn + 1, a are turned on.

Next, the output H of the D-FF (E) and the clock signal of the next rising edge from the CK1 are input to the D-FF (F). As a result, the output of D-FF (F) becomes H. The output H of the D-FF (F) is input to the OR gate 8 (E). The output of the OR gate 8 (E) becomes H, and the sub-gate lines GLn + 1, b are turned on.

Next, the output H of the D-FF (F) and the clock signal of the next rising edge from the CK1 are input to the D-FF (G). As a result, the output of D-FF (G) becomes H. The output H of the D-FF (G) is input to the OR gate 8 (F). The output of the OR gate 8 (F) becomes H, and the sub-gate line GLn + 3, a is turned on.

Next, the output H of the D-FF (G) and the clock signal of the next rising edge from the CK1 are input to the D-FF (H). As a result, the output of D-FF (H) becomes H. The output H of the D-FF (H) is simultaneously input to the OR gate 8 (A), the OR gate 8 (B), and the OR gate 8 (C). The outputs of the OR gate 8 (A), the OR gate 8 (B), and the OR gate 8 (C) are H, and the sub-gate lines GLn, a, GLn, b, and GLn + 2, a are turned on at the same time.

Hereinafter, similarly, the sub gate lines GLn + 3, b, GLn + 5, a, GLn + 5, b are sequentially turned on, and then the sub gate lines GLn + 2, b, GLn + 4, a, GLn + 4, b are turned on at the same time.

Therefore, the gate drive unit 16 turns on the sub-gate lines GLn, a to GLn + 5, b at eight clock timings per frame.

(Normal interlaced writing method)
The image display device 11 according to the present embodiment has the configuration of the gate drive unit 16 described with reference to FIG. 7, performs normal interlace writing, and writes sub-pixel data to each sub-pixel. The normal interlaced writing method will be described below. FIG. 8 is a diagram illustrating a method in which the image display device 11 according to the present embodiment performs normal interlaced writing in the Nth frame and writes sub-pixel data to each sub-pixel. In FIG. 8, “−” represents the sub-pixel data written in the N-1 frame.

In the Nth frame, the following eight steps are required to write the sub-pixel data to all the sub-pixels.
-First step: Driving the sub-gate lines GLn, a, and writing data to the sub-pixels {W, G} in the first line via the data lines DLm to DLm + 5.
-Second step: Driving the sub-gate lines GLn and b, and writing data to the sub-pixels {R, B} in the first line via the data lines DLm to DLm + 5.
-Third step: Driving the sub-gate line GLn + 2, a and writing data to the sub-pixel {W, G} in the third line via the data lines DLm to DLm + 5.
-Fourth step: Simultaneous drive of sub-gate lines GLn + 1, a, GLn + 1, b, and GLn + 3, a, and sub-pixels in the second line via data lines DLm to DLm + 5 {W, R, G, B} , And the writing of data "0" to the sub-pixel {W, G} on the 4th line.
Fifth step: Driving the sub-gate line GLn + 2, b and writing data to the sub-pixel {R, B} in the third line via the data lines DLm to DLm + 5.
-Sixth step: Driving the sub-gate line GLn + 4, a and writing data to the sub-pixel {W, G} on the fifth line via the data lines DLm to DLm + 5.
7th step: Driving the sub-gate line GLn + 4, b and writing data to the sub-pixel {R, B} on the 5th line via the data lines DLm to DLm + 5.
Eighth step: Simultaneous drive of sub-gate lines GLn + 3, b, GLn + 5, a, and GLn + 5, b, and sub-pixels {R, B} in the fourth row via data lines DLm to DLm + 5, and 6 Writing data "0" to the sub-pixels {W, R, G, B} on the line.
This ends the writing operation of the Nth frame.

In the image display device 11 according to the present embodiment, sub-pixel data is written to each sub-pixel in eight steps. Therefore, the sub-gate line is driven in the order of GLn, a to GLn + 5, b, and the writing step is 8/12 = 2 /, as compared with the case where the sub-pixel data is written to each sub-pixel in 12 steps. It decreases by 3. As a result, the data writing time per one time can be extended by 3/2 = 1.5 times, and the time that can be spent for writing per sub-gate line is about 1.9 μs in the case of 4K and 120 Hz. → It becomes about 2.9 μs, and it is possible to prevent a writing defect.

In the present invention, the data writing time is extended by thinning out the number of sub-pixels for which data is written in each frame in units of sub-gate lines. However, if the data of the previous frame remains in the sub-pixels that have not been written, false colors will be derived at the edges of the objects and textures in the displayed image, and the lines will be broken, resulting in deterioration of the display image quality. .. Therefore, in the present invention, after writing to a plurality of sub-gate lines in a plurality of lines, "0" data is simultaneously written to the plurality of sub-gate lines that were not written in the line, thereby causing image deterioration. I'm preventing it.

On the other hand, in the N + 1th frame, the sub-gate line, that is, the sub-pixel that normally writes data in the N-th frame, and the sub-gate line, that is, the sub-pixel that collectively writes “0” data at the same time are exchanged to perform the same writing operation. conduct. FIG. 9 is a diagram illustrating a method in which the image display device 1 according to the present embodiment performs normal interlace writing in the N + 1th frame and writes sub-pixel data to each sub-pixel. In FIG. 9, “−” represents the sub-pixel data written in the N frame.

In the N + 1th frame, the following eight steps are required to write the sub-pixel data to all the sub-pixels.
-First step: Driving the sub-gate lines GLn + 1, a, and writing data to the sub-pixels {W, G} in the second line via the data lines DLm to DLm + 5.
-Second step: Driving the sub-gate lines GLn + 1 and b, and writing data to the sub-pixels {R, B} in the second line via the data lines DLm to DLm + 5.
-Third step: Driving the sub-gate line GLn + 3, a and writing data to the sub-pixel {W, G} on the fourth line via the data lines DLm to DLm + 5.
Fourth step: Simultaneous drive of sub-gate lines GLn, a, GLn, b, and GLn + 2, a, and sub-pixels {W, R, G, B} in the first line via data lines DLm to DLm + 5. , And the writing of data "0" to the sub-pixels {W, G} on the third line.
Fifth step: Driving the sub-gate line GLn + 3, b and writing data to the sub-pixel {R, B} on the fourth line via the data lines DLm to DLm + 5.
-Sixth step: Driving the sub-gate line GLn + 5, a and writing data to the sub-pixel {W, G} on the sixth line via the data lines DLm to DLm + 5.
7th step: Driving the sub-gate line GLn + 5, b and writing data to the sub-pixel {R, B} on the 6th line via the data lines DLm to DLm + 5.
Eighth step: Simultaneous drive of sub-gate lines GLn + 2, b, GLn + 4, a, and GLn + 4, b, and sub-pixels {R, B} in the third row via data lines DLm to DLm + 5, and 5 Writing data "0" to the sub-pixels {W, R, G, B} on the line.
This ends the writing operation of the N + 1th frame.

In this way, in the Nth frame and the N + 1th frame, the sub-gate line, that is, the sub-pixel that performs normal data writing, and the sub-gate line, that is, the sub-pixel that collectively writes “0” data at the same time are exchanged to perform the writing operation. Thereby, image deterioration can be prevented.

According to the second embodiment, although the configuration of the communication gate drive unit is different from that of the first embodiment, the image display device having four types of RGBW sub-pixels is similar to the first embodiment. In, of the four types of sub-pixels, two types of sub-pixels that are different from the set of two types of sub-pixels that connect the set of two types of sub-pixels to different sub-gate lines and connect to the sub-gate line. By connecting these pairs to different data lines, the number of gate lines (secondary gate lines) is double that of a normal RGBW display panel, and the number of data lines is half that of a normal RGBW display panel. Even if this is the case, by reducing the number of times the pixel data is written, the data writing time per time can be extended, so that reliable data writing becomes possible. As a result, deterioration of display image quality can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, various modifications and uniform embodiments are possible from now on as long as the person has ordinary knowledge in the art.

In the image display apparatus according to the first and second embodiments, in order to gate on the six sub-gate lines, individual gate-on signals are sequentially applied to the three sub-gate lines, and the individual data applied to the data lines. By sequentially applying voltage, applying the same gate-on signal to the three sub-gate lines, and applying zero as the data voltage to the three data lines, the pixels on the display panel 2 while maintaining the level of display image quality. The number of times data is written is reduced by 2/3. However, the ratio of the number of sub-gate lines to which the same gate-on signal is applied to the number of sub-gate lines to which individual gate-on signals are applied is not limited to this. The ratio of the number of sub-gate lines to which the individual gate-on signals are applied and the number of sub-gate lines to which the same gate-on signals are applied can be arbitrarily changed as long as the image quality of the displayed image is satisfied with the required level. For example, it is possible to apply an individual gate-on signal to one sub-gate line and further apply the same gate-on signal to two sub-gate lines.

Furthermore, it is possible to arbitrarily change the ratio of the number of times an individual gate-on signal is applied to the sub-gate line and the number of times the same gate-on signal is applied to the sub-gate line by inserting a dummy processing step. Is.

Therefore, the scope of rights of the present invention is not limited to this, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the claims are also included in the present invention.

1, 11 Image display device 2 Display panel 3 Grayscale voltage generator 4 Signal control unit 5 Data drive unit 6, 16 Gate drive unit 7 Backlight unit 8 OR gate TR switching element D-FF

Claims (21)

It has four types of sub-pixels, and of the four types of sub-pixels, a set of two types of sub-pixels is connected to a different sub-gate line and a set of two types of sub-pixels connected to the sub-gate line. A display panel in which a set of two types of sub-pixels different from the above is connected to different data lines, a data drive unit that generates a data voltage for displaying the four types of sub-pixels and applies the data voltage to the data line, and the data line. In an image display device comprising a gate drive unit for applying a gate signal for writing a data voltage applied to the four types of sub-pixels to the sub-gate line, and having at least three sub-gate lines.
A separate gate signal is applied to the sub-gate line, and the data voltage applied to the data line is written to the four types of sub-pixels.
After that, the same gate signal is simultaneously applied to the sub-gate line, and the data voltage applied to the data line is written to the four types of sub-pixels.
Including
A pixel data writing method in which the number of times the data voltage applied to the data line is written to the four types of sub-pixels is less than the total number of the sub-gate lines. When the total number of sub-gate lines is 6 × n (n is an integer),
A separate gate signal is applied to at least n of the sub-gate lines, and the data voltage applied to the data line is written to the four types of sub-pixels.
The same gate signal is simultaneously applied to at least 2 × n sub-gate lines, and the data voltage applied to the data line is written to the four types of sub-pixels.
The pixel data writing method according to claim 1. The pixel data writing method according to claim 2, wherein a separate gate signal is applied to 2 × n of the sub-gate lines. The pixel data writing method according to claim 2, wherein a separate gate signal is applied to 3 × n sub-gate lines. The pixel data writing method according to claim 4, wherein the same gate signal is simultaneously applied to 3 × n lines of the sub-gate line. The pixel data writing method according to any one of claims 1 to 5, wherein zero is applied as a data voltage to the data line corresponding to the sub-gate line to which the same gate signal is applied. The pixel data writing method according to any one of claims 1 to 6, wherein the sub-gate line to which the same gate signal is applied is changed for each pixel frame as the sub-gate line to which a separate gate signal is applied. The pixel data writing method according to any one of claims 5 to 7, wherein the time for writing the data voltage applied to the data line to the four types of sub-pixels is 1.5 times. When the display panel has (3840 × 3) columns × 2160 rows = 8,294,400 × 3 of the sub-pixels and the refresh period is 120 Hz, the data voltage applied to the data line is used as the sub-gate. The pixel data writing method according to any one of claims 5 to 8, wherein the time applied to one line is about 2.9 μs. The pixel according to any one of claims 1 to 9, wherein the four types of sub-pixels are four types of sub-pixels of R (red), G (green), B (blue), and W (white). Data writing method. It has four types of sub-pixels, and of the four types of sub-pixels, a set of two types of sub-pixels is connected to a different sub-gate line and a set of two types of sub-pixels connected to the sub-gate line. A display panel in which two different sets of sub-pixels are connected to different data lines,
A data drive unit that generates a data voltage that displays the four types of sub-pixels and applies it to the data line.
A gate drive unit that applies a gate signal for writing the data voltage applied to the data line to the four types of sub-pixels to the sub-gate line, and a gate drive unit.
In an image display device equipped with
The gate drive unit applies a gate signal to all of the sub-gate lines at a number of times less than the total number of the sub-gate lines, and writes the data voltage applied to the data lines to the four types of sub-pixels. Display device. The image display device according to claim 11, wherein the gate drive unit is composed of a plurality of D-type flip-flops and a plurality of OR gates. The image display device according to claim 12, wherein the plurality of D-type flip-flops function as shift registers. The image display device according to any one of claims 11 to 13, wherein the gate drive unit simultaneously applies the same gate signal to an arbitrary number of sub-gate lines among the sub-gate lines. The image display device according to claim 14, wherein the data drive unit applies zero as a data voltage to the data lines corresponding to the arbitrary number of sub-gate lines. The image display device according to claim 14, wherein the gate drive unit changes an arbitrary number of sub-gate lines to which the same gate signal is applied for each pixel frame. When the total number of the sub-gate lines is 6 × n (n is an integer), the number of the sub-gate lines to which the same gate signal is applied is 3 × n (n is an integer), claims 14 to 16. The image display device according to any one of the above. 17. The image display device described. The image display device according to claim 17, wherein the time for writing the data voltage applied to the data line to the four types of sub-pixels is 1.5 times. When the display panel has (3840 × 3) columns × 2160 rows = 8,294,400 × 3 of the sub-pixels and the refresh period is 120 Hz, the data voltage applied to the data lines is used as the sub-gate. The image display device according to any one of claims 17 to 19, wherein the time applied to one wire is about 2.9 μs. The image according to any one of claims 12 to 20, wherein the four types of sub-pixels are four types of sub-pixels of R (red), G (green), B (blue), and W (white). Display device.

Images