CN114636919A - Multi-gradient attenuation test system and method for PCIE (peripheral component interface express) differential signal link and electronic equipment - Google Patents

Abstract

The invention provides a system and a method for testing multi-gradient attenuation of a PCIE differential signal link and electronic equipment, relating to the technical field of chip testing and comprising an upper computer, a testing mother board and a plurality of attenuation daughter boards; according to the multi-gradient attenuation test system for the PCIE differential signal link, provided by the invention, a multi-channel and multi-gradient attenuation link can be built in a mode of combining the mother board and the daughter board, the test mother board leads out a differential signal line of a PCIE control chip to be tested, the design of an attenuation loop is transferred to the attenuation daughter board, and the switching of different attenuation gradients is realized by replacing the attenuation daughter board inserted into the daughter board slot. Compared with the multi-gradient attenuation design of using a chip test special board to complete a PCIE differential signal link, the test system provided by the invention can effectively reduce the PCB design difficulty and shorten the chip test period, thereby quickly responding to the user requirement, and the multiplexing of the attenuation daughter board can further reduce the test cost.

Description

Multi-gradient decay test system, method and electronic device for PCIE differential signal link

technical field

The invention relates to the technical field of chip testing, in particular to a multi-gradient attenuation testing system, method and electronic device for a PCIE differential signal link.

Background technique

The PCIE (Peripheral Component Interface Express, high-speed peripheral component interconnection) control chip has two types of pins: TX sending and RX receiving. In practical applications, there are many kinds of link attenuation between the TX sending end and the RX receiving end of the PCIE control chip. If possible, in order to test the performance of the PCIE control chip under different attenuations, as shown in Figure 1, a peripheral loopback (loopback) attenuation loop is established to realize that the differential signal in the PCIE control chip is sent from the TX pin (pin), Then enter the loopback (loopback) attenuation loop, and finally receive the differential signal returned by the RX pin (pin), and determine the performance of the PCIE control chip by analyzing the quality of the received differential signal.

In the current attenuation loop design of PCIE links, an independent chip test board is usually designed for each attenuation gradient of each PCIE control chip. However, the manufacturing cost of the chip test board is high and the design is difficult, resulting in a long test cycle. , unable to quickly respond to the user's testing needs.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a multi-gradient decay test system, method and electronic device for a PCIE differential signal link, so as to shorten the period of the multi-gradient decay test of the differential signal link of the PCIE control chip and reduce the test cost.

In a first aspect, the present invention provides a multi-gradient attenuation test system for a PCIE differential signal link, including: a host computer, a test motherboard and a plurality of attenuation daughter boards; wherein, the test motherboard is provided with a PCIE control to be tested Chip and sub-board slots, each of the attenuation sub-boards can be movably plugged into the sub-board slots; each of the attenuation sub-boards is used to provide a preset insertion loss; the host computer and the The PCIE control chip to be tested is connected; the differential transmitting end of the PCIE control chip to be tested is connected to the differential receiving end of the sub-board slot in a one-to-one correspondence; the test input end of each attenuation sub-board is connected to the sub-board The differential receiving end of the board slot is in one-to-one correspondence; the differential receiving end of the PCIE control chip to be tested is connected to the differential transmitting end of the sub-board slot in a one-to-one correspondence; the test output end of each attenuation sub-board is connected to the The differential sending ends of the sub-board slots are in one-to-one correspondence; the host computer is used to send a test command to the PCIE control chip to be tested, so that the PCIE control chip to be tested enters the test mode; the PCIE to be tested The control chip is used to output the first test signal through its own differential transmitting end in the test mode, and receive the second test signal returned by its own differential receiving end, and send the identification information of the AC parameter of the second test signal to the the host computer; wherein, the second test signal is the return signal of the first test signal after passing through the target attenuating sub-board currently plugged into the sub-board slot; the host computer is used for based on the AC The identification information of the parameter determines the performance index of the PCIE control chip to be tested under the target insertion loss; wherein the target insertion loss is the insertion loss provided by the target attenuation sub-board.

In an optional implementation manner, the attenuation sub-board includes: N+1 attenuation links; the N+1 attenuation links include: a calibration link and N test links; the calibration link The input end of the test link is connected with the calibration input end of the sub-board slot, and the output end of the calibration link is connected with the calibration output end of the sub-board slot; the input end of each test link is connected with the calibration output end of the sub-board slot. The test input ends of the attenuator sub-board are connected correspondingly, and the output end of each test link is correspondingly connected with the test output end of the attenuator sub-board.

In an optional implementation manner, each attenuation chain includes: a first-stage attenuator and a second-stage attenuator; the input end of the first-stage attenuator is connected to the input end of the attenuating chain , the output end of the first-stage attenuator is connected to the input end of the second-stage attenuator, and the output end of the second-stage attenuator is connected to the output end of the attenuation chain.

In an optional implementation manner, the first-stage attenuator includes: a first π-type attenuator or a first T-type attenuator; the second-stage attenuator includes: a second π-type attenuator or a second T-type attenuator type attenuator.

In an optional embodiment, the insertion loss of the first-stage attenuator is not greater than 3dB.

In an optional implementation manner, the Nyquist frequency of the transmission signal supported by the test motherboard and each of the attenuation sub-boards is 16 GHz.

In an optional implementation manner, the resonance frequency of the resistors in the first-stage attenuator and the second-stage attenuator is not less than twice the Nyquist frequency of the transmission signal of the PCIE control chip to be tested.

In a second aspect, the present invention provides a multi-gradient attenuation test method for a PCIE differential signal link, which is applied to the multi-gradient attenuation test system for a PCIE differential signal link according to any one of the foregoing embodiments. The method includes: : send a test command to the PCIE control chip to be tested, so that the PCIE control chip to be tested enters the test mode; receive the identification information of the AC parameter of the second test signal returned by the PCIE control chip to be tested, and based on the communication The identification information of the parameter determines the performance index of the PCIE control chip to be tested under the target insertion loss; wherein, the second test signal is the output of the PCIE control chip to be tested through its own differential transmission terminal in the test mode. A test signal, the return signal after passing through the target attenuating sub-board currently plugged into the sub-board slot; the target insertion loss is the insertion loss provided by the target attenuating sub-board.

In an optional implementation manner, before sending the test command to the PCIE control chip to be tested, the method further includes: sending a calibration signal to the calibration input terminal of the sub-board slot, and receiving a calibration signal of the sub-board slot Calibrate the feedback signal of the output end; determine whether the S-parameter of the calibration link of the target attenuation sub-board meets the preset attenuation standard based on the calibration signal and the feedback signal; if it is determined to meet the preset attenuation standard, send the test command to PCIE control chip to be tested.

In a third aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor implements the above embodiments when the processor executes the computer program The steps of any one of the methods.

In a fourth aspect, the present invention provides a computer-readable medium having non-volatile program code executable by a processor, the program code causing the processor to perform the method of any one of the preceding embodiments.

The multi-gradient attenuation test system of the PCIE differential signal link provided by the present invention includes: a host computer, a test motherboard and a plurality of attenuation sub-boards; wherein, the test motherboard is provided with a PCIE control chip to be tested and a sub-board slot, each Each attenuation sub-board can be movably plugged into the sub-board slot; each attenuation sub-board is used to provide a preset insertion loss; the host computer is connected to the PCIE control chip to be tested; the differential transmission end of the PCIE control chip to be tested One-to-one connection with the differential receiving end of the daughter board slot; the test input terminal of each attenuating daughter board corresponds to the differential receiving end of the daughter board slot one-to-one; the differential receiving end of the PCIE control chip to be tested and the daughter board slot The differential transmitters of the sub-boards are connected in one-to-one correspondence; the test output of each attenuation sub-board corresponds to the differential transmitter of the sub-board slot one-to-one; the host computer is used to send test commands to the PCIE control chip to be tested, so that the PCIE to be tested is The control chip enters the test mode; the PCIE control chip to be tested is used to output the first test signal through its own differential transmitting end in the test mode, and receive the second test signal returned by its own differential receiving end, and convert the AC parameters of the second test signal The identification information is sent to the host computer; wherein, the second test signal is the return signal of the first test signal after the target attenuation sub-board currently inserted in the sub-board slot; the host computer is used to determine the identification information based on the AC parameters The performance index of the PCIE control chip to be tested under the target insertion loss; the target insertion loss is the insertion loss provided by the target attenuation sub-board.

The multi-gradient attenuation test system of the PCIE differential signal link provided by the present invention can build a multi-channel and multi-gradient attenuation link by combining the motherboard and the daughter board, and the test motherboard leads out the differential signal of the PCIE control chip to be tested. The design of the attenuation circuit is transferred to the attenuation sub-board, and the switching of different attenuation gradients is realized by replacing the attenuation sub-board plugged in the sub-board slot. Compared with using a special chip test board to complete the multi-gradient attenuation design of the PCIE differential signal link, the test system provided by the present invention can effectively reduce the difficulty of PCB design and shorten the chip test cycle, thereby quickly responding to user requirements, and the attenuator Board reuse can further reduce test costs.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

1 is a schematic diagram of an attenuation loop for performing an attenuation test on a PCIE control chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of using Polar SI software to estimate the corresponding routing line length of -5dB attenuation provided by an embodiment of the present invention;

3 is a system schematic diagram of a multi-gradient attenuation test system for a PCIE differential signal link provided by an embodiment of the present invention;

FIG. 4 is a schematic layout diagram of an attenuation sub-board according to an embodiment of the present invention;

5 is a schematic diagram of a design of a single attenuation link using a π-type passive attenuation network according to an embodiment of the present invention;

6 is a schematic diagram of a π-type attenuation network provided by an embodiment of the present invention;

7 is a flowchart of a multi-gradient attenuation test method for a PCIE differential signal link provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of an electronic device according to an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

The multi-gradient attenuation design of the traditional PCIE differential signal link is generally based on the transmission line theory, and is realized by lengthening the routing (winding) length of the signal line; for example, PCIE Gen5 (Generation Fifth) 16GHz/differential 85 ohm impedance , the multi-attenuation gradients to be tested include: -5dB, -10dB, -15dB, -20dB, -25dB, etc. Figure 2 is a schematic diagram of using the Polar SI software to estimate the -5dB attenuation corresponding to the routing (winding) line length, using the classic 5Mil The line width and 5Mil Spacing (1OZ ounce copper thickness) differential 85 ohm impedance design, the estimated line lengths are: insertion loss = -5dB corresponding line length is approximately equal to "7000Mil"; insertion loss = -10dB corresponding line length It is approximately equal to "14000Mil"; the line length corresponding to insertion loss = -15dB is approximately equal to "21000Mil"; the line length corresponding to insertion loss = -20dB is approximately equal to "28000Mil"; the line length corresponding to insertion loss = -25dB is approximately equal to "35000Mil" . Among them, 1Mil (Mil)=0.0254MM mm.

Obviously, "7000Mil", "14000Mil", "21000Mil", "28000Mil", "35000Mil" and other signal lines are relatively long and require a lot of layout (layout) space for routing (routing); so simply rely on lengthening the signal It is difficult to achieve multi-gradient and multi-lane (that is, multi-channel, for example, x8 Lane/x16Lane) attenuation sub-board-level designs, especially in DUT chips x16 or x32-bit PCIE Lane (channel) case. In the current attenuation loop design of PCIE links, an independent chip test board is usually designed for each attenuation gradient of each PCIE control chip. However, the manufacturing cost of the chip test board is high and the design is difficult, resulting in a long test cycle. , unable to quickly respond to the user's testing needs. In view of this, an embodiment of the present invention provides a multi-gradient attenuation test system for a PCIE differential signal link, so as to alleviate the technical problems raised above.

Example 1

FIG. 3 is a system schematic diagram of a multi-gradient attenuation test system for a PCIE differential signal link provided by an embodiment of the present invention. As shown in FIG. 3, the multi-gradient attenuation test system includes: a host computer 100, a test motherboard 200, and a multi-gradient attenuation test system. Attenuation sub-boards 300 (only one attenuation sub-board is shown in FIG. 3 ); wherein, the test motherboard is provided with a PCIE control chip 400 to be tested and a sub-board slot 500, and each attenuation sub-board can be movably plugged into the sub-board slot; each attenuator daughter board is used to provide a preset insertion loss.

The host computer is connected with the PCIE control chip to be tested; the differential sending end of the PCIE control chip to be tested is connected to the differential receiving end of the sub-board slot in a one-to-one correspondence; the test input end of each attenuating sub-board is connected to the differential of the sub-board slot. One-to-one correspondence at the receiving end.

The differential receiving end of the PCIE control chip to be tested is connected to the differential transmitting end of the sub-board slot in one-to-one correspondence; the test output end of each attenuating sub-board is in one-to-one correspondence with the differential transmitting end of the sub-board slot.

The upper computer is used for sending a test command to the PCIE control chip to be tested, so that the PCIE control chip to be tested enters the test mode.

The PCIE control chip to be tested is used to output the first test signal through its own differential sending end in the test mode, and receive the second test signal returned by its own differential receiving end, and send the identification information of the AC parameters of the second test signal to the upper level wherein, the second test signal is the return signal of the first test signal after passing through the target attenuating sub-board currently plugged into the sub-board slot.

The upper computer is used to determine the performance index of the PCIE control chip to be tested under the target insertion loss based on the identification information of the AC parameters; wherein, the target insertion loss is the insertion loss provided by the target attenuation sub-board. Embodiments of the present invention ignore the small fixed insertion loss on the motherboard.

Based on the requirements of the PCIE control chip link test, the attenuation of the insertion loss of the PCIE differential signal link has various gradients. In order to reduce the difficulty of PCB design, the inventor thought of designing a variety of insertion loss attenuation sub-boards (each attenuation sub-board provides A kind of insertion loss, and all attenuation daughter boards are compatible with the same interface), and a combination of daughter boards and mother boards is used to build multi-lane (channel) and multi-gradient attenuation links. That is to say, if the attenuation test of the insertion loss of the PCIE differential signal link requires 7 kinds of attenuation gradients, then the corresponding 7 kinds of attenuation sub-boards can be designed.

Specifically, as shown in FIG. 3 , the PCIE control chip to be tested is set on the test motherboard, and the test motherboard is also equipped with a daughter board slot, which can support multiple attenuators of the same type of interface. The board is compatible and plugged on the same test motherboard. Therefore, the circuit design on the test motherboard can be done very simply. It only needs to lead out the differential signal lines of the PCIE control chip to be tested (including the differential transmitter and the differential receiver) and The shortest and point-to-point connection to the corresponding terminal of the daughter board slot is sufficient, and the complex attenuation loop design can be transferred to each attenuation daughter board. In the embodiment of the present invention, the differential transmitting end of the PCIE control chip to be tested is connected to the differential receiving end of the daughter board slot in a one-to-one correspondence, and the differential receiving end of the PCIE control chip to be tested and the differential transmitting end of the daughter board slot are connected one by one. corresponding connection. The PCIE control chip to be tested can be the control chip of x8 and x16 Lane channels of PCIE Gen5, or it can be the multi-channel control chip of other Gen.

As can be seen from the above description, the differential receiving end of the sub-board slot also corresponds to the test input end of the attenuator sub-board, and the differential transmitting end of the sub-board slot also corresponds to the test output end of the attenuating sub-board. That is, the daughter board slot is a connection device used to establish a connection between the test motherboard and the signal of the attenuated daughter board. The attenuation sub-board in the example uses gold-finger type interface terminals. Since the slot SLOT+Gold-finger card board method is a relatively mature solution in the field of PCIE protocol cards, the product cost can also be controlled to a certain extent. .

The existing attenuation sub-boards in the current test system are suitable for PCIE 16-channel differential lines. If there is a test requirement of 32 or more channels, the above-mentioned attenuation sub-boards can also be reused. For example, if the PCIE control chip to be tested is 32 channel, then set 2 sets of SLOT + gold finger design on its test motherboard to achieve the corresponding gradient attenuation, and multiple sets of SLOTs can be more flexible in circuit layout compared to only one set of SLOTs, which reduces the number of chips to a certain extent. In terms of the difficulty of layout design, at the same time, the multiplexing of the attenuation sub-board can also reduce the manufacturing cost.

In order to perform multi-gradient attenuation test on the PCIE differential signal link, the test system also needs to set the communication connection between the host computer and the PCIE control chip to be tested on the test motherboard; The test of the chip controls the wiring of the relevant pins, and guides the above wiring to the test input terminal of the upper computer.

After confirming that the target attenuation sub-board (any one of the multiple attenuation sub-boards) is correctly inserted into the sub-board slot on the test motherboard, the host computer will send a test command to the PCIE control unit to be tested through its test terminal chip, so that the PCIE control chip to be tested enters the test mode. The above test mode is a working mode preconfigured according to the requirements of the conventional PCIE control chip link test, which will not be repeated here. In the test mode, the PCIE control chip to be tested outputs the first test signal through its own differential transmitting end, and receives the second test signal returned by its differential receiving end. It can be seen from the structure description of the test system above that the second test signal is The test signal is the return signal after the first test signal passes through the target attenuator sub-board.

In order to determine the performance of the PCIE control chip to be tested under the current attenuation gradient, the PCIE control chip to be tested also needs to send the received identification information of the AC parameters of the second test signal to the host computer, so that the host computer can understand the second test signal. The identification information of the AC parameters is analyzed to determine the performance index of the PCIE control chip to be tested under the target insertion loss. Among them, the identification information of the AC parameters is also the processing information of the signal eye diagram, and the host computer can analyze and determine the AC parameter performance indicators of the PCIE control chip to be tested through this information (for the specific items of the performance indicators, please refer to the corresponding protocol standard). The above target insertion loss is the insertion loss provided by the target attenuator sub-board. The embodiment of the present invention does not specifically limit the performance index tested by the host computer, and the user can configure the composition structure of the host computer according to actual test requirements. That is, if the user wants to know the A parameter of the PCIE control chip to be tested under the target insertion loss, the upper computer should be equipped with a test device capable of determining the A parameter according to the second test signal.

The multi-gradient attenuation test system of the PCIE differential signal link provided by the present invention can build a multi-channel and multi-gradient attenuation link by combining the motherboard and the daughter board, and the test motherboard leads out the differential signal of the PCIE control chip to be tested. The design of the attenuation circuit is transferred to the attenuation sub-board, and the switching of different attenuation gradients is realized by replacing the attenuation sub-board plugged in the sub-board slot. Compared with using a special chip test board to complete the multi-gradient attenuation design of the PCIE differential signal link, the test system provided by the present invention can effectively reduce the difficulty of PCB design and shorten the chip test cycle, thereby quickly responding to user requirements, and the attenuator Board reuse can further reduce test costs.

In an optional implementation manner, the attenuation sub-board includes: N+1 attenuation links; the N+1 attenuation links include: one calibration link and N test links.

The input end of the calibration link is connected with the calibration input end of the sub-board slot, and the output end of the calibration link is connected with the calibration output end of the sub-board slot.

The input end of each test link is correspondingly connected to the test input end of the attenuation sub-board, and the output end of each test link is correspondingly connected to the test output end of the attenuation sub-board.

Specifically, in order to facilitate the measurement and correction of the performance parameters of the attenuation sub-board, in addition to setting N test links on the attenuation sub-board, the embodiment of the present invention further sets a calibration link on each attenuation sub-board, and the calibration The link uses the same circuit design as the single test link on the attenuator daughterboard. According to the PCIE protocol, the number N of differential signal channels of the test control chip is a multiple of the power of 2.

In the embodiment of the present invention, the input terminal of the calibration link is connected to the calibration input terminal of the sub-board slot, and the output terminal of the calibration link is connected to the calibration output terminal of the sub-board slot, so that the Build the S-parameter calibration measurement module. In the embodiment of the present invention, calibration test ports respectively connected to the calibration input end and the calibration output end of the sub-board slot are reserved on the test motherboard, and a network analyzer can be used to measure the attenuation of the calibration link on the sub-board through the calibration test port. S-parameter performance. For the part of the S-parameter that does not meet the standard, the designer can make corrections and adjustments in time. For example, the layout of the attenuation network and the high-frequency resistance value can be corrected, or other adjustment measures can be adopted.

Once it is determined that the S-parameters of the calibration link meet the standard, then on the basis of the known circuit design of the calibration link and a single test link, it can be determined that the S-parameters of all test links also meet the test requirements. The attenuator board can be put into use for testing.

It has been proved by experiments that if the attenuation sub-board is properly designed, the installation space of the attenuation sub-board can be controlled at about 45x160MM, that is, the size is equivalent to the size of the desktop computer memory card, which is convenient for its use in various occasions, such as: chip applications On-board functional test, ATE test carrier on-board PCIE performance test, etc.

In an optional implementation manner, as shown in FIG. 4 , each attenuation chain includes: a first-stage attenuator and a second-stage attenuator.

The input end of the first stage attenuator is connected with the input end of the attenuation chain, the output end of the first stage attenuator is connected with the input end of the second stage attenuator, and the output end of the second stage attenuator is connected with the attenuation chain connected to the output.

As mentioned above, the various attenuation gradients that PCIE Gen5 (16GHz/differential 85 ohm impedance) needs to be tested include: -5dB, -10dB, -15dB, -20dB, -25dB, etc., due to -15dB, -20dB, -25dB, etc. The attenuation value requirements of the gradient insertion loss are relatively large. Therefore, the attenuation link provided by the embodiment of the present invention adopts the design method of the two-stage attenuation network in series. Although the attenuation network with more than three stages can also achieve the above Attenuation requirements, but the three-level attenuation network will increase the cost and require a larger layout space, so it is preferred to use a two-level attenuation network. In addition, the attenuation link should take into account the transmission frequency and characteristic impedance requirements of PCIE differential signals. For example, the differential line of PCIE Gen5 has an impedance of 85 ohms.

In order to avoid the risk of burning out the passive resistance in the line, in an optional embodiment, the insertion loss of the first-stage attenuator is not greater than 3dB. That is to say, in the multi-gradient attenuation test system provided by the embodiment of the present invention, it is suggested that the first-level network does not attenuate energy exceeding 3 dB.

Optionally, the first-stage attenuator includes: a first π-type attenuator or a first T-type attenuator; and the second-stage attenuator includes: a second π-type attenuator or a second T-type attenuator.

Specifically, according to the radio frequency S-parameter theory, the two attenuators in the attenuation chain can choose to use a π-type attenuator or a T-type attenuator, and the embodiment of the present invention does not specifically limit the type of the attenuator. 5 is a schematic diagram of the design of a single attenuation link using a π-type passive attenuation network according to an embodiment of the present invention. When designing a two-stage π-type passive attenuation network, the attenuation sub-board and the sub-board should also be considered The connection insertion loss of the slot includes the loss of the RX gold finger and the loss of the TX gold finger. The following table 1 is an optional reference design for the distribution of the dB insertion loss energy in the two-stage π-type passive attenuation network in the multi-gradient attenuation design. In the embodiment of the present invention, the first stage attenuator and the second stage attenuation are not used. The specific attenuation value of the device is specifically limited, and the user can set it according to actual needs.

Table I

attenuation dB RX Gold Finger first stage attenuator second stage attenuator TX Gold Finger -5dB -1.5 -2 -0 -1.5 -10dB -1.5 -3 -4 -1.5 -15dB -1.5 -3 -9 -1.5 -20dB -1.5 -3 -14 -1.5 -25dB -1.5 -3 -19 -1.5

其中，Q(x)表示品质因子，x表示衰减因子，x的取值可以选择自然数N，Z₀₁表示网络的输入端阻抗，Z₀₀表示网络的输出端阻抗。例如，PCIE设计85欧姆阻抗匹配，故系统输入端接Z₀₁和输出端接Z₀₀阻抗皆为42.5欧姆。因此，依据多梯度衰减的两级设计中，不同的π型衰减网络的dB要求，是可以评估出初版无源电阻的Value值的。Figure 6 is a schematic diagram of a π-type attenuation network. Taking a π-type attenuator as an example, after determining the dB value that the attenuator needs to attenuate, in the passive attenuation π-type network, the selection of resistance parameters can refer to the following formula. Calculation: Q(x)=10 ^0.1x ;

Among them, Q(x) represents the quality factor, x represents the attenuation factor, and the value of x can be selected as a natural number N, Z ₀₁ represents the input impedance of the network, and Z ₀₀ represents the output impedance of the network. For example, the PCIE design is 85 ohm impedance matching, so the impedance of the system input terminal Z ₀₁ and the output terminal Z ₀₀ are both 42.5 ohms. Therefore, according to the dB requirements of different π-type attenuation networks in the two-stage design of multi-gradient attenuation, the value of the original passive resistor can be estimated.

After the layout of the attenuation sub-board is designed in the first version, the link parameter simulation of the attenuation sub-board can be performed, and ADS and ANSYS_HFSS/SIwave simulation software can be used for the simulation. Specifically, the performance parameters of the π-type attenuation network can be fitted by hierarchical simulation first, and then the full-link simulation can be integrated. The simulation process will not be described in detail here. In general, the important passive parameters that need to be paid attention to during simulation include: Insertion Loss IL (Insert Loss), Return Loss RL (Return Loss), differential imbalance and Time-Domain Reflectometry (TDR). It is necessary to confirm whether the current parameters are all can meet the design requirements. In addition, if you can obtain the chip package IBIS model and the chip AMI model, you can also perform eye diagram simulation to check whether the AC parameter eye diagram specifications of the PCIE Gen5 receiver can be met under different attenuation parameters.

In an optional embodiment, the Nyquist frequency of the transmission signal supported by the test motherboard and each attenuation daughter board is 16 GHz. Moreover, the test motherboard and each attenuation daughter board are backward compatible with low frequency (less than 16GHz) transmission signals.

The latest generation of PCIE control chips in the prior art is PCIE Gen5. According to the PCIE protocol, the transmission rate of Gen5 is 32Gbps, and the Nyquist frequency is 16GHz. Generally, the board can only support the transmission of low-speed frequency signals (for example, 0-10GHz). , can not meet the design requirements of PCIE Gen5, therefore, the PCB board of the test motherboard and the attenuation daughter board in the embodiment of the present invention should select high-performance Panasonic M6 and above boards. The transmission link attenuation is smaller.

In an optional implementation manner, the resonance frequency of the resistors in the first-stage attenuator and the second-stage attenuator is not less than twice the Nyquist frequency of the PCIE transmission signal to be tested.

In order to ensure the consistency of the performance of the board after PCB soldering, when selecting the resistance of the passive attenuation matching network, it is necessary to select a high-frequency resistance that is more than 2 times the Nyquist frequency of the PCIE transmission signal to be measured. If the PCIE control chip to be tested is a PCIE Gen5 chip, since the Nyquist frequency of PCIE Gen5 is 16GHz, it is recommended to use a high-frequency resistor with a frequency of 40G or higher.

To sum up, the embodiment of the present invention provides a multi-gradient attenuation test system for a PCIE differential signal link. Compared with the multi-gradient attenuation design of the PCIE differential signal link completed by the chip test board, the test system provided by the present invention can effectively reduce the difficulty of PCB design, shorten the chip test cycle, and quickly respond to user needs. , and the multiplexing of the attenuation sub-board can further reduce the test cost. In addition, different chips to be tested and different attenuation gradients can also use the same design and layout of the attenuation sub-board PCB. It is only necessary to adjust the resistance value of the resistors in the attenuation network according to the actual needs, which can greatly reduce the design and manufacture of the attenuation sub-board. cost, which is convenient for mass production.

Embodiment 2

An embodiment of the present invention further provides a multi-gradient attenuation test method for a PCIE differential signal link. The multi-gradient attenuation test method is applied to the multi-gradient attenuation test system for a PCIE differential signal link in the first embodiment. FIG. 7 shows A flowchart of a multi-gradient attenuation test method for a PCIE differential signal link provided by an embodiment of the present invention, as shown in FIG. 7 , the method specifically includes the following steps:

Step S102, sending a test instruction to the PCIE control chip to be tested, so that the PCIE control chip to be tested enters a test mode.

Step S104: Receive the identification information of the AC parameter of the second test signal returned by the PCIE control chip to be tested, and determine the performance index of the PCIE control chip to be tested under the target insertion loss based on the identification information of the AC parameter.

Wherein, the second test signal is the return signal after the PCIE control chip to be tested outputs the first test signal through its own differential transmission terminal in the test mode, and passes through the target attenuating sub-board currently inserted in the sub-board slot; the target insertion loss Insertion loss provided for the target attenuator daughterboard. Embodiments of the present invention ignore the small fixed insertion loss on the motherboard.

The structure and working principle of the multi-gradient attenuation test system of the PCIE differential signal link have been described in detail in the above-mentioned Embodiment 1. For details, please refer to the above, and will not be repeated here.

In an optional implementation manner, before step S102 is executed and the test instruction is sent to the PCIE control chip to be tested, the method of the present invention further includes the following steps:

Step S1011, sending a calibration signal to the calibration input end of the sub-board slot, and receiving a feedback signal from the calibration output end of the sub-board slot.

Step S1012, based on the calibration signal and the feedback signal, determine whether the S parameter of the calibration link of the target attenuation sub-board meets the preset attenuation standard.

If it is determined to be in line, the above step S102 is performed, and a test instruction is sent to the PCIE control chip to be tested.

Specifically, before using the multi-gradient attenuation test system to test the PCIE chip to be tested, it is necessary to judge whether the attenuation link on the attenuation sub-board meets the preset attenuation standard. PCIE control chip, so that the PCIE control chip to be tested enters the test mode, and then its performance index is evaluated. In the existing test environment, network analyzers are mostly used to connect the calibration input and calibration output of the sub-board slot to measure the attenuation value of the calibration link on the attenuation sub-board and compare it with the expected value. to determine whether the target is met.

Embodiment 3

Referring to FIG. 8 , an embodiment of the present invention provides an electronic device, the electronic device includes: a processor 60 , a memory 61 , a bus 62 and a communication interface 63 , the processor 60 , the communication interface 63 and the memory 61 are connected through the bus 62 ; The processor 60 is used to execute executable modules, such as computer programs, stored in the memory 61 .

The memory 61 may include a high-speed random access memory (RAM, Random Access Memory), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 63 (which may be wired or wireless), which may use the Internet, a wide area network, a local area network, a metropolitan area network, and the like.

The bus 62 may be an ISA bus, a PCI bus, an EISA bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one bidirectional arrow is used in FIG. 8, but it does not mean that there is only one bus or one type of bus.

The memory 61 is used to store a program, and the processor 60 executes the program after receiving the execution instruction. The method executed by the apparatus defined by the stream process disclosed in any of the foregoing embodiments of the present invention can be applied to processing in the processor 60 , or implemented by the processor 60 .

The processor 60 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above-mentioned method can be completed by a hardware integrated logic circuit in the processor 60 or an instruction in the form of software. The above-mentioned processor 60 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; it may also be a digital signal processor (Digital Signal Processing, DSP for short) , Application Specific Integrated Circuit (ASIC for short), Field-Programmable Gate Array (FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The methods, steps, and logical block diagrams disclosed in the embodiments of the present invention can be implemented or executed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present invention may be directly embodied as executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory 61, and the processor 60 reads the information in the memory 61, and completes the steps of the above method in combination with its hardware.

The multi-gradient decay test method for a PCIE differential signal link and the computer program product of the electronic device provided by the embodiments of the present invention include a computer-readable storage medium storing a non-volatile program code executable by a processor, and the program The instructions included in the code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, reference may be made to the method embodiments, which will not be repeated here.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-executable non-volatile computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of the invention is usually placed in use, only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first", "second", "third", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

Furthermore, the terms "horizontal", "vertical", "overhanging" etc. do not imply that a component is required to be absolutely horizontal or overhang, but rather may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal than "vertical", it does not mean that the structure must be completely horizontal, but can be slightly inclined.

In the description of the present invention, it should also be noted that, unless otherwise expressly specified and limited, the terms "arranged", "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection, It can also be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or the internal communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (11)

1. A multi-gradient attenuation test system of a PCIE differential signal link is characterized by comprising: the device comprises an upper computer, a test mother board and a plurality of attenuation daughter boards; the test motherboard is provided with a PCIE control chip to be tested and daughter board slots, and each attenuation daughter board can be movably plugged into the daughter board slots; each attenuation daughter board is used for providing a preset insertion loss;

the upper computer is connected with the PCIE control chip to be tested; the differential transmitting ends of the PCIE control chip to be tested are connected with the differential receiving ends of the daughter board slots in a one-to-one correspondence mode; the test input end of each attenuation daughter board corresponds to the differential receiving end of the daughter board slot one by one;

the differential receiving ends of the PCIE control chips to be tested are connected with the differential sending ends of the daughter board slots in a one-to-one correspondence manner; the test output end of each attenuation daughter board corresponds to the differential transmitting end of the daughter board slot one by one;

the upper computer is used for sending a test instruction to the PCIE control chip to be tested so as to enable the PCIE control chip to be tested to enter a test mode;

the PCIE control chip to be tested is used for outputting a first test signal through the self differential sending end in the test mode, receiving a second test signal returned by the self differential receiving end and sending identification information of alternating current parameters of the second test signal to the upper computer; the second test signal is a return signal of the first test signal after passing through a target attenuation daughter board currently inserted into the daughter board slot;

the upper computer is used for determining the performance index of the PCIE control chip to be tested under the target insertion loss based on the identification information of the alternating current parameters; wherein the target insertion loss is an insertion loss provided by the target attenuator daughter board.

2. The multi-gradient attenuation testing system of claim 1, wherein the attenuation sub-board comprises: n +1 attenuation links; the N +1 attenuation links comprise: one calibration link and N test links;

the input end of the calibration link is connected with the calibration input end of the daughter board slot, and the output end of the calibration link is connected with the calibration output end of the daughter board slot;

the input end of each test link is correspondingly connected with the test input end of the attenuation daughter board, and the output end of each test link is correspondingly connected with the test output end of the attenuation daughter board.

3. The multi-gradient attenuation testing system of claim 2, wherein each of the attenuation links comprises: a first stage attenuator and a second stage attenuator;

the input end of the first-stage attenuator is connected with the input end of the attenuation link, the output end of the first-stage attenuator is connected with the input end of the second-stage attenuator, and the output end of the second-stage attenuator is connected with the output end of the attenuation link.

4. The multi-gradient attenuation testing system of claim 3, wherein the first stage attenuator comprises: a first pi-type attenuator or a first T-type attenuator; the second stage attenuator includes: a second pi-type attenuator or a second T-type attenuator.

5. The multi-gradient attenuation testing system of claim 3, wherein the insertion loss of the first stage attenuator is no greater than 3 dB.

6. The multi-gradient attenuation testing system of claim 1, wherein the nyquist frequency of the transmission signal supported by the test motherboard and each of the attenuation daughter boards is 16 GHz.

7. The multi-gradient attenuation test system of claim 3, wherein the resonant frequency of the resistors in the first-stage attenuator and the second-stage attenuator is not less than 2 times the Nyquist frequency of the transmission signal of the PCIE control chip to be tested.

8. A multi-gradient attenuation test method for a PCIE differential signal link, which is applied to the multi-gradient attenuation test system for a PCIE differential signal link according to any one of claims 1 to 7, and the method includes:

sending a test instruction to a PCIE control chip to be tested so as to enable the PCIE control chip to be tested to enter a test mode;

receiving identification information of an alternating current parameter of a second test signal returned by the PCIE control chip to be tested, and determining a performance index of the PCIE control chip to be tested under the target insertion loss based on the identification information of the alternating current parameter; the second test signal is a return signal of the PCIE control chip to be tested after the first test signal is output by a self differential sending end in the test mode and passes through a target attenuation daughter board currently inserted into a daughter board slot; the target insertion loss is an insertion loss provided by the target attenuator daughter board.

9. The multi-gradient attenuation testing method according to claim 8, before sending the testing command to the PCIE control chip to be tested, the method further comprises:

sending a calibration signal to a calibration input end of the daughter board slot, and receiving a feedback signal of a calibration output end of the daughter board slot;

judging whether the S parameter of the calibration link of the target attenuation daughter board meets a preset attenuation standard or not based on the calibration signal and the feedback signal;

and sending the test instruction to a PCIE control chip to be tested under the condition of determining the coincidence.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the processor implements the steps of the method of any of the preceding claims 8 to 9 when executing the computer program.

11. A computer-readable medium having non-volatile program code executable by a processor, the program code causing the processor to perform the method of any of claims 8 to 9.

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