CN117743053A

CN117743053A - High-speed signal processing method, device, equipment and system

Info

Publication number: CN117743053A
Application number: CN202311755087.9A
Authority: CN
Inventors: 姚文博
Original assignee: Xian Yep Telecommunication Technology Co Ltd
Current assignee: Xian Yep Telecommunication Technology Co Ltd
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-03-22

Abstract

The application provides a method, a device, equipment and a system for processing a high-speed signal, wherein the method comprises the following steps: acquiring a total link loss value allowed by a PCIE version of a high-speed serial computer expansion bus standard selected by a user; performing simulation according to the total link loss value to obtain an S parameter; adjusting the input signal according to the S parameter to obtain an adjusted signal; and outputting an adjusted signal, wherein the adjusted signal is used for testing the test link. The method solves the problem that the link loss required by the test link is reached by using the mode of plugging the ISI plate in the prior art, and the mode of embedding the S parameter adjusts the signal to be less influenced by the ambient temperature and humidity compared with the mode of the ISI plate, thereby improving the test efficiency and stability.

Description

High-speed signal processing method, device, equipment and system

Technical Field

The present disclosure relates to the field of high-speed signal measurement, and in particular, to a method, an apparatus, a device, and a system for processing a high-speed signal.

Background

The signal consistency test helps to verify the stability of the product under different operating conditions. By examining the consistency of the signals throughout the transmission link, it is ensured that the product will remain stable in a wide variety of environments and use conditions.

Intersymbol interference (ISI) is commonly used to simulate the consistency characteristics of high-speed signals during transmission, particularly in high-speed communication systems, high-frequency circuit designs and testing. Because the interface of the ISI board is plugged and pressed for a long time, a printed circuit board (Printed Circuit Board, PCB for short) is easy to bend, and the PCB is influenced by the ambient temperature and humidity and other factors, so that the result change of a calibrated file is large when the calibrated file is used each time, the actual condition of the link can not be accurately reflected, and error information can be caused; in addition, when the ISI plate is used for network calibration, the loss condition of a plurality of sections is measured manually, so that manpower and time are consumed, and the calibration and test efficiency is reduced.

Therefore, how to improve the verification efficiency and accuracy of the test process is a problem to be solved.

Disclosure of Invention

The application provides a method, a device, equipment and a system for processing a high-speed signal, which are used for solving the problem of low efficiency in the existing high-speed signal processing process.

In a first aspect, the present application provides a high-speed signal processing apparatus, the apparatus comprising: the system comprises an ISI generating module, a loss embedding module, a power module, a first SMA connector and a second SMA connector;

The ISI generation module is respectively connected with the loss embedding module and the power supply module and is used for generating S parameters in a simulation mode according to the set total link loss value;

the loss embedding module is respectively connected with the power supply module, the first SMA connector and the second SMA connector;

the first SMA connector inputs a received input signal to the loss embedding module, the loss embedding module adjusts the input signal according to the S parameter to obtain an adjusted signal, and the adjusted signal is output through the second SMA connector.

Optionally, the second SMA connector comprises: at least one adapter of the SMA-USB adapter, the SMA-SMP adapter and the SMA-MMPX adapter.

Optionally, the apparatus further includes: the third SMA connector, the fourth SMA connector and the channel indicator lamp;

the third SMA connector and the fourth SMA connector are respectively connected with the loss embedding module;

the third SMA connector is configured to receive a new input signal, the new input signal being a signal generated after the conditioned signal passes through an external test device;

The loss embedding module is also used for adjusting the new input signal according to the S parameter to generate a new adjusted signal;

the fourth SMA connector is configured to output the new adjusted signal;

the channel indicator light is connected with the power module and used for indicating a channel which is processing signals.

Optionally, the apparatus further includes: a processor;

the processor is respectively connected with the ISI generation module, the loss embedding module and the power supply module, and is used for controlling the ISI generation module and the loss embedding module.

Optionally, the apparatus further includes: a control switch, a USB interface and/or an Ethernet interface;

the control switch is connected with the power supply module and is used for controlling the power supply module to be turned on or turned off;

the USB interface and/or the Ethernet interface is/are connected with the processor, and the USB interface and/or the Ethernet interface inputs the received control signals to the processor.

Optionally, the power module includes an ac-to-dc unit, and the ac-to-dc unit is configured to convert an input ac into a dc.

In a second aspect, the present application provides a method for processing a high-speed signal, which is applied to the device for processing a high-speed signal according to any one of the first aspects, and the method includes:

acquiring a total link loss value allowed by a PCIE version of a high-speed serial computer expansion bus standard selected by a user;

performing simulation according to the total link loss value to obtain an S parameter;

adjusting the input signal according to the S parameter to obtain an adjusted signal;

and outputting the adjusted signal, wherein the adjusted signal is used for testing a test link.

Optionally, the step of performing simulation according to the total link loss value to obtain an S parameter includes:

calculating to obtain a first insertion loss value according to the total link loss value and a link loss value of a processing device which removes the high-speed signal in the test link;

and obtaining the S parameter through simulation according to the first insertion loss value.

acquiring the type of an object to be tested selected by the user in the test process, wherein the type of the object to be tested comprises a main board or an additional card;

Calculating a second insertion loss value according to the total link loss value and a link loss value of a processing device for removing the high-speed signal in the test link after the object to be tested is placed;

and simulating and obtaining the S parameter according to the second insertion loss value.

In a third aspect, the present application further provides a high-speed signal processing apparatus, the apparatus including:

the acquisition module is used for acquiring the total link loss value allowed by the PCIE version of the high-speed serial computer expansion bus standard selected by the user;

the simulation module is used for performing simulation according to the total link loss value to obtain an S parameter;

the adjusting module is used for adjusting the input signal according to the S parameter to obtain an adjusted signal;

and the output module is used for outputting the adjusted signal, and the adjusted signal is used for testing the test link.

Optionally, the simulation module is specifically configured to:

In a fourth aspect, the present application further provides a high-speed signal processing system, where the system includes the high-speed signal processing device, the error code meter, and the test fixture set according to any one of the first aspects.

The method, the device, the equipment and the system for processing the high-speed signal provided by the application comprise the following steps: acquiring a total link loss value allowed by a PCIE version of a high-speed serial computer expansion bus standard selected by a user; performing simulation according to the total link loss value to obtain an S parameter; adjusting the input signal according to the S parameter to obtain an adjusted signal; and outputting an adjusted signal, wherein the adjusted signal is used for testing the test link. The method solves the problem that the link loss required by the test link is reached by using the mode of plugging the ISI plate in the prior art, and the mode of adjusting the signal by embedding the S parameter is less influenced by the ambient temperature and humidity compared with the mode of the PCB of the ISI, so that the test efficiency and stability are improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of a first embodiment of a high-speed signal processing device provided in the present application;

Fig. 2 is a schematic structural diagram of a second embodiment of a high-speed signal processing device provided in the present application;

fig. 3 is a schematic structural diagram of a third embodiment of a high-speed signal processing device provided in the present application;

fig. 4 is a schematic structural diagram of a fourth embodiment of a high-speed signal processing device provided in the present application

Fig. 5 is a flowchart of a first embodiment of a method for processing a high-speed signal provided in the present application;

fig. 6 is a flowchart of a second embodiment of a method for processing a high-speed signal provided in the present application;

fig. 7 is a schematic structural diagram of a high-speed signal processing device provided by the present application;

fig. 8 is a networking schematic diagram of the high-speed signal processing system provided in the present application.

Reference numerals illustrate:

a 101-ISI generation module; 102-a loss embedding module; 103-a power module; 104-a first SMA connector; 105-a second SMA connector; 106-a third SMA connector; 107-fourth SMA connector; 108-a channel indicator light; 109-a processor; 110-a control switch; a 111-USB interface; 112-ethernet interface.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

The terms referred to in this application are explained first:

and (3) testing networking: by test networking is meant a test environment and connection configuration that is built to evaluate, verify, or optimize an electronic device, communication system, or other electronic component. The test network comprises tools such as test equipment, connectors, cables, clamps, possible analog signal sources, network analyzers and the like, and the tested equipment itself.

Testing and calibrating networking: refers to a configuration in a test network for ensuring that test equipment and test environments provide accurate measurement and assessment results. Errors in the system are eliminated or compensated by calibrating the test equipment and the networking elements to ensure that the measurement results conform to the accuracy of the actual physical quantity.

Intersymbol interference (Intersymbol Interference, simply: ISI) plates: refers to a special board card or device for simulating and introducing ISI characteristics, i.e. interference between adjacent symbols in high-speed communication. ISI boards are commonly used to test high-speed communication systems, particularly in the high-speed serial computer expansion bus standard (peripheral component interconnect express, abbreviated as PCIe), to evaluate the sensitivity of the system to ISI and optimize signal integrity.

Scattering parameter (Scatter, S parameter): is a set of complex numbers used to describe scattering parameters in a multiport linear circuit. For a two-port network, the S parameters typically include S11, S12, S21, and S22, which can provide detailed information about signal propagation and reflection in the circuit. Wherein S12 is a reverse transmission coefficient, representing isolation, S21 is a forward transmission coefficient, representing gain. S11 is an input reflection coefficient and also represents an input return loss, and S22 is an output reflection coefficient and represents an output return loss.

In PCIE test calibration networking, ISI boards are used to simulate ISI that may be present in an actual transmission link in order to more fully evaluate the performance of the system during testing. The test calibration networking aims to ensure that the system provides accurate, reliable and repeatable measurement results, thereby improving the accuracy and reliability of the test.

There are many sources of distortion in the channels of PCIE test systems that can degrade the signal quality from the PCIE transmitter to the PCIE receiver, including crosstalk, jitter, inter-symbol interference (ISI), and so on. The loss characteristics in the channel must be measured to ensure that they are within the tolerance of PCIe for a particular data rate. The use of a vector network analyzer can help quickly verify various parameters in the design, ensuring that they meet the performance requirements of the PCIe specification.

In the prior art, high-speed signal integrity testing is performed according to standards defined by an association organization, and starting from PCIE4.0, a variable ISI board fixture is introduced into a test calibration network, and a plurality of differential trace pairs stepped by approximately 0.5dB loss are designed on the fixture, before a transmitter/receiver is tested, a network analyzer is required to calibrate and select a proper trace pair, and a total link loss target required by a specification is constructed.

However, calibration and proper routing pairs are required to be replaced frequently, because the interface of the ISI board is plugged and pressed for a long time, the PCB is easy to bend, and the result change of a calibrated file is large when the calibrated file is used each time due to the factors such as the influence of the ambient temperature and the humidity, the actual condition of a link cannot be accurately reflected, and error information is caused; in addition, when the ISI plate is used for network calibration, different wiring pairs are manually plugged and unplugged, the loss condition of multiple sections is measured, manpower and time are very consumed, and the calibration and test efficiency is reduced.

In addition, the ISI board configures only one interface, while the PCIE GEN3/GEN4 protocol specifies the SMP interface, the PCIE GEN5 specifies the MMPX interface, and there are compatibility issues with other interface types.

In view of this, the inventor found that in the process of researching the integrity of PCIE signals, the purpose of inserting and modifying the ISI board routing pair by a tester is to generate different losses in the test network to perform calibration and testing, and by replacing the ISI board with a device capable of generating S parameters in the test link, different line losses can be changed by directly embedding different S parameters. Therefore, according to the loss standard required by the protocol, the test calibration and the test of PCIE equipment can be completed by changing the S parameter, artificial plugging and measurement are not needed, the calibration and test efficiency is improved, and in addition, the test device provided by the application can be suitable for different test fixtures and can be compatible with various test signals. Based on the above, the application provides a method, a device, equipment and a system for testing high-speed signal integrity.

The application scene is applied to the PCIE signal integrity test process, and can also be applied to calibration of test equipment in a test network.

The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a first embodiment of a high-speed signal processing apparatus provided in the present application, where the apparatus includes: an ISI generation module 101, a loss embedding module 102, a power supply module 103, a first SMA connector 104, and a second SMA connector 105.

The ISI generating module 101 is respectively connected with the loss embedding module 102 and the power module 103, and the ISI generating module 101 is used for generating an S parameter according to the set total link loss value simulation. Wherein the S parameter is used to describe the scattering parameter between different ports in the circuit. The ISI generating module 101 generates a simulated S parameter by simulating the loss and signal transmission process. The S parameter reflects signal distortion and interference that may occur in the actual link, providing a system performance parameter under different loss conditions.

The loss embedded module 102 is connected to the power module 103, the first SMA connector 104, and the second SMA connector 105, respectively. The loss embedding module 102 is configured to adjust scattering parameters of the signal in the link according to the provided S parameter information, and adjust loss and distortion of the signal during transmission.

The first SMA connector 104 inputs the received input signal to the loss embedding module 102, the loss embedding module 102 adjusts the input signal according to the S parameter, obtains an adjusted signal, and outputs the adjusted signal through the second SMA connector 105.

Optionally, the second SMA connector comprises: at least one adapter of the SMA-USB adapter, the SMA-SMP adapter and the SMA-MMPX adapter. Different test fixtures can be adapted through different adapter on the basis of SMA connectors. Therefore, the hardware of the interface such as NVME, SATA, SAS can be tested in the error code test through the transfer of the adapter.

Alternatively, the inner diameters of the outer conductors of the first SMA connector and the second SMA connector may be selected from, but not limited to, 2.4mm, 2.92mm, 3.5mm; preferably, the inner diameter of the outer conductor of the first SMA connector and the second SMA connector is 2.92mm.

Alternatively, the source of power for the power module 103 may be an externally connected ac power or a battery internal to the device. When the electric quantity source of the power supply module can be alternating current connected outside the device, the power supply module comprises an alternating current-to-direct current unit, and the alternating current-to-direct current unit is used for converting the input alternating current into direct current.

The present embodiment provides a high-speed signal processing apparatus, which can change the transmission loss of a signal passing through the apparatus by adjusting the S parameter according to the actually required link loss through an internal ISI generating module and a loss embedding module. The device can replace an ISI plate defined by an association, optimize a test link, adjust the link loss only by changing a set S parameter, avoid the defect that the ISI plate is frequently plugged and unplugged in the prior art, and can share a processing device of a high-speed signal on various signal clamps in a manner of an adapter, thereby solving the defect that the ISI plate only supports one interface in the prior art, and expanding the use scene for adjusting the link loss.

Fig. 2 is a schematic structural diagram of a second embodiment of a high-speed signal processing device provided in the present application, where on the basis of the first embodiment of the device, the device further includes: a third SMA connector 106, a fourth SMA connector 107 and a channel indicator 108.

The third SMA connectors 106 and the fourth SMA connectors 107 are connected to the loss embedded module 102, respectively.

The third SMA connector 106 is configured to receive a new input signal, which is the signal generated after the conditioned signal has passed through the external test equipment.

Optionally, the loss embedding module 102 is further configured to adjust the new input signal according to the S parameter, and generate a new adjusted signal.

Optionally, input signals corresponding to different connector interfaces are preconfigured to be set to different S parameters respectively, and the loss embedding module 102 selectively adjusts the input signals. Illustratively, the first SMA connector and the third SMA connector are two input interfaces in a set of ISI channels, the loss embedding module adjusts the signal input by the first SMA connector according to the S parameter, and does not adjust the signal input by the third SMA connector.

The fourth SMA connector 107 is used to output a new conditioned signal.

A channel indicator light 108 is connected to the power module for indicating the channel on which the signal is being processed.

Alternatively, the channel indicator light 108 flashing green indicates that the channel is communicating and is normally lit to indicate a pause in input and output.

The first SMA connector 104, the second SMA connector 105, the third SMA connector 106, and the fourth SMA connector 107 form a set of ISI channels. The error code meter signal is input into the processing device of the high-speed signal through the first SMA connector, the processing device of the high-speed signal is output through the second SMA connector after being regulated by the signal of the loss embedding module, the error code meter signal is input into the processing device of the high-speed signal through the third SMA connector after being regulated by the signal of the loss embedding module, and the processing device of the high-speed signal is output through the fourth SMA connector to reach the oscilloscope or other equipment.

Optionally, the apparatus further comprises a selection button, connected to the ISI generating module, and the user may adjust the value of the S parameter generated by the ISI generating module by selecting the button. The user may also control the adjustment of ISI generating module parameters by selecting a button.

Optionally, the apparatus further comprises a display means by which a user can view parameters of the ISI generating module configuration. The display device may also have interactive functionality to prompt the user to operate via the user graphical interface.

The embodiment provides a high-speed signal processing device, which comprises an ISI generating module, a loss embedding module, a power module, a first SMA connector, a second SMA connector, a third SMA connector, a fourth SMA connector and a channel indicator lamp, wherein the indicator lamp indicates whether the device is in a working state; the first SMA connector, the second SMA connector, the third SMA connector, and the fourth SMA connector form a set of ISI channels, and the loss embedding module may embed different S parameters, i.e. perform different loss adjustments, on signals input by different connectors in the set of ISI channels. The arrangement of the device can be suitable for different conditions of adjustment requirements.

Fig. 3 is a schematic structural diagram of a third embodiment of the high-speed signal processing device provided in the present application, as shown in fig. 3, on the basis of the first embodiment of the device, the device further includes: a processor 109.

The processor 109 is connected to the ISI generating module 101, the loss embedding module 102, and the power supply module connection 103, respectively, and the processor 109 is configured to control the ISI generating module 101 and the loss embedding module 102.

In one implementation, the processor is capable of controlling the ISI generation module to generate the S parameter in accordance with a control signal generated in response to a user operation and controlling the loss embedding module to embed the S parameter into the communication link. In this implementation, the processing device of the high-speed signal includes a device (such as a touch display screen) that interacts with the user, and can acquire the operation of the user, so that the processor generates the control signal according to the user operation.

In another implementation, the processor can control the ISI generating module to generate the S parameter according to the received external control signal and control the loss embedding module to embed the S parameter into the communication link. In this implementation, the high-speed signal processing device includes a module (e.g., a wireless communication module, an interactive interface) that interacts with an external device, and is capable of acquiring an operation instruction of a user, so that the processor generates a control signal according to the user operation.

The embodiment provides a high-speed signal processing device, which comprises an internal processor, and can control an ISI generating module and a loss embedding module to generate and embed S parameters according to the operation or the instruction of a user.

Fig. 4 is a schematic structural diagram of a fourth embodiment of the high-speed signal processing device provided in the present application, as shown in fig. 4, on the basis of the third embodiment of the device, the device further includes: a control switch 110, a usb interface 111 and/or an ethernet interface 112;

the control switch 110 is connected to the power module 103, and is used for controlling the power module to be turned on or off.

The processor of the high-speed signal processing device may be directly connected through a universal serial bus (Universal Serial Bus, abbreviated as USB) interface and/or an ethernet interface external device. An external device (e.g., a computer or other terminal device) may input control signals or control data to the processor via a USB interface and/or an ethernet interface. If the interactive interface is a USB interface, the USB interface may also be connected to a storage device (for example, a USB disk), and parameters or data in the storage device are input to the processor, where the processor processes the acquired data according to a preset rule. The USB interface may have one or more, may be a TypeA and/or TypeC interface. Illustratively, the data of the S parameter is stored in the usb disk, and the processor reads the S parameter in the storage device, inputs the S parameter to the loss embedding module, and controls the loss embedding module to embed the S parameter into the communication link.

The embodiment provides a high-speed signal processing device, which is connected with external equipment through a USB interface and/or an ethernet interface, and a user can control the high-speed signal processing device through the USB interface and/or the ethernet interface.

Fig. 5 is a flowchart of a first embodiment of a method for processing a high-speed signal, as shown in fig. 5, where the method includes the following steps:

s301, acquiring a total link loss value allowed by a PCIE version of a high-speed serial computer expansion bus standard selected by a user.

In the scheme, the PCIE test specification clearly specifies the loss of the test link, and specifies the total link loss from end to end, the loss of the components such as the motherboard, the card, the slot, the connector and the like. Link loss is typically expressed in dB, with the specification specifying the allowable loss range for each component at frequency. For example, the total link loss value of the whole link in the PCIE3.0 test standard is-22 dB, the total link loss value of the whole link in the PCIE4.0 test standard is-28 dB, and the total link loss value of the whole link in the PCIE5.0 test standard is-36 dB. The later pushed PCIE version will also specify the total link loss value allowed.

Illustratively, the PCIE 5.0 test specification specifies an overall link loss of-36 dB end-to-end at a frequency of 16 GHz; motherboard loss-26.5 dB; the total loss of the plug-in card, whether the transmission path or the receiving path, including the PCB, the via hole, the value-isolating capacitor, the chip package and the like, from the edge of the golden finger cannot exceed-9.5 dB.

Illustratively, the PCIE 4.0 test specification specifies an overall link loss of-28 dB end-to-end at 8GHz frequency; motherboard loss-20 dB; the total loss of the plug-in card, whether the transmission path or the receiving path, including the PCB, the via hole, the value-isolating capacitor, the chip package and the like, from the edge of the golden finger cannot exceed-8 dB.

In one implementation, a user selects a PCIE version by operating on a processing device of a high-speed signal, and the processing device of the high-speed signal obtains a total link loss value allowed by the user to select the PCIE version according to total link loss values corresponding to different preconfigured PCIE versions. Illustratively, if the user selects PCIE version 5.0, then the total allowed link loss value is-36 dB.

In one implementation, a user inputs an allowable total link loss value of-36 dB to a high-speed signal processing device through an interface of the high-speed signal processing device, and the high-speed signal processing device acquires the total link loss value allowed by the PCIE version input by the user.

In one implementation, according to a PCIE version input or selected by a user, the PCIE version is connected to a preset cloud server through a network to query a total link loss value allowed by the PCIE version. The content in the cloud server comprises a preset total link loss value allowed by each PCIE version and a link loss value of each component.

S302, performing simulation according to the total link loss value to obtain an S parameter.

In the step, S parameters of simulation corresponding to different test conditions are different, and when a user selects to perform a calibration test function, the S parameters are required to be adjusted to enable the actual loss value of a total line to move up and down on the total link loss value according to a preset step length; when a user selects a receiving end tolerance test, setting the tolerance test as a preset loss according to a protocol specification; when a user selects to perform a main board test function, simulating and generating an S parameter according to a loss value required by the main board test; and when the user selects to perform the card inserting test function, simulating and generating an S parameter according to the loss value required by the card inserting test.

In a specific implementation, the first insertion loss value is calculated according to the total link loss value and a link loss value of a processing device in the test link for removing the high-speed signal. And obtaining the S parameter through simulation according to the first insertion loss value. The link loss value of the processing device for removing the high-speed signal in the test link can be obtained through measurement, and a user inputs the link loss value into the processing device for removing the high-speed signal. Illustratively, the total link loss value is-36 dB, the actual loss value of the test link is-10 dB, and the first insertion loss value is-26 bB.

The link loss value of the processing device for removing the high-speed signal in the test link can be measured directly by using a vector network analyzer or the loss value of each component is measured according to the test specification, and the link loss value of the processing device for removing the high-speed signal in the whole test link is calculated.

The high-speed signal processing device uses electromagnetic field simulation software (such as CST Microwave Studio, keysight Advanced Design System and the like) or a linear simulation tool (such as MATLAB and the like) for simulation. And establishing a circuit model in the simulation tool, adjusting parameters of corresponding components in the simulation tool, simulating an actual loss value and a first insertion loss value, and obtaining a simulation result. S parameters are extracted from simulation results. The simulation tool typically provides an S-parameter matrix that contains all S-parameters at the frequency bin.

Wherein the simulation of the different S parameters mainly changes the parameters of S11, S12, S21 and S22. Wherein S12 is a reverse transmission coefficient, representing isolation, S21 is a forward transmission coefficient, representing gain. S11 is an input reflection coefficient and also represents an input return loss, and S22 is an output reflection coefficient and represents an output return loss.

S303, adjusting the input signal according to the S parameter to obtain an adjusted signal.

In this step, the S parameters are embedded in the test link, and the parameters of the selected components are adjusted according to the target S parameters, which may include changing the element values of the impedance matching network, etc.

After the S parameter is embedded into the test link, the test link in the device can realize the adjustment of the input signal, and the adjusted signal is obtained.

Optionally, the S parameter is embedded in only one link, and only signals of a specified input/output line are adjusted.

S304, outputting an adjusted signal, wherein the adjusted signal is used for testing the test link.

The embodiment provides a processing method of a high-speed signal, which is used for acquiring a total link loss value allowed by a PCIE version of a high-speed serial computer expansion bus standard selected by a user; performing simulation according to the total link loss value to obtain an S parameter; adjusting the input signal according to the S parameter to obtain an adjusted signal; and outputting an adjusted signal, wherein the adjusted signal is used for testing the test link. By the method, the link loss required by the link reaching in the prior art by using the mode of plugging the ISI plate is solved, the test efficiency is improved, and the mode of adjusting signals by embedding S parameters is less influenced by the ambient temperature and humidity compared with the mode of the PCB plate of the ISI.

Fig. 6 is a flow chart of a second embodiment of the high-speed signal processing method provided in the present application, as shown in fig. 6, on the basis of the first embodiment, when performing a link test, performing simulation according to a total link loss value to obtain an S parameter, including the following steps:

s3021, obtaining the type of the object to be tested selected by the user in the testing process, wherein the type of the object to be tested comprises a main board or an additional card.

In this step, the S parameters that need to be generated in the simulation in the processing device of the high-speed signal are different for different subjects to be tested because of their different loss requirements on the test jig. After calibration of the test link, the type of the object to be tested selected by the user on the processing device of the high-speed signal is obtained, wherein the type of the object to be tested comprises a main board or an additional card.

S3022, calculating a second insertion loss value according to the total link loss value and the link loss value of the processing device for removing the high-speed signal in the test link after the object to be tested is placed.

In one implementation, after the object to be tested is placed, the link loss value of the processing device excluding the high-speed signal in the whole test link is measured by the vector network analyzer, and the link loss value is input into the processing device of the high-speed signal.

In one implementation, the loss value of each component is measured according to a test specification, the link loss value of the processing device excluding the high-speed signal in the whole test link is calculated, and the link loss value is input into the processing device of the high-speed signal.

And subtracting the link loss value of the processing device for removing the high-speed signal in the whole actually measured test link from the total link loss value required by the PCIE version to obtain a second insertion loss value.

In another way of calculating the second insertion loss value, the link loss allowed by the test standard is used to subtract the line loss to obtain the second insertion loss value. Illustratively, in PCIE5.0, when a test motherboard is selected, the total link loss value is-36 dB, the loss allocated to the motherboard is-26.5 dB, the allowable link loss is-9.5 dB, and the-9.5 dB is distributed on a consistency load board (Card Location Bracket, CLB for short), a cable, a connector and a processing device of a high-speed signal, so that the allowable link loss is-9.5 dB minus the line loss of the actual CLB and the cable to obtain a second insertion loss value. The loss of the components such as the CLBs, the cables, the connectors and the like can be configured in the high-speed signal processing device in advance according to the standard, and the loss can be calculated by selecting the corresponding number and length in the high-speed signal processing device by a user.

Alternatively, considering the loss of the connector and the line of the processing apparatus of the high-speed signal, when the S parameter is not set, the link loss of the processing apparatus of the high-speed signal is measured in advance, and when the second insertion loss value is calculated, the link loss of the processing apparatus of the high-speed signal needs to be considered. In one implementation, the total link loss value required according to the PCIE version subtracts the link loss value of the processing device that removes the high-speed signal from the entire actually measured test link, and subtracts the link loss of the processing device that removes the high-speed signal to obtain the second insertion loss value. In another implementation, the link loss allowed by the test standard is used to subtract the line loss and then subtract the link loss of the processing device of the high speed signal to obtain the second insertion loss value.

S3023, simulating and obtaining an S parameter according to the second insertion loss value.

In this step, an electromagnetic field simulation software (e.g., CST Microwave Studio, keysight Advanced Design System, etc.) or a linear simulation tool (e.g., MATLAB, etc.) is used to perform simulation based on the second insertion loss value to obtain the S parameter.

The embodiment provides a method for processing a high-speed signal, which is used for acquiring the type of an object to be tested selected by a user in a test process, wherein the type of the object to be tested comprises a main board or an additional card; calculating to obtain a second insertion loss value according to the total link loss value and a link loss value of a processing device for removing high-speed signals in the test link after placing the object to be tested; and simulating according to the second insertion loss value to obtain an S parameter. By the method, when a user tests hardware, different S parameters are generated according to different test object types, and adjustment is not needed in a mode of adjusting ISI board lines. In the prior art, the loss step length of each line is 0.5dB, the required loss is in the middle of two lines, the required loss cannot be accurately constructed, the step length problem does not exist in a calculation mode, and the required loss can be accurately constructed.

Fig. 7 is a schematic structural diagram of a high-speed signal processing device provided in the present application, and as shown in fig. 7, a high-speed signal processing device 500 includes:

the obtaining module 511 is configured to obtain a total link loss value allowed by a PCIE version of the high-speed serial computer expansion bus standard selected by a user;

the simulation module 512 is configured to perform simulation according to the total link loss value to obtain an S parameter;

the adjusting module 513 is configured to adjust the input signal according to the S parameter, to obtain an adjusted signal;

and an output module 514, configured to output the adjusted signal, where the adjusted signal is used to test the test link.

Optionally, the simulation module 512 is configured to:

Optionally, the simulation module 512 is further configured to:

and carrying out simulation according to the object to be tested and the total link loss value to obtain the S parameter.

Optionally, the simulation module 512 is further configured to:

The processing device for high-speed signals provided in the embodiments of the present application is configured to implement the method for processing high-speed signals described in any one of the foregoing method embodiments, and the implementation principle and technical effects are similar, and are not described herein in detail.

Fig. 8 is a networking schematic diagram of a high-speed signal processing system provided in the present application, where, as shown in fig. 8, the high-speed signal processing system includes: the system comprises a code error meter, an oscilloscope, a high-speed signal integrity testing device, a testing clamp set and a cable.

The error code meter is used for measuring bit error rate in digital communication system, evaluating reliability and performance of signal transmission, and can detect and count bit error occurred in transmission process.

Oscilloscopes are used to observe and analyze waveforms of electrical signals. In high-speed signal integrity testing, oscilloscopes can display characteristics of waveform, amplitude, time, noise and the like of signals, and help evaluate signal quality.

The high-speed signal processing device is any one of the device embodiments, and may generate an S parameter according to the set total link loss value, so as to simulate and generate ISI characteristics, and change link loss in the test link. The processing device of the high-speed signal adopts a universal SMA interface and can be adapted to a common error code instrument and an oscilloscope in the market. Through SMA-USB adapter, SMA-SMP adapter, the adapter of SMA-MMPX can adapt different test fixture suites, satisfies the test demand of multiple signal.

Test fixture kits are used to hold and connect devices under test, cables, etc., ensure their stability and repeatability in testing, and create a consistent test environment. In the test networking of PCIe high-speed signal measurement, the test fixture set comprises a consistency load board (Card Location Bracket, CLB) and a consistency base board (Card Blocker Bracket, abbreviated as CBB), wherein the CBB board is used for testing an inserting card, and the CLB board is used for testing a main board.

In the connection of the test calibration network, the error code meter is connected to a high-speed signal processing device through an SMA wire, the high-speed signal processing device is connected to RX of a test fixture CLB, TX of the test fixture CBB is connected to the high-speed signal processing device through a cable, and the high-speed signal processing device is connected to an oscilloscope.

Different types of cables are suitable for different testing scenes, and different cables can be selected according to the interface types of equipment to be tested. Such as SMP-SMP cables, MMPX-MMPX cables, and the like.

The high-speed signal processing system can perform test networking calibration, receiving end test and transmitting end test according to PCIE test standards.

The test calibration procedure is briefly described as follows:

step one: the processing means of the high-speed signal generates the S-parameter according to the loss step size required for the calibration.

Step two: the S parameter is embedded into the test link.

In this step, the test calibration process requires multiple adjustments of the S parameter, with different S parameters embedded into the test link each time the test is adjusted.

Step three: the error detector transmits the pattern.

Step four: the processing device of the high-speed signal generates a processing signal by processing the received code pattern through the S parameter, and sends the processing signal to the test fixture.

Step five: the receiving channel (RX) of the test fixture CLB receives signals and the transmitting channel (TX) of the CBB transmits signals.

Step six: the processing device of the high-speed signal receives the signal sent by the CBB, and sends the signal to the error code instrument after processing the S parameter.

Step seven: and the error code instrument receives the signal and realizes calibration according to the received signal and the transmitted code pattern.

In this step, the received signal is also sent to an oscilloscope where a pressure eye diagram is generated, where the eye height, eye width, jitter, and duty cycle are required to meet the requirements specified in the test specification. And (3) adjusting different S parameters, wherein the pressure eye diagram meets the specification requirement, and the test link calibration is completed when the pressure eye diagram is linearly changed.

During the whole calibration process, the error code meter generates a clean signal, and then precisely controlled Random Jitter (RJ), periodic jitter (SJ), differential mode and common mode noise and intersymbol interference (generated by S parameters through a processing device of a high-speed signal) are superimposed on the signal, wherein RJ, SJ, common mode noise and the like of the signal can be generated by the error code meter. And generating an S parameter according to the maximum loss specified by PCIE version test specification at the receiving end during test as the total link loss and the mode recorded in the processing method of the high-speed signal, and embedding the S parameter into a test link. And testing the loss corresponding to each S parameter to meet the standard requirement, namely generating a pressure eye diagram required by the standard at the receiving end.

The pressure eye diagram required to accurately generate PCIE specifications requires adjustment of many parameters, such as amplitude of the output signal, pre-emphasis, differential mode noise, RJ, SJ, S parameters, etc., to meet eye height, eye width, and jitter requirements. But also the adjustment parameters are mutually restricted, such as the amplitude of the adjustment signal, and the eye width is also affected in addition to the eye height, so that the adjustment of the parameters needs to be repeated to obtain an optimized combination. When in calibration, a training code pattern is sent out to set the tested piece to be in a loop-back state, error rate statistics of loop-back data is automatically carried out, and automatic calibration can be completed in the error code meter. When the tested piece enters a loop-back mode and the error code instrument sends out a signal of a pressure eye pattern, the tested system can send the data received from the RX end back to the error code instrument through the TX end, the error code instrument judges whether the data is correctly received or not through comparing error codes, and the error code rate is required to be smaller than a test standard.

In the calibration process, the transmitter TX and the receiver RX are subjected to test contents such as calibration test and signal tolerance test according to PCIE test standards, and a processing device of a high-speed signal is adopted to generate S parameter to adjust the loss of a link in the whole process.

The processing system for high-speed signals provided by the embodiment can complete test calibration of a transmitter and a receiver and signal integrity test of equipment in the system through the processing device for high-speed signals. The problem that the ISI board interface is frequently changed to select a proper ISI wiring pair in the prior art can be avoided, and the calibration and test efficiency is improved.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A high-speed signal processing apparatus, the apparatus comprising: the system comprises an intersymbol interference (ISI) generating module, a loss embedding module, a power module, a first miniature A-version radio frequency coaxial SMA connector and a second SMA connector;

2. The apparatus of claim 1, wherein the second SMA connector comprises: at least one adapter of an SMA-Universal Serial Bus (USB) adapter, an SMA-miniature P-type radio frequency coaxial (SMP) adapter and an adapter of an SMA-buckle type connector MMPX.

3. The apparatus according to claim 1 or 2, characterized in that the apparatus further comprises: the third SMA connector, the fourth SMA connector and the channel indicator lamp;

the fourth SMA connector is configured to output the new adjusted signal;

4. The apparatus according to claim 1 or 2, characterized in that the apparatus further comprises: a processor;

5. The apparatus of claim 4, wherein the apparatus further comprises: a control switch, a USB interface and/or an Ethernet interface;

6. The apparatus according to claim 1 or 2, wherein the power module comprises an ac-to-dc unit for converting an input ac to dc.

7. A method of processing a high-speed signal, characterized by being applied to the high-speed signal processing apparatus according to any one of claims 1 to 6, the method comprising:

8. The method of claim 7, wherein said performing a simulation based on said total link loss value to obtain an S parameter comprises:

9. The method of claim 7, wherein said performing a simulation based on said total link loss value to obtain an S parameter comprises:

10. A high-speed signal processing system, characterized in that the system comprises a high-speed signal processing device, an error detector, an oscilloscope and a test fixture set according to any one of claims 1 to 6.