CN116774020A - Chip testing system, method, device and storage medium - Google Patents
Chip testing system, method, device and storage medium Download PDFInfo
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Abstract
The invention discloses a chip testing system, a method, a device and a storage medium, relating to the field of chip testing, wherein the system comprises: the system comprises a management control module, a signal switching module, a signal relay module, a first insertion loss simulation module and a multiplexer group; the management control module is connected with the multiplexer group and used for constructing a target communication link by controlling the on-off state of a port of the multiplexer group and sending a test signal sent by the central processing unit to a chip to be tested through the target communication link; according to the technical scheme, the simulation link construction under multiple test scenes in the server is realized, the test results cover multiple service scenes of the auxiliary operation device in the server, the comprehensiveness of the test results is improved, meanwhile, the chip test system also ensures that the test results under all communication links are acquired based on the same functional components, and the accuracy of the test results is improved.
Description
Technical Field
The present invention relates to the field of chip testing, and in particular, to a chip testing system, method, apparatus, and storage medium.
Background
Existing servers, particularly servers for cloud computing services, typically employ PCIe (peripheral component interconnect express, high speed serial computer expansion bus standard) tree architecture consisting of a central processor, switching chips and auxiliary computing devices.
In order to avoid the influence of the auxiliary computing device with poor performance on the service performance of the server cluster, functional test and performance test are required to be carried out on the computing chip of the auxiliary computing device after the production of the computing chip of the auxiliary computing device is completed so as to enable the computing chip to meet the performance requirement of the server; at present, a test machine for operation chips on a production line, for example, a test machine for system testing and burn-in testing is usually developed based on a desktop host, and related testing is completed through a fixed exchange chip.
However, such a test mode cannot completely cover the service scenario of the auxiliary computing device in the server, and the test result has a serious coverage rate deficiency problem.
Disclosure of Invention
The invention provides a chip test system, a method, a device and a storage medium, which are used for solving the problem of coverage rate deficiency of service scenes in chip test.
According to an aspect of the present invention, there is provided a chip test system including: the system comprises a management control module, a signal switching module, a signal relay module, a first insertion loss simulation module and a multiplexer group; the multiplexer group comprises a first multiplexer and a second multiplexer; the first multiplexer is connected with the central processing unit and the second multiplexer, and the second multiplexer is connected with the chip to be tested;
the management control module is connected with the multiplexer group and used for constructing a target communication link by controlling the on-off state of a port of the multiplexer group and sending a test signal sent by the central processing unit to the chip to be tested through the target communication link;
the signal switching module, the signal relay module and the first insertion loss simulation module are connected with the first multiplexer and the second multiplexer and used for transmitting the test signals.
The multiplexer group further includes a third multiplexer; the third multiplexer is respectively connected with the first multiplexer, the second multiplexer, the signal switching module, the signal relay module and the first insertion loss simulation module; the management control module is specifically configured to construct a first communication link and/or a second communication link by controlling the on-off state of a port of the multiplexer set; the first communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the first insertion loss simulation module and the second multiplexer; the second communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the first insertion loss simulation module and the second multiplexer.
The chip test system further comprises a second insertion loss simulation module; the second insertion loss simulation module has the same insertion loss value as the first insertion loss simulation module and different structure types; the second insertion loss simulation module is respectively connected with the second multiplexer and the third multiplexer; the management control module is specifically configured to construct a third communication link and/or a fourth communication link by controlling the on-off state of the ports of the multiplexer set; the third communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the second insertion loss simulation module and the second multiplexer; the fourth communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the second insertion loss simulation module and the second multiplexer.
The chip test system further comprises a third insertion loss simulation module; the third insertion loss simulation module and the first insertion loss simulation module are different in insertion loss value and identical in structure type; the third insertion loss simulation module is respectively connected with the second multiplexer and the third multiplexer; the management control module is specifically configured to further construct a fifth communication link and/or a sixth communication link by controlling a port on-off state of the multiplexer set; the fifth communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the third insertion loss simulation module and the second multiplexer; the sixth communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the third insertion loss simulation module and the second multiplexer.
The multiplexer group further includes a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, and a seventh multiplexer; the signal switching module is respectively connected with the fourth multiplexer and the fifth multiplexer; the signal relay module is respectively connected with the sixth multiplexer and the seventh multiplexer; the management control module is specifically configured to construct a seventh communication link and/or an eighth communication link by controlling a port on-off state of the multiplexer set; the seventh communication link is sequentially composed of the first multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the third multiplexer and the second multiplexer; the eighth communication link is composed of the first multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the third multiplexer and the second multiplexer in sequence.
The management control module is specifically configured to further construct a ninth communication link and/or a tenth communication link by controlling a port on-off state of the multiplexer set; the ninth communication link is sequentially composed of the first multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the third multiplexer, the first insertion loss simulation module and the second multiplexer; the tenth communication link is sequentially composed of the first multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the third multiplexer, the first insertion loss simulation module and the second multiplexer.
The management control module is connected with the central processing unit and is also used for constructing a target communication link according to the test type identifier sent by the central processing unit or constructing a target communication link according to the communication link identifier sent by the central processing unit.
According to another aspect of the present invention, there is provided a chip testing method, including:
the management control module constructs a target communication link by controlling the on-off state of the port of the multiplexer group;
and the management control module sends the test signal sent by the central processing unit to the chip to be tested through the target communication link.
According to another aspect of the present invention, there is provided a chip testing apparatus including:
the target communication link acquisition module is configured in the management control module and is used for constructing a target communication link by controlling the on-off state of the port of the multiplexer group;
and the test signal management module is configured in the management control module and is used for sending the test signal sent by the central processing unit to the chip to be tested through the target communication link.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a chip test method according to any one of the embodiments of the present invention.
According to the technical scheme, the chip test system comprises the management control module, the signal switching module, the signal relay module, the first insertion loss simulation module and the multiplexer group, different types of communication links are constructed through controlling the on-off state of the ports of the multiplexer group, and test signals are transmitted based on the communication links, so that the simulation link construction under multiple test scenes in the server is realized, the test results cover multiple service scenes of the auxiliary computing device in the server, the comprehensiveness of the test results is improved, meanwhile, the chip test system uses internal functional components to construct different communication links, the transition occupation of test resources is avoided, the test efficiency is improved, the test results under all the communication links are ensured to be acquired based on the same functional components, and the accuracy of the test results is improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip test system according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a chip test system according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a chip test system according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a chip test system according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a chip test system according to a second embodiment of the present invention;
FIG. 6 is a flow chart of a method for testing a chip according to a third embodiment of the present invention;
fig. 7 is a block diagram of a chip testing apparatus according to a fourth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a schematic structural diagram of a chip testing system according to a first embodiment of the present invention, as shown in fig. 1, the system includes: the system comprises a management control module 100, a signal switching module 200, a signal relay module 300, a first insertion loss simulation module 401 and a multiplexer group; the multiplexer group comprises a first multiplexer 501 and a second multiplexer 502; the first multiplexer 501 is connected with the central processing unit and the second multiplexer 502, and the second multiplexer 502 is connected with the chip to be tested.
A Multiplexer (Mux) is a signal multiplexing device provided with a plurality of signal input channels and a plurality of signal output channels for transmission of analog signals or digital signals; as shown in fig. 1, an input end of the first multiplexer 501 is connected with a central processing unit (Central Processing Unit, CPU) and is used for receiving a test signal sent by the CPU; the output end of the first multiplexer 501 is respectively connected with the signal switching module 200, the signal relay module 300, the first insertion loss simulation module 401 and the second multiplexer 502, and is used for sending the acquired test signals to the modules through output ports which are matched one by one.
The input end of the second multiplexer 502 is respectively connected with the signal switching module 200, the signal relay module 300, the first insertion loss simulation module 401 and the first multiplexer 501, and is used for receiving test signals sent by the modules through input ports matched one by one; the output end of the second multiplexer 502 is connected with the chip to be tested and is used for sending the acquired test signal to the chip to be tested; the chip to be tested may include an operation chip such as an AI (Artificial Intelligence, AI) accelerator card and/or a graphics processor (Graphics Processing Unit, GPU). In addition, the central processor in fig. 1 may be a processor in a real server or a processor in a terminal device, so that the central processor of the server is simulated by the central processor of the terminal device.
The management control module 100 is connected with each multiplexer in the multiplexer group and is used for controlling the port on-off state of each multiplexer; in the embodiment of the invention, in order to ensure the unidirectional property of the test signal transmission, an input port and an output port are respectively opened for each multiplexer involved in the current test signal transmission process, and all the input ports and the output ports of each multiplexer not involved in the current test signal transmission process are closed; the management control module 100 constructs different communication links by controlling the on-off states of ports of the multiplexers, so as to transmit test signals sent by the central processing unit to the chip to be tested based on different transmission media, and simulate various communication scenes between the central processing unit of the server and the auxiliary computing device comprising the chip to be tested.
The signal switching module 200, the signal relay module 300 and the first insertion loss simulation module 401 are all connected with the first multiplexer 501 and the second multiplexer 502, and are used for transmitting the test signal. Specifically, the signal switching module 200 is configured to provide an expansion and aggregation function for the central processing unit, and the CPU in the server may connect more auxiliary computing devices including the chip to be tested to the current PCIe port through connection with the signal switching module 200, where the signal switching module 200 may specifically include functional components such as a switch switching card; as shown in fig. 1, the signal switching module 200 is respectively connected to the first multiplexer 501 and the second multiplexer 502, and is configured to forward the test signal sent by the first multiplexer 501 to the second multiplexer 502.
The signal relay module 300 has the function of signal transfer and the function of enhancing the transmission signal, particularly when the transmission distance between the CPU and the auxiliary operation device comprising the chip to be tested is long, the CPU in the server can ensure stable communication with the auxiliary operation device by connecting the signal relay module 300, and the signal relay module 300 can specifically comprise functional components such as a driver transfer card and/or a timer transfer card; as shown in fig. 1, the signal relay module 300 is respectively connected to the first multiplexer 501 and the second multiplexer 502, and is configured to forward the test signal sent by the first multiplexer 501 to the second multiplexer 502; in the embodiment of the present invention, optionally, the component types of the signal forwarding module 200 and the signal relaying module 300 are not specifically limited.
Because of the size limitation of the server in reality, the CPU of the server and the auxiliary computing device including the chip to be tested often need to be connected through a longer PCB (Printed Circuit Board ) trace, and the actual link insertion loss is far higher than that in the conventional test environment, so the first insertion loss simulation module 401 is a functional module with fixed insertion loss value and known, and is used for simulating the actual insertion loss on the transmission link in the server; the first insertion loss simulation module 401 may specifically include a Cable (Cable) with a known insertion loss or a PCIe bridge card with a known insertion loss.
In fig. 1, the management control module 100 can construct four communication links by managing the on-off states of the ports of the first multiplexer 501 and the second multiplexer 502, that is, the communication link a is "the first multiplexer 501→the second multiplexer 502", which is used for simulating a communication scene that the CPU and the auxiliary computing device in the server are directly connected through the PCIe bus; the communication link B is a first multiplexer 501, a signal switching module 200 and a second multiplexer 502, and is used for simulating a scene that a CPU in a server is in communication connection with auxiliary operation equipment through the signal switching module 200 such as a switch switching card; the communication link C is a first multiplexer 501, a signal relay module 300 and a second multiplexer 502, and is used for simulating a scene of communication connection of the signal relay module 300 such as a repeater adapter card when the transmission distance between a CPU and auxiliary operation equipment in the server is far; the communication link D is "first multiplexer 501→first insertion loss simulation module 401→second multiplexer 502", and is used for simulating a communication scene in which a larger link insertion loss exists between the CPU and the auxiliary operation device in the server.
In particular, for each communication link, the management control module 100 may turn on each communication link in a polling manner according to a preset test period, and when each communication link is turned on, ensure that other communication links are turned off, so as to perform a test on a chip to be tested under multiple scenarios through different communication links.
As shown in fig. 2, optionally, in an embodiment of the present invention, the multiplexer group further includes a third multiplexer 503; the third multiplexer 503 is connected to the first multiplexer 501, the second multiplexer 502, the signal switching module 200, the signal relay module 300, and the first insertion loss analog module 401, respectively; the management control module 100 is specifically configured to construct a first communication link and/or a second communication link by controlling a port on-off state of the multiplexer set; the first communication link is composed of the first multiplexer 501, the signal switching module 200, the third multiplexer 503, the first insertion loss analog module 401, and the second multiplexer 502; the second communication link is composed of the first multiplexer 501, the signal relay module 300, the third multiplexer 503, the first insertion loss analog module 401, and the second multiplexer 502.
Specifically, after the third multiplexer 503 is added in the chip test system, the management control module 100 configures the acquired first communication link as "the first multiplexer 501→the signal switching module 200→the third multiplexer 503→the first insertion loss simulation module 401→the second multiplexer 502" through controlling the on-off states of the ports of the first multiplexer 501, the second multiplexer 502 and the third multiplexer 503, and is used for simulating a communication scene that the CPU and the auxiliary operation equipment in the server are in communication connection through the signal switching module 200 and the link insertion loss is larger; the second communication link acquired by configuration is composed of a first multiplexer 501, a signal relay module 300, a third multiplexer 503, a first insertion loss simulation module 401 and a second multiplexer 502, and is used for simulating a communication scene that a CPU and auxiliary operation equipment in a server are in communication connection through the signal relay module 300, and the link insertion loss is large; therefore, the communication scene between the CPU and the auxiliary operation device in the server simulated by the chip test system is expanded, and the test diversity of the chip to be tested is improved.
In addition, after the management control module 100 obtains the test results of each communication link fed back by the chip to be tested through the second multiplexer 502, by comparing the test results of the first communication link with the test results of the communication link a, the communication link B and the communication link D, the performance evaluation results of the chip to be tested for the signal switching module 200 and the first insertion loss simulation module 401, that is, whether the performance of the chip to be tested is affected by the signal switching module 200 or the first insertion loss simulation module 401, and the respective influence proportion can be obtained; similarly, by comparing the second communication link with the test results of the communication link a, the communication link C and the communication link D, the performance evaluation results of the chip to be tested for the signal relay module 300 and the first insertion loss simulation module 401, that is, whether the performance of the chip to be tested is affected by the signal relay module 300 or the first insertion loss simulation module 401, and the respective influence proportion, can be obtained.
As shown in fig. 3, optionally, in an embodiment of the present invention, the chip test system further includes a second insertion loss simulation module 402; the second insertion loss simulation module 402 has the same insertion loss value as the first insertion loss simulation module 401, and has different structure types; the second insertion loss simulation module 402 is connected to the second multiplexer 502 and the third multiplexer 503 respectively; the management control module 100 is specifically further configured to construct a third communication link and/or a fourth communication link by controlling the on-off state of the ports of the multiplexer set; wherein the third communication link is composed of the first multiplexer 501, the signal switching module 200, the third multiplexer 503, the second insertion loss analog module 402, and the second multiplexer 502; the fourth communication link is composed of the first multiplexer 501, the signal relay module 300, the third multiplexer 503, the second insertion loss simulation module 402, and the second multiplexer 502.
Specifically, taking the above technical solution as an example, the first insertion loss simulation module 401 may be a Cable (Cable) with a known insertion loss, the second insertion loss simulation module 402 is a PCIe bridge card with a known insertion loss, or the first insertion loss simulation module 401 is a PCIe bridge card with a known insertion loss, the second insertion loss simulation module 402 is a Cable with a known insertion loss, and insertion loss values of the first insertion loss simulation module 401 and the second insertion loss simulation module 402 are the same; the third communication link obtained by configuration is formed by a first multiplexer 501, a signal switching module 200, a third multiplexer 503, a second insertion loss simulation module 402 and a second multiplexer 502, and simulates a communication scene that a CPU and auxiliary operation equipment in a server are in communication connection through the signal switching module 200 and the insertion loss of the link is large; in addition, the management control module 100 may also determine whether the different types of insertion loss simulation modules affect the performance of the chip to be tested while the signal switching module 200 is accessed by comparing the test result of the third communication link with the test result of the first communication link.
Similarly, the fourth communication link is formed by the first multiplexer 501, the signal relay module 300, the third multiplexer 503, the second insertion loss simulation module 402 and the second multiplexer 502, and simulates a communication scene that the CPU and the auxiliary operation equipment in the server are in communication connection through the signal relay module 300, and the insertion loss of the link is larger; the management control module 100 may also determine whether the different types of insertion loss simulation modules affect the performance of the chip to be tested while the signal relay module 300 is being accessed by comparing the test result of the fourth communication link with the test result of the second communication link.
As shown in fig. 4, optionally, in an embodiment of the present invention, the chip testing system further includes a third insertion loss simulation module 403; the third insertion loss simulation module 403 and the first insertion loss simulation module 401 have different insertion loss values and the same structure type; the third insertion loss simulation module 403 is connected to the second multiplexer 502 and the third multiplexer 503, respectively; the management control module 100 is specifically further configured to construct a fifth communication link and/or a sixth communication link by controlling the on-off state of the ports of the multiplexer set; wherein the fifth communication link is composed of the first multiplexer 501, the signal switching module 200, the third multiplexer 503, the third insertion loss analog module 403, and the second multiplexer 502; the sixth communication link is composed of the first multiplexer 501, the signal relay module 300, the third multiplexer 503, the third insertion loss simulation module 403, and the second multiplexer 502.
Specifically, taking the above technical solution as an example, the first insertion loss simulation module 401 and the third insertion loss simulation module 403 may be both cables (Cable), or PCIe bridge cards, and insertion loss values of the two modules are different; for example, the first insertion loss simulation module 401 is configured to simulate an actual link insertion loss in the server, and the third insertion loss simulation module 403 is configured to simulate a link insertion loss in a more severe environment, that is, the insertion loss value of the third insertion loss simulation module 403 is greater than that of the first insertion loss simulation module 401; the fifth communication link obtained by configuration is formed by a first multiplexer 501, a signal switching module 200, a third multiplexer 503, a third insertion loss simulation module 403 and a second multiplexer 502, and simulates a communication scene that a CPU and auxiliary operation equipment in a server are in communication connection through the signal switching module 200, and the insertion loss of the link is extremely large; in addition, the management control module 100 may also determine whether the insertion loss simulation modules with different values affect the performance of the chip to be tested while the signal switching module 200 is accessed by comparing the test result of the fifth communication link with the test result of the first communication link.
Similarly, the sixth communication link is formed by the first multiplexer 501, the signal relay module 300, the third multiplexer 503, the third insertion loss simulation module 403 and the second multiplexer 502, and the sixth communication link simulates a communication scene that the CPU in the server is in communication connection with the auxiliary computing device through the signal relay module 300, and the insertion loss of the link is extremely large; in addition, the management control module 100 may also determine whether the insertion loss simulation module with different values affects the performance of the chip to be tested while the signal relay module 300 is accessed by comparing the test result of the sixth communication link with the test result of the second communication link.
Optionally, in an embodiment of the present invention, the management control module 100 is connected to the central processing unit, and is further configured to construct a target communication link according to a test type identifier sent by the central processing unit, or construct a target communication link according to a communication link identifier sent by the central processing unit. Specifically, for the selection of each communication link, the central processing unit may directly send the communication link identifier to the management control module 100, that is, the management control module 100 directly constructs a matched target communication link according to the communication link requirement sent by the central processing unit; the matched target communication link may also be constructed by the management control module 100 for different test types according to the test type identifier sent by the central processing unit to the management control module 100, for example, a functional test, a performance test, a stress test, an aging test, and the like.
For example, when the chip to be tested is subjected to pressure test, test signal transmission is performed through a communication link sequentially formed by the first multiplexer 501, the signal switching module 200, the signal relay module 300, the first insertion loss simulation module 401 and the second multiplexer 502, so as to test the accuracy of a data processing result of the chip to be tested under a transmission medium with a relatively complex structure; when the performance test is performed on the chip to be tested, the test signal is transmitted through the communication link sequentially formed by the first multiplexer 501 and the second multiplexer 502, so that the data processing efficiency of the chip to be tested under the transmission medium with a simpler structure is tested. And constructing a matched target communication link through the acquired test type identifier and the communication link identifier, so that the targeted test of the specific component link under different test requirements is realized, and the test efficiency of the chip to be tested is improved.
According to the technical scheme, the chip test system comprises the management control module, the signal switching module, the signal relay module, the first insertion loss simulation module and the multiplexer group, different types of communication links are constructed through controlling the on-off state of the ports of the multiplexer group, and test signals are transmitted based on the communication links, so that the simulation link construction under multiple test scenes in the server is realized, the test results cover multiple service scenes of the auxiliary computing device in the server, the comprehensiveness of the test results is improved, meanwhile, the chip test system uses internal functional components to construct different communication links, the transition occupation of test resources is avoided, the test efficiency is improved, the test results under all the communication links are ensured to be acquired based on the same functional components, and the accuracy of the test results is improved.
Example two
Fig. 5 is a block diagram of a chip testing system according to a second embodiment of the present invention. On the basis of the technical scheme, the multiplexer group further comprises a fourth multiplexer 504, a fifth multiplexer 505, a sixth multiplexer 506 and a seventh multiplexer 507; the signal switching module 200 is connected to the fourth multiplexer 504 and the fifth multiplexer 505, respectively; the signal relay module 300 is connected to the sixth multiplexer 506 and the seventh multiplexer 507, respectively.
Specifically, since the signal switching module 200 and the signal relay module 300 do not have the gating function of the transmission channel, in order to further increase the diversity of the communication link, it is necessary to add multiplexers at two ends of the signal switching module 200 and the signal relay module 300, respectively, that is, to add the fourth multiplexer 504 and the fifth multiplexer 505 at two ends of the signal switching module 200, and to add the sixth multiplexer 506 and the seventh multiplexer 507 at two ends of the signal relay module 300, respectively.
The management control module 100 is specifically configured to construct a seventh communication link and/or an eighth communication link by controlling the port on-off state of the multiplexer set. As shown in fig. 5, the seventh communication link is sequentially composed of the first multiplexer 501, the fourth multiplexer 504, the signal switching module 200, the fifth multiplexer 505, the sixth multiplexer 506, the signal relay module 300, the seventh multiplexer 507, the third multiplexer 503, and the second multiplexer 502.
The seventh communication link simulates a communication scene that the CPU and the auxiliary computing device in the server are sequentially connected through the signal switching module 200 and the signal relay module 300 in a communication manner; in addition, the management control module 100 may determine whether the performance of the chip to be tested is affected by continuing to access the signal relay module 300 at the rear end thereof while the signal transit module 200 is accessed by comparing the test result of the seventh communication link with the test results of the communication link B and the communication link C; it may also be determined whether the signal relay module 300 is connected and the front end of the signal relay module is connected to the signal transfer module 200, so that the performance of the chip to be tested is affected.
As shown in fig. 5, the eighth communication link is sequentially composed of the first multiplexer 501, the sixth multiplexer 506, the signal relay module 300, the seventh multiplexer 507, the fourth multiplexer 504, the signal switching module 200, the fifth multiplexer 505, the third multiplexer 503, and the second multiplexer 502.
The eighth communication link simulates a communication scene that the CPU and the auxiliary computing device in the server are sequentially connected through the signal relay module 300 and the signal transfer module 200 in a communication manner; in addition, the management control module 100 may determine whether the signal relay module 300 is connected to the signal switching module 200 at the rear end thereof while the performance of the chip to be tested is affected by comparing the test result of the eighth communication link with the test results of the communication link B and the communication link C; it may also be determined whether the signal relay module 300 is continuously connected to the front end of the signal relay module 200 while the signal relay module 200 is connected thereto, which may affect the performance of the chip to be tested.
Optionally, in an embodiment of the present invention, the management control module 100 is specifically further configured to construct a ninth communication link and/or a tenth communication link by controlling a port on-off state of the multiplexer set. As shown in fig. 5, the ninth communication link is sequentially composed of the first multiplexer 501, the fourth multiplexer 504, the signal switching module 200, the fifth multiplexer 505, the sixth multiplexer 506, the signal relay module 300, the seventh multiplexer 507, the third multiplexer 503, the first insertion loss simulation module 401, and the second multiplexer 502. The ninth communication link simulates a communication scene that a CPU and auxiliary operation equipment in the server are sequentially connected with each other through the signal switching module 200 and the signal relay module 300 in a communication way, and a larger link insertion loss exists; in addition, the management control module 100 may determine whether the performance of the chip to be tested is affected by continuing to access the first insertion loss simulation module 401 at the rear end thereof while having sequentially accessed the signal switching module 200 and the signal relay module 300 by comparing the test result of the ninth communication link with the test result of the seventh communication link.
The tenth communication link is sequentially composed of the first multiplexer 501, the sixth multiplexer 506, the signal relay module 300, the seventh multiplexer 507, the fourth multiplexer 504, the signal switching module 200, the fifth multiplexer 505, the third multiplexer 503, the first insertion loss simulation module 401, and the second multiplexer 502. The tenth communication link simulates a communication scene that a CPU and auxiliary operation equipment in the server are sequentially connected with each other through the signal relay module 300 and the signal transfer module 200 in a communication way, and a larger link insertion loss exists; in addition, the management control module 100 may determine whether the performance of the chip to be tested is affected by continuing to access the first insertion loss simulation module 401 at the rear end thereof while having sequentially accessed the signal relay module 300 and the signal transit module 200 by comparing the test result of the tenth communication link with the test result of the eighth communication link.
According to the technical scheme of the embodiment of the invention, the chip test system constructs the communication link simultaneously comprising any plurality of the signal switching module, the signal relay module and the first insertion loss simulation module by adding the fourth multiplexer, the fifth multiplexer, the sixth multiplexer and the seventh multiplexer, and changes the relative positions of any plurality of modules in different communication links, so that the communication scene between the CPU and the auxiliary operation device in the server simulated by the chip test system is further expanded, and the test diversity of the chip to be tested is improved.
Example III
Fig. 6 is a flowchart of a chip testing method according to a third embodiment of the present invention, where the method may be performed by a chip testing device, which may be implemented in hardware and/or software, and the chip testing device may be configured in the chip testing system according to the first or second embodiment. As shown in fig. 6, the method includes:
s601, the management control module constructs a target communication link by controlling the port on-off state of the multiplexer group.
S602, the management control module sends a test signal sent by the central processing unit to the chip to be tested through the target communication link.
According to the technical scheme, the chip test system comprises the management control module, the signal switching module, the signal relay module, the first insertion loss simulation module and the multiplexer group, different types of communication links are constructed through controlling the on-off state of the ports of the multiplexer group, and test signals are transmitted based on the communication links, so that the simulation link construction under multiple test scenes in the server is realized, the test results cover multiple service scenes of the auxiliary computing device in the server, the comprehensiveness of the test results is improved, meanwhile, the chip test system uses internal functional components to construct different communication links, the transition occupation of test resources is avoided, the test efficiency is improved, the test results under all the communication links are ensured to be acquired based on the same functional components, and the accuracy of the test results is improved.
Example IV
Fig. 7 is a block diagram of a chip testing apparatus according to a fourth embodiment of the present invention, where the apparatus specifically includes:
the target communication link acquisition module 701 is configured in the management control module, and is configured to construct a target communication link by controlling the on-off state of the ports of the multiplexer set;
the test signal management module 702 is configured in the management control module, and is configured to send a test signal sent by the central processing unit to the chip to be tested through the target communication link.
According to the technical scheme, the chip test system comprises the management control module, the signal switching module, the signal relay module, the first insertion loss simulation module and the multiplexer group, different types of communication links are constructed through controlling the on-off state of the ports of the multiplexer group, and test signals are transmitted based on the communication links, so that the simulation link construction under multiple test scenes in the server is realized, the test results cover multiple service scenes of the auxiliary computing device in the server, the comprehensiveness of the test results is improved, meanwhile, the chip test system uses internal functional components to construct different communication links, the transition occupation of test resources is avoided, the test efficiency is improved, the test results under all the communication links are ensured to be acquired based on the same functional components, and the accuracy of the test results is improved.
The device can execute the chip testing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be referred to the chip testing method provided in any embodiment of the present invention.
Example five
In some embodiments, the chip test method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as a memory unit. In some embodiments, part or all of the computer program may be loaded and/or installed onto the heterogeneous hardware accelerator via the ROM and/or the communication unit. One or more of the steps of the chip test method described above may be performed when the computer program is loaded into RAM and executed by a processor. Alternatively, in other embodiments, the processor may be configured to perform the chip test method in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or a trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A chip testing system, comprising: the system comprises a management control module, a signal switching module, a signal relay module, a first insertion loss simulation module and a multiplexer group; the multiplexer group comprises a first multiplexer and a second multiplexer; the first multiplexer is connected with the central processing unit and the second multiplexer, and the second multiplexer is connected with the chip to be tested;
the management control module is connected with the multiplexer group and used for constructing a target communication link by controlling the on-off state of a port of the multiplexer group and sending a test signal sent by the central processing unit to the chip to be tested through the target communication link;
the signal switching module, the signal relay module and the first insertion loss simulation module are connected with the first multiplexer and the second multiplexer and used for transmitting the test signals.
2. The chip test system of claim 1, wherein the multiplexer bank further comprises a third multiplexer; the third multiplexer is respectively connected with the first multiplexer, the second multiplexer, the signal switching module, the signal relay module and the first insertion loss simulation module;
The management control module is specifically configured to construct a first communication link and/or a second communication link by controlling the on-off state of a port of the multiplexer set;
the first communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the first insertion loss simulation module and the second multiplexer; the second communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the first insertion loss simulation module and the second multiplexer.
3. The chip test system of claim 2, further comprising a second insertion loss simulation module; the second insertion loss simulation module has the same insertion loss value as the first insertion loss simulation module and different structure types; the second insertion loss simulation module is respectively connected with the second multiplexer and the third multiplexer;
the management control module is specifically configured to construct a third communication link and/or a fourth communication link by controlling the on-off state of the ports of the multiplexer set;
The third communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the second insertion loss simulation module and the second multiplexer; the fourth communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the second insertion loss simulation module and the second multiplexer.
4. The chip test system of claim 2, further comprising a third insertion loss simulation module; the third insertion loss simulation module and the first insertion loss simulation module are different in insertion loss value and identical in structure type; the third insertion loss simulation module is respectively connected with the second multiplexer and the third multiplexer;
the management control module is specifically configured to further construct a fifth communication link and/or a sixth communication link by controlling a port on-off state of the multiplexer set;
the fifth communication link is composed of the first multiplexer, the signal switching module, the third multiplexer, the third insertion loss simulation module and the second multiplexer; the sixth communication link is composed of the first multiplexer, the signal relay module, the third multiplexer, the third insertion loss simulation module and the second multiplexer.
5. The chip test system of claim 2, wherein the multiplexer set further comprises a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, and a seventh multiplexer; the signal switching module is respectively connected with the fourth multiplexer and the fifth multiplexer; the signal relay module is respectively connected with the sixth multiplexer and the seventh multiplexer;
the management control module is specifically configured to construct a seventh communication link and/or an eighth communication link by controlling a port on-off state of the multiplexer set;
the seventh communication link is sequentially composed of the first multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the third multiplexer and the second multiplexer;
the eighth communication link is composed of the first multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the third multiplexer and the second multiplexer in sequence.
6. The chip test system according to claim 5, wherein the management control module is further configured to construct a ninth communication link and/or a tenth communication link by controlling a port on-off state of the multiplexer group;
the ninth communication link is sequentially composed of the first multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the third multiplexer, the first insertion loss simulation module and the second multiplexer;
the tenth communication link is sequentially composed of the first multiplexer, the sixth multiplexer, the signal relay module, the seventh multiplexer, the fourth multiplexer, the signal switching module, the fifth multiplexer, the third multiplexer, the first insertion loss simulation module and the second multiplexer.
7. The chip test system according to any one of claims 1-6, wherein the management control module is further configured to construct a target communication link according to a test type identifier sent by the central processor, or construct a target communication link according to a communication link identifier sent by the central processor.
8. A method of testing a chip, wherein the chip testing system of claim 1 is applied, comprising:
the management control module constructs a target communication link by controlling the on-off state of the port of the multiplexer group;
and the management control module sends the test signal sent by the central processing unit to the chip to be tested through the target communication link.
9. A chip testing apparatus, wherein the chip testing system of claim 1 is applied, comprising:
the target communication link acquisition module is configured in the management control module and is used for constructing a target communication link by controlling the on-off state of the port of the multiplexer group;
and the test signal management module is configured in the management control module and is used for sending the test signal sent by the central processing unit to the chip to be tested through the target communication link.
10. A computer readable storage medium storing computer instructions for causing a processor to execute the chip test method of claim 8.
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