CN109684139B - Test fixture of PCIe4.0 slot - Google Patents
Test fixture of PCIe4.0 slot Download PDFInfo
- Publication number
- CN109684139B CN109684139B CN201811476055.4A CN201811476055A CN109684139B CN 109684139 B CN109684139 B CN 109684139B CN 201811476055 A CN201811476055 A CN 201811476055A CN 109684139 B CN109684139 B CN 109684139B
- Authority
- CN
- China
- Prior art keywords
- circuit board
- signal
- slot
- tested
- test fixture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 28
- 230000009977 dual effect Effects 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a test fixture of PCIe4.0 slot, the PCIe4.0 slot to be tested is dual in-line package, the test fixture includes: the circuit comprises a first circuit board and a second circuit board, wherein the first circuit board is welded with a PCIe4.0 slot to be tested, all signal ends of the PCIe4.0 slot to be tested are led out of all signal wires in a single-ended mode respectively, the lengths of the signal wires are equal, and the other end of each signal wire is connected with an SMA connector; the second circuit board is welded with a golden finger, the golden finger is matched with a PCIe4.0 slot to be tested, all signal ends of the golden finger are led out of all signal wires in a single-ended mode, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector. The invention can test the performance parameters of the PCIe4.0 slot.
Description
Technical Field
The invention relates to the technical field of signal transmission, in particular to a test fixture for a PCIe4.0 slot.
Background
With the development of modern processor technology, the use of high speed differential buses instead of parallel buses is a great trend in the interconnect field. High speed differential signaling allows for a higher clock frequency than single ended parallel signaling, thereby using fewer signal lines to achieve a bus bandwidth that would have previously required many single ended parallel data signals.
PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard that offers many improvements over previous standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical size, better scaling of bus device performance, more detailed error detection and reporting mechanisms (advanced error reporting, AER) and native hot plug functionality. Newer versions of the PCIe standard provide hardware support for I/O virtualization.
The PCI SIG approved PCIe version 1.0 of the 4.0 specification in 2017, month 9. The single channel transmission rate is changed into 16GT/s, the coding format is still 128b/130b, and the actual transmission bandwidth is increased by 1.969 GB/s. A communication bridge between the processor and the chipset can also be attached to PCIe4.0 and has larger bandwidth, both AMD and Intel are unidirectional 3.98GB/s and bidirectional 7.9GB/s at present, and the communication bridge can be doubled after PCIe4.0 is upgraded.
At present, PCIe4.0 is still in a new technology, and PCIe4.0 slots released by various connector manufacturers are not perfect in performance, and need to be actually measured and verified. Most of existing PCIe test jigs are PCIe3.0 jigs, details noticed in design are few, influence on signals is large when the existing PCIe test jigs are directly applied to PCIe4.0, and actual performance of a PCIe4.0 slot cannot be embodied.
Disclosure of Invention
In order to solve the above problems, the present invention provides a test fixture for PCIe4.0 socket, which can test performance parameters of the PCIe4.0 socket itself.
The invention provides a test fixture of PCIe4.0 slot, the PCIe4.0 slot to be tested is dual in-line package, the test fixture includes: a first circuit board and a second circuit board, wherein,
the first circuit board is welded with a PCIe4.0 slot to be tested, all signal ends of the PCIe4.0 slot to be tested are led out of all signal wires in a single-ended mode, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector;
the second circuit board is welded with a golden finger, the golden finger is matched with a PCIe4.0 slot to be tested, all signal ends of the golden finger are led out of all signal wires in a single-ended mode, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector.
Optionally, the signal line length of the first circuit board is equal to the signal line length of the second circuit board.
Optionally, two sides of each signal line of the first circuit board and the second circuit board are respectively provided with a row of ground holes.
Optionally, the hole spacing of each row of ground holes is 1 mm.
Optionally, the first circuit board and the second circuit board are respectively provided with a 2X Thru line, the 2X Thru line of the first circuit board is located at the opposite side of the PCIe4.0 slot to be tested, a certain angle is provided with respect to the opposite side edge of the first circuit board, the 2X Thru line of the second circuit board is located at the opposite side of the gold finger, a certain angle is provided with respect to the opposite side edge of the second circuit board, the 2X Thru lines of the first circuit board and the second circuit board have the same angle, and the length is the sum of the length of the signal line of the first circuit board and the length of the signal line of the second circuit board.
Optionally, the positions of the first circuit board, which are located at the signal ends of the PCIe4.0 slot to be tested, are subjected to hollowing processing of an anti-pad.
Optionally, the first circuit board is hollowed at the position of each signal end of the PCIe4.0 slot to be tested by using an ellipse.
Optionally, the first circuit board and the second circuit board are multilayer circuit boards, and all signal lines are arranged in an intermediate layer.
Optionally, the PCB material of the first circuit board and the second circuit board is selected to be M6 grade.
Optionally, the copper foil type of the first circuit board and the second circuit board is HVLP.
The test fixture for the PCIe4.0 slot provided by the invention can test the performance parameters of the PCIe4.0 slot, and performs transverse comparison by testing the PCIe4.0 slot released by different manufacturers.
Drawings
FIG. 1 is a schematic structural diagram of a test fixture for PCIe4.0 sockets according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating the solder pad of the first circuit board in the PCIe4.0 socket test fixture of the present invention being hollowed out.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a test fixture for PCIe4.0 slots, aiming at the PCIe4.0 slots to be tested which are dual-in-line packages, the test fixture comprises: the device comprises a first circuit board and a second circuit board, wherein the first circuit board is welded with a PCIe4.0 slot to be tested, all signal ends of the PCIe4.0 slot to be tested are led out of all signal wires in a single-ended mode respectively, the lengths of the signal wires are equal, and the other end of each signal wire is connected with an SMA connector; the second circuit board is welded with a golden finger, the golden finger is matched with a PCIe4.0 slot to be tested, all signal ends of the golden finger are led out of all signal wires in a single-ended mode respectively, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector.
Particularly, for simple design, the first circuit board and the second circuit board can adopt the same design, have the same structure and the same wiring form, and the only difference lies in the leading-out position of the signal line, the first circuit board leads out the signal line from the PCIe4.0 slot to be tested, and the second circuit board leads out the signal line from the golden finger part.
As shown in fig. 1, (a) is a first circuit board, and (b) is a second circuit board, all signal ends of a PCIe4.0 slot 11 to be tested are respectively led out in a single-ended manner, each signal end has the same length and is 3 inches, and the other end of each signal end is connected with an SMA connector; all signal ends of the golden finger 12 are led out of all signal wires in a single-ended mode, the length of each signal wire is equal and is 3 inches, and the other end of each signal wire is connected with an SMA connector.
Furthermore, on the first circuit board and the second circuit board, a row of grounded through holes are added on two sides of each signal line to be used as isolation, signal interference is prevented, and the hole interval of each row of grounded holes is 1 mm.
In addition, referring to fig. 1, the PCIe4.0 slot to be tested is located on the right side of the first circuit board, the gold finger is located on the right side of the second circuit board, a 2X Thru line is respectively disposed on the left sides of the two circuit boards, the 2X Thru line is 10 degrees relative to the weft direction of the work panel used for producing the circuit board, and may also be considered as 10 degrees relative to the left edge of the circuit board, as shown by θ in fig. 1, θ is 10 degrees, the length of the 2X Thru line of the two circuit boards is the sum of the length of the signal line of the first circuit board and the length of the signal line of the second circuit board, which is 6inch in this embodiment, and both ends of the 2X Thru line are connected with SMA connectors. The influence of glass fiber effect on AFR de-embedding can be avoided through the 2X Thru line, and AFR de-embedding is better realized. Meanwhile, the signal lines led out from the first circuit board and the second circuit board are single-ended lines with impedance of 42.5ohm, so that the influence on AFR de-embedding precision caused by skew generated by a difference line in a glass fiber effect is avoided.
As shown in fig. 2, the first circuit board optimizes the outgoing line of the PCIe4.0 slot, and a cavity of an anti-pad (anti pad) is used at each signal end of the PCIe4.0 slot to be tested. In fig. 2, oval circles represent hollowing processes of an anti-pad (anti), circles inside the oval represent signal holes on the PCB, and white lines represent signal lines. The processing of the oval hollowed anti-pad has the advantages that: 1) the length of the signal wire in the reverse welding disc is reduced, and impedance discontinuity caused by reference loss is avoided; 2) the capacitance of the DIP connector via is greatly compensated for, resulting in better signal integrity.
Finally, the PCB material of the first circuit board and the second circuit board is selected to be M6 grade, and the copper foil type is selected to be HVLP. The thickness of each board card is 1.6mm, the number of layers is designed to be 6, and all the led-out signal wires are arranged on the 5 th layer. The routing layer is the design of the 5 th layer, can provide a complete reference plane for the signal line, and avoids the technical problem that the impedance of the surface layer routing is difficult to control. In addition, the length of the signal via stub is reduced, and a series of signal integrity problems caused by the fact that the resonance point is close to the fundamental frequency are avoided.
From the above, the test fixture for the PCIe4.0 socket of the present invention has multiple detailed designs of the fixture itself to improve signal integrity, and after completing AFR de-embedding, the performance parameters of the PCIe4.0 socket itself can be ideally tested.
In an actual test, the second circuit board shown in fig. 1(b) is inserted into the first circuit board shown in fig. 1(a), that is, the gold finger is inserted into the PCIe4.0 slot to be tested, and the SMA connector of the first circuit board and the SMA connector of the second circuit board (including the SMA connector of the signal line and the SMA connector of the 2X Thru line) are respectively connected to the vector network analyzer VNA to form a signal loop, and a passive test is performed, and the passive S parameter and the Z parameter of the PCIe4.0 slot are obtained through the processing of AFR de-embedding. And judging the performance of the PCIe4.0 slot through the passive S parameter and the passive Z parameter.
It should be noted that the object of the present invention can also be achieved by changing the stacked design of the PCB (increasing or decreasing the number of layers/selecting other materials) or changing the angle and manner of the traces.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (9)
1. The utility model provides a test fixture of PCIe4.0 slot, PCIe4.0 slot that awaits measuring is the dual in-line package, its characterized in that, test fixture includes: a first circuit board and a second circuit board, wherein,
the first circuit board is welded with a PCIe4.0 slot to be tested, all signal ends of the PCIe4.0 slot to be tested are led out of all signal wires in a single-ended mode, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector;
the second circuit board is welded with a golden finger, the golden finger is matched with a PCIe4.0 slot to be tested, all signal ends of the golden finger are led out of all signal wires in a single-ended mode respectively, the length of each signal wire is equal, and the other end of each signal wire is connected with an SMA connector;
the first circuit board and the second circuit board are respectively provided with a 2X Thru line, two ends of the 2X Thru line are connected with SMA connectors, the 2X Thru line of the first circuit board is positioned at the opposite side of a PCIe4.0 slot to be tested and has a certain angle relative to the opposite side edge of the first circuit board, the 2X Thru line of the second circuit board is positioned at the opposite side of a golden finger and has a certain angle relative to the opposite side edge of the second circuit board, the 2X Thru lines of the first circuit board and the second circuit board have the same angle, and the lengths of the two lines are the sum of the length of a signal line of the first circuit board and the length of a signal line of the second circuit board;
the signal wire is connected with the SMA connector and the SMA connector connected with the 2X Thru wire and is used for connecting a vector network analyzer to form a signal loop.
2. The test fixture for PCIe4.0 sockets as specified in claim 1 wherein the signal line length of the first circuit board is equal to the signal line length of the second circuit board.
3. The tool of claim 1, wherein a row of ground vias is formed on each of two sides of each signal line of the first circuit board and the second circuit board.
4. The test fixture for PCIe4.0 slot according to claim 3, wherein the hole interval of each row of ground holes is 1 mm.
5. The tool of claim 1, wherein the first circuit board is hollowed out at locations corresponding to signal terminals of the PCIe4.0 socket to be tested by using anti-pads.
6. The tool of claim 5, wherein the first circuit board is hollowed out with an oval shape at each signal end of the PCIe4.0 socket to be tested.
7. The tool of claim 1, wherein the first circuit board and the second circuit board are multi-layer circuit boards, and all signal lines are disposed on an intermediate layer.
8. The PCIe4.0 socket test fixture of claim 1, wherein the PCB material of the first circuit board and the second circuit board is selected from M6 grade.
9. The PCIe4.0 socket test fixture of claim 1, wherein the copper foil type of the first circuit board and the second circuit board is HVLP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811476055.4A CN109684139B (en) | 2018-12-04 | 2018-12-04 | Test fixture of PCIe4.0 slot |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811476055.4A CN109684139B (en) | 2018-12-04 | 2018-12-04 | Test fixture of PCIe4.0 slot |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109684139A CN109684139A (en) | 2019-04-26 |
| CN109684139B true CN109684139B (en) | 2022-06-24 |
Family
ID=66187072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811476055.4A Active CN109684139B (en) | 2018-12-04 | 2018-12-04 | Test fixture of PCIe4.0 slot |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109684139B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111044762A (en) * | 2020-01-19 | 2020-04-21 | 安费诺电子装配（厦门）有限公司 | High-speed former cable electrical integrity test fixture |
| CN111679944B (en) * | 2020-06-10 | 2023-08-29 | 浪潮商用机器有限公司 | PCI-E interface function test device |
| CN112115673A (en) * | 2020-09-27 | 2020-12-22 | 浪潮电子信息产业股份有限公司 | PCIE signal PIN adjacent layer hollowing design method, system, device and storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102735945A (en) * | 2011-04-07 | 2012-10-17 | 鸿富锦精密工业（深圳）有限公司 | Signal testing device |
| US10055379B2 (en) * | 2015-07-10 | 2018-08-21 | SK Hynix Inc. | Peripheral component interconnect express card |
| CN206178002U (en) * | 2016-11-23 | 2017-05-17 | 郑州云海信息技术有限公司 | 10, 000, 000, 000 net gape test fixture |
| CN206609901U (en) * | 2017-04-06 | 2017-11-03 | 郑州云海信息技术有限公司 | A kind of PCIE channel loss test tool |
| CN107703362A (en) * | 2017-12-07 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of server master board PCIE signal line impedence measurement jig |
| CN108663548A (en) * | 2018-04-11 | 2018-10-16 | 郑州云海信息技术有限公司 | A kind of PCIe card test protection jig, test structure and test method |
-
2018
- 2018-12-04 CN CN201811476055.4A patent/CN109684139B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109684139A (en) | 2019-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109684139B (en) | Test fixture of PCIe4.0 slot | |
| US6462570B1 (en) | Breakout board using blind vias to eliminate stubs | |
| US9515031B2 (en) | Mitigation of far-end crosstalk induced by routing and out-of-plane interconnects | |
| US9568498B2 (en) | Concept for extracting a signal being exchanged between a device under test and an automatic test equipment | |
| CN108169574B (en) | Method and system for testing via loss | |
| EP2624668A1 (en) | Integrated module, integrated system board, and electronic device | |
| CN112710977B (en) | Surface-mounted passive device S parameter measuring device and method based on TRM calibration | |
| CN107077176B (en) | Two-part electrical connector | |
| CN208044474U (en) | Mainboard and computer device | |
| CN108255652B (en) | Signal testing device | |
| WO2018086314A1 (en) | Connector and communication device | |
| US20110271025A1 (en) | Computer motherboard | |
| CN104219870A (en) | Printed circuit board | |
| CN111372371A (en) | Printed circuit board, wiring method of printed circuit board and electronic equipment | |
| TWI695658B (en) | Circuits and methods providing electronic band gap (ebg) structures at memory module electrical coupling | |
| JP2013065657A (en) | Printed wiring board, and method for wiring printed wiring board | |
| CN113125855B (en) | Impedance measurement method for printed board differential signal line | |
| US9921262B2 (en) | Method and apparatus for a probe card | |
| CN115442968B (en) | High-speed differential signal wiring method and circuit board | |
| US7394260B2 (en) | Tuning a test trace configured for capacitive coupling to signal traces | |
| CN109743834B (en) | Method for optimizing USB link impedance | |
| TW202004205A (en) | Circuit board for transmitting high speed signal and for said signal to be detected | |
| US11229115B2 (en) | Wiring board and electronic device | |
| WO2023077646A1 (en) | Printed circuit board | |
| CN110839314B (en) | PCB board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220803 Address after: 100089 building 36, courtyard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee after: Dawning Information Industry (Beijing) Co.,Ltd. Patentee after: DAWNING INFORMATION INDUSTRY Co.,Ltd. Address before: 100193 No. 36 Building, No. 8 Hospital, Wangxi Road, Haidian District, Beijing Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231114 Address after: 030024 No. 19 Gaoxin Street, Taiyuan Xuefu Park, Shanxi Comprehensive Reform Demonstration Zone, Taiyuan City, Shanxi Province Patentee after: Guoke Jinyun Technology Co.,Ltd. Address before: 100089 building 36, courtyard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee before: Dawning Information Industry (Beijing) Co.,Ltd. Patentee before: DAWNING INFORMATION INDUSTRY Co.,Ltd. |