CN108169574B - Method and system for testing via loss - Google Patents
Method and system for testing via loss Download PDFInfo
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- CN108169574B CN108169574B CN201711380128.5A CN201711380128A CN108169574B CN 108169574 B CN108169574 B CN 108169574B CN 201711380128 A CN201711380128 A CN 201711380128A CN 108169574 B CN108169574 B CN 108169574B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2688—Measuring quality factor or dielectric loss, e.g. loss angle, or power factor
- G01R27/2694—Measuring dielectric loss, e.g. loss angle, loss factor or power factor
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Abstract
Methods and systems for testing via loss are provided. The method for testing the via hole loss comprises the following steps: providing a circuit board, wherein the circuit board comprises three pairs of differential lines with the same length, a first pair of differential lines is provided with a plurality of groups of through holes, and a second pair of differential lines and a third pair of differential lines are not provided with through holes; respectively measuring the insertion loss of the first pair of differential lines, the second pair of differential lines and the third pair of differential lines; and performing AFR de-embedding on the first pair of differential lines by using the second pair of differential lines and the third pair of differential lines to obtain via hole loss. The influence brought by the PCB glass fiber effect and the process error is greatly reduced, and the loss of the differential via hole obtained through testing is more accurate.
Description
Technical Field
The present application relates generally to the field of electronics and sexual measurement, and more particularly, to a method and system for testing via loss.
Background
With the development of high-speed signal rates of various differential interconnects on a Printed Circuit Board (PCB) of a server and the limitation of the loss of the total link by each protocol, the requirement for signal integrity is becoming more and more strict. For a complete link on a PCB (printed circuit board) wiring (also called a wiring) of a server, factors influencing signal integrity are many, and only each discontinuous structure is optimized, a margin can be reserved, so that a link which has high cost performance and meets the requirement of a protocol specification is designed. Because the on-board wiring has connectors, interconnection among chips, space limitation and the like, the layer change design of signals is inevitably introduced, but the via hole structure has the characteristics of smaller size and smaller loss compared with an integral link, and if more allowance can be reserved for the rest parts with larger loss, the accurate test of the loss of the on-board via hole structure is very important.
The prior art provides a circuit board capable of simultaneously measuring via hole impedance and via hole loss, which comprises a circuit board body, wherein a plurality of via holes to be measured are arranged on the circuit board body, the via holes to be measured are provided with a first opening and a second opening, the first opening is positioned on one side of the circuit board body, and the second opening is positioned on the other side of the circuit board body; one side of the circuit board body is also provided with a first impedance line, a third impedance line, a first connector, a third connector and a fourth connector, and the other side of the circuit board body is also provided with a second impedance line and a second connector; one end of the first impedance line is connected with the first connector, and the other end of the first impedance line is connected with the first opening; one end of the second impedance line is connected with the second connector, and the other end of the second impedance line is connected with the second opening; one end of the third impedance line is connected with the third connector, and the other end of the third impedance line is connected with the fourth connector; a TRL (transmission, reflection, line, that is, TRL is an abbreviation of three test items of a through test item, a reflection test item, and a test line/load) calibration piece is further disposed on one surface of the circuit board body.
The prior art does not need to search for a through hole to be tested during measurement, and does not need to use a probe station for testing. However, the following drawbacks still exist:
1. the design of the circuit board only considering the via holes of the single-end lines is not significant for the high-speed signal lines of the server, and because the high-speed lines are all designed by using differential pairs, the via holes also need to be differential via holes.
2. The circuit board adopts a TRL calibration line method, but special treatment is not carried out on the via routing and the calibration line. With the increasing signal rate, the glass fiber effect of the material must be taken into account, and if the calibration line and the via routing are just in a special case of one on the glass fiber cloth and one on the windowing, the calculation of the loss of the via will have a large error.
3. The design does not take into account the influence of process errors. If the transmission line is too long, the line width of the transmission line is small, and the influence of errors is more obvious. In the design, the length of the transmission line is more than 2 inches, and the number of the through holes to be tested is only 1, so that the special condition that the loss of the through hole testing line is smaller than that of the calibration line exists
Disclosure of Invention
The present application provides a method and system for testing via loss, which can solve the above problems.
According to an aspect of the present application, there is provided a method of testing via loss, comprising: providing a circuit board, wherein the circuit board comprises three pairs of differential lines with the same length, a first pair of differential lines is provided with a plurality of groups of through holes, and a second pair of differential lines and a third pair of differential lines are not provided with through holes; respectively measuring the insertion loss of the first pair of differential lines, the second pair of differential lines and the third pair of differential lines; and performing AFR de-embedding on the first pair of differential lines by using the second pair of differential lines and the third pair of differential lines to obtain via hole loss.
Preferably, the AFR de-embedding is used for removing the influence of the connector and the on-board wiring on the via loss during measurement.
Preferably, the via hole layers on the first pair of differential lines are both a bottom layer and a top layer; the second pair of differential lines is positioned on the top layer; and the third pair of differential lines is located at the bottom layer.
Preferably, performing AFR de-embedding on the first pair of differential lines using the second pair of differential lines and the three pairs of differential lines to obtain via loss further comprises: performing first AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the second pair of differential lines; and then performing a second AFR de-embedding of the first pair of differential lines using half of the insertion loss of the third pair of differential lines to obtain the via loss.
Preferably, the via loss is an insertion loss of a plurality of vias.
Preferably, the insertion loss of each via is obtained based on the via loss.
Preferably, the line width and the line distance of the second pair of differential lines and the third pair of differential lines are respectively the same as the line width and the line distance of the top layer and the bottom layer of the first pair of differential lines.
Preferably, the three pairs of differential lines are wired in a manner rotated by an angle of 10 degrees.
Preferably, the plurality of groups of vias are 5 groups of vias.
Preferably, each of the vias in the plurality of sets of vias includes two vias on the differential lines and two reflow holes for differential signals, wherein the reflow holes are disposed near outer sides of the vias on the two differential lines.
Preferably, the distance between two adjacent groups of vias is not equal to an integer multiple of one-quarter of the signal wavelength.
Preferably, the distance between two adjacent sets of vias is 10 mils.
Preferably, the distance between one of the two outermost groups of vias and the corresponding connector is 200 mils.
According to another aspect of the present application, there is provided a system for testing via loss, comprising: the circuit board comprises three pairs of differential lines with the same length, wherein the first pair of differential lines are provided with a plurality of groups of through holes, and the second pair of differential lines and the third pair of differential lines are not provided with through holes; a measuring device for measuring insertion loss of the first pair of differential lines, the second pair of differential lines, and the third pair of differential lines; and the processing device is used for carrying out AFR de-embedding on the first pair of differential lines by utilizing the second pair of differential lines and the third pair of differential lines so as to obtain the via hole loss.
The method and the system for testing the via hole loss greatly reduce the influence caused by PCB glass fiber effect and process error, so that the loss of the differential via hole obtained through testing is more accurate.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a flow chart of a method of testing via loss according to an embodiment of the present application;
FIG. 2 is a simplified diagram of a circuit board according to an embodiment of the present application; and
FIG. 3 is a block diagram of a system for testing via loss according to an embodiment of the present application;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flow chart of a method of testing via loss according to an embodiment of the present application. A method of testing via loss is described below with reference to fig. 1.
Referring to fig. 1, a method 100 of testing via loss according to an embodiment of the present application includes: 102, providing a circuit board, wherein the circuit board comprises three pairs of differential lines with the same length, the first pair of differential lines are provided with a plurality of groups of through holes, and the second pair of differential lines and the third pair of differential lines are not provided with through holes; step 104, respectively measuring the insertion loss of the first pair of differential lines, the second pair of differential lines and the third pair of differential lines; and 106, performing AFR de-embedding on the first pair of differential lines by using the second pair of differential lines and the third pair of differential lines to obtain the via hole loss.
According to the embodiment of the application, the loss of the obtained differential via hole can be tested by using the method for testing the loss of the via hole, so that the application can be applied to the high-speed signal line of the server.
Fig. 2 is a simplified diagram of a circuit board according to an embodiment of the present application. Hereinafter, a method of testing via loss will be described in detail with reference to fig. 1-2.
Referring to fig. 1, a method 100 of testing via loss includes: step 102, providing a circuit board, wherein the circuit board includes three pairs of differential lines (also called differential pairs) with the same length, the first pair of differential lines 3-4 is provided with a plurality of groups of via holes, and the second pair of differential lines 1-2 and the third pair of differential lines 5-6 are not provided with via holes. The via hole layers on the first pair of differential lines are both a bottom layer and a top layer; the second pair of differential lines 1-2 is positioned on the top layer; and a third pair of differential lines is located at the bottom layer 3-4. The line width and the line distance of the second pair of differential lines 1-2 and the third pair of differential lines 3-4 are respectively the same as the line width and the line distance of the top layer and the bottom layer of the first pair of differential lines. Three pairs of differential lines are wired so as to be rotated by an angle of 10 degrees. For example, the plurality of sets of vias are 5 sets of vias 202, 212, 222, 232, and 242. In other embodiments, the plurality of sets of vias is any number of sets of vias. Each of the sets of vias includes two differential on- line vias 204 and 206 and two differential signal reflow holes 208 and 210, wherein the reflow holes 208 and 210 are disposed adjacent to the outer sides of the two differential on- line vias 204 and 206. The distance between two adjacent groups of through holes is not equal to the integral multiple of one-fourth signal wavelength. The distance between two adjacent groups of vias is 10 mils. The distance between one of the outermost two sets of vias and the corresponding connectors is 200 mils.
And step 104, respectively measuring the insertion loss of the first pair of differential lines, the second pair of differential lines and the third pair of differential lines. Wherein, insertion loss of the first pair of differential lines, the second pair of differential lines, and the third pair of differential lines are respectively measured using a VAN (vector network analyzer, i.e., VNA) test device.
And 106, performing AFR (automatic texture removal) embedding on the first pair of differential lines by using the second pair of differential lines and the third pair of differential lines to obtain the via hole loss. And the AFR de-embedding is used for removing the influence of the connector and the wiring on the board on the via hole loss during measurement. Specifically, performing AFR de-embedding on the first pair of differential lines using the second pair of differential lines and the three pairs of differential lines to obtain the via loss further comprises: performing first AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the second pair of differential lines; and then performing a second AFR de-embedding of the first pair of differential lines using half of the insertion loss of the third pair of differential lines to obtain a via loss. The via loss is the insertion loss of a plurality of vias. For example, the via loss is an insertion loss of 5 vias. And acquiring the insertion loss of each via hole based on the via hole loss. I.e., averaging the loss of multiple vias to obtain the insertion loss of each via. In other embodiments, embodiments in which the number of vias and the size of the inter-via spacing are altered are within the scope of the present application.
Hereinafter, referring to fig. 2, a method of testing via loss is illustrated. Firstly, determining the lamination information of the differential via to be tested and the layer change information of the via, and proposing a loose coupling routing design mode on the design of the differential pairs 1-2, 5-6 and 3-4 to reduce the influence caused by process errors, wherein the line spacing is not more than 2 times of the line width and is tight coupling, and the line spacing is more than 3 times of the line width and is loose coupling. Differential pairs 1-2 and 5-6 are divided into layers where traces are located at both ends of the vias of differential pairs 3-4. The following description will be made by taking the via information as Top and changing to a Bottom (Bottom) layer as an example.
The test board comprises 3 pairs of differential lines, differential pairs 1-2, 3-4 and 5-6, wherein the differential pair 1-2 is positioned on a TOP (TOP) layer, the differential pair 5-6 is positioned on a bottom layer, and the via hole layers on the differential pair 3-4 are both the bottom layer and the TOP layer. The de-embedding mode is selected as an AFR de-embedding algorithm, wherein the most convenient S parameter test calibration method AFR has the following advantages compared with a TRL de-embedding algorithm: the AFR only needs to set one tru calibration piece, the number of the tru calibration pieces is much less than that of the TRL calibration pieces, and the operation steps are correspondingly reduced; the AFR can process the situation that the texture at two ends of the DUT is not symmetrical; the AFR can perform de-embedding operation of a single port; and 4, the single-ended AFR function can convert the single-ended S parameter into a two-port S parameter. Due to the specificity that the wires at the two ends of the via hole are in different layers, the AFR de-embedding advantage is more obvious. The line width and the line distance of the differential pairs 1-2 are completely consistent with those of the top layer wires of the differential pairs 3-4, the line width and the line distance of the differential pairs 5-6 are completely consistent with those of the bottom layer wires of the differential pairs 3-4, and the differential pairs are all subjected to 10-degree angle rotation design, so that the influence of a glass fiber effect is greatly reduced, wherein the glass fiber effect is caused by the local change of the relative dielectric constant of a dielectric layer due to the gaps existing in warp and weft weaving of glass fiber cloth in the dielectric. The connection of the two ends of the differential pair is the SMA head, and the effect of embedding the wire differential pair 1-2 by the AFR is to remove the influence of the connector and the wiring on the board on the loss test of the differential via hole during measurement.
5 differential through holes are uniformly set on the differential pairs 3-4Considering that the designed via holes may have the situation that the impedance is not optimized or is not ideal, the oscillation caused by multiple reflections of the signal between the via holes is avoided, the length between the via holes is avoided by integral multiple of 1/4 signal wavelength, the calculation formula of the signal wavelength is that lambda is C/(. f), lambda is the wavelength, C is 3 × 108m/s is the dielectric constant of the medium in which the signal is located, and f is the frequency of the signal. Since the high speed signal lines of greater concern to the server are all at rates above 5Gbps, setting the inter-aperture trace length to 10 mils herein avoids the resonance problem where the amplitude of the electromagnetic oscillations of the circuit will peak when the frequency excited in the circuit is equal to the natural frequency of the circuit. The distance from the outermost hole to the SMA head was set at 200 mils, again to avoid introducing effects due to insufficient SMA impedance optimization. The total length of the differential pairs 1-2, 5-6 and 3-4 is 440 mils.
And carrying out Sdd21 test on the differential pairs 1-2, 3-4 and 5-6 by using VNA, and carrying out AFR de-embedding on the differential pair 3-4 by using the differential pairs 1-2 and 5-6 to obtain an insertion loss curve of 5 through holes. And determining a fundamental frequency value of the high-speed signal line on the obtained insertion loss curve to obtain an insertion loss value, and dividing the obtained insertion loss value by 5 to obtain loss data of a through hole to be tested.
The method for testing the via hole loss greatly reduces the influence caused by PCB glass fiber effect and process errors, and enables the loss of the differential via hole obtained through testing to be more accurate.
Fig. 3 is a block diagram of a system for testing via loss according to an embodiment of the present application. Hereinafter, a system for testing via loss will be described with reference to fig. 3.
Referring to fig. 3, a system 300 for testing via loss is provided, according to an embodiment of the present application, comprising: the circuit board 302 comprises three pairs of differential lines with the same length, wherein the first pair of differential lines is provided with a plurality of groups of through holes, and the second pair of differential lines and the third pair of differential lines are not provided with through holes; a measuring device 304 for measuring insertion loss of the first pair of differential lines, the second pair of differential lines, and the third pair of differential lines; and a processing device 306 for performing AFR de-embedding on the first pair of differential lines using the second pair of differential lines and the third pair of differential lines to obtain via hole loss.
The detailed description of the system 300 for testing via loss is consistent with the method for testing via loss and, therefore, will not be repeated here.
The system for testing the via hole loss greatly reduces the influence caused by the PCB glass fiber effect and the process error, so that the loss of the differential via hole obtained through testing is more accurate.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (13)
1.A method of testing via loss, comprising:
providing a circuit board, wherein the circuit board comprises three pairs of differential lines with the same length, a first pair of differential lines is provided with a plurality of groups of through holes, and a second pair of differential lines and a third pair of differential lines are not provided with through holes;
respectively measuring the insertion loss of the first pair of differential lines, the second pair of differential lines and the third pair of differential lines; and
performing AFR de-embedding on the first pair of differential lines using the second and third pairs of differential lines to obtain via hole loss;
wherein AFR de-embedding the first pair of differential lines using the second and third pairs of differential lines to obtain via loss further comprises:
performing first AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the second pair of differential lines; and
and then performing second AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the third pair of differential lines to obtain the via hole loss.
2. The method of claim 1, wherein the AFR de-embedding is used to remove the effect of connectors and on-board wiring on the via loss during measurement.
3. The method of claim 1, wherein the via exchange layers on the first pair of differential lines are both a bottom layer and a top layer;
the second pair of differential lines is positioned on the top layer; and
the third pair of differential lines is located at the bottom layer.
4. The method of testing via loss according to claim 1, wherein the via loss is an insertion loss of a plurality of vias.
5. The method of claim 4, wherein the insertion loss of each via is obtained based on the via loss.
6. The method of claim 3, wherein the line width and line spacing of the second pair of differential lines and the third pair of differential lines are the same as the line width and line spacing of the top layer and the bottom layer, respectively, of the first pair of differential lines.
7. The method of claim 1, wherein the three pairs of differential lines are routed with a 10 degree rotation.
8. The method for testing via loss according to claim 1, wherein the plurality of sets of vias are 5 sets of vias.
9. The method of testing via loss according to claim 1, wherein each of the plurality of sets of vias comprises two differential over-the-wire vias and two differential signal reflow holes, wherein the reflow holes are disposed near outer sides of the two differential over-the-wire vias.
10. The method of testing via loss according to claim 1, wherein a distance between two adjacent sets of vias is not equal to an integer multiple of a quarter of a signal wavelength.
11. The method of claim 10, wherein the distance between two adjacent sets of vias is 10 mils.
12. The method of claim 1, wherein a distance between one of the two outermost groups of vias and the corresponding connectors is 200 mils.
13. A system for testing via loss, comprising:
the circuit board comprises three pairs of differential lines with the same length, wherein the first pair of differential lines are provided with a plurality of groups of through holes, and the second pair of differential lines and the third pair of differential lines are not provided with through holes;
a measuring device for measuring insertion loss of the first pair of differential lines, the second pair of differential lines, and the third pair of differential lines; and
processing means for performing AFR de-embedding on the first pair of differential lines using the second and third pairs of differential lines to obtain via loss;
wherein AFR de-embedding the first pair of differential lines using the second and third pairs of differential lines to obtain via loss further comprises:
performing first AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the second pair of differential lines; and
and then performing second AFR de-embedding on the first pair of differential lines by using half of the insertion loss of the third pair of differential lines to obtain the via hole loss.
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| CN109525308B (en) * | 2018-11-19 | 2020-06-16 | 苏州浪潮智能科技有限公司 | Optical module detection method, device, equipment and storage medium |
| CN109406839B (en) * | 2018-11-20 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Signal test fixture, system and test method |
| CN110441628A (en) * | 2019-07-29 | 2019-11-12 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | High speed connector performance test methods, apparatus and system |
| CN115884492A (en) * | 2021-08-25 | 2023-03-31 | 中兴智能科技南京有限公司 | Loss test strip and PCB device |
| CN117062309B (en) * | 2023-10-10 | 2024-01-26 | 苏州元脑智能科技有限公司 | Via loss measurement structure, method, system, equipment and medium |
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| US9571059B2 (en) * | 2015-03-28 | 2017-02-14 | Intel Corporation | Parallel via to improve the impedance match for embedded common mode filter design |
| CN205657907U (en) * | 2016-03-31 | 2016-10-19 | 广州兴森快捷电路科技有限公司 | But circuit board of impedance of simultaneous measurement via hole and via hole loss |
| CN106872790B (en) * | 2017-02-25 | 2021-04-09 | 郑州云海信息技术有限公司 | Method and system for detecting via hole loss |
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