CN113612554A - Testing device and testing method for equalizer parameters - Google Patents
Testing device and testing method for equalizer parameters Download PDFInfo
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- CN113612554A CN113612554A CN202110701409.6A CN202110701409A CN113612554A CN 113612554 A CN113612554 A CN 113612554A CN 202110701409 A CN202110701409 A CN 202110701409A CN 113612554 A CN113612554 A CN 113612554A
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- H—ELECTRICITY
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- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/309—Measuring or estimating channel quality parameters
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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Abstract
The invention has proposed testing device and test method of a equalizer parameter, the testing device includes setting up the chip to be tested of the equalizer, first exchange module and second exchange module, the chip to be tested is used for adjusting the voltage output size when the equalizer parameter tests; the chip to be tested is in communication connection with the first switching module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; the first switching module is used for receiving the voltage output of the chip to be tested, the first switching module and the second switching module jointly realize the switching of different link channels to obtain the signal attenuation of different links, and the equalizer is used for obtaining the signal compensation of different link channels according to the signal attenuation of different links. Based on the testing device, the testing method of the equalizer parameters is also provided, and each different device can be adjusted by adopting one-time testing, so that the time is saved, and the testing effect is improved.
Description
Technical Field
The invention belongs to the technical field of signal testing, and particularly relates to a testing device and a testing method for equalizer parameters.
Background
Signal integrity is more and more important along with development of high-speed signals, and communication between chips is more challenging under the condition that signal bandwidth is rapidly increased, so that at present, products such as servers, notebook computers and the like pay more and more attention to verification of signal quality, margin testing is one of important points, and the purpose is to verify that proper signal compensation can be obtained after the chips are communicated with the chips so as to compensate distortion caused by attenuation of signals after the signals pass through a channel. There are many combinations of equalization parameters as given in the table below, and it is often necessary to perform optimization tests using devices of different brands/capacities/models, so optimizing the parameters in margin tests to optimize the signal back to a large point. Since C-1 and C +1 are both less than 0 in the table, this means that the de-emphasis and pre-emphasis, respectively, are applied to the switching bit: and de-emphasis is only effected when the current bit of the pattern of the signal is switched from 0 level to 1 level or from 1 level to 0 level compared to the previous bit; pre-emphasis only works when the current bit of the code pattern of the signal is switched from 0 level to 1 level or from 1 level to 0 level compared with the next bit; for example, if C-1 is zero, then only de-emphasis should be active; if C +1 is zero, then only pre-emphasis should be active; if both are active at the same time, Boost will be generated, i.e. simultaneous switching of 0, 1, 0 levels.
Depending on the product requirements, 5-10 different PCIe devices, such as network cards, are often tested on a single PCIe slot. Often, devices of different brands/capacities/models are required to be used, and signal quality must be verified, and if there are multiple PCIe slots on the system and the optimum equalizer parameters are to be adapted for different devices, the prior art approach is to independently perform corresponding optimization tests for each product, which inevitably results in a large amount of time waste.
Disclosure of Invention
In order to solve the technical problems, the invention provides a testing device and a testing method for equalizer parameters, which can adopt one-time testing to finish different devices to adjust the optimal equalizer parameters, save time and improve the testing effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a testing device for equalizer parameters comprises a chip to be tested, a first switching module and a second switching module, wherein the chip to be tested is provided with an equalizer;
the chip to be tested is used for adjusting the voltage output during the parameter test of the equalizer; the chip to be tested is in communication connection with the first switching module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; the first switching module is used for receiving the voltage output of the chip to be tested, the first switching module and the second switching module jointly realize the switching of different link channels to obtain the signal attenuation of different links, and the equalizer is used for obtaining the signal compensation of different link channels according to the signal attenuation of different links.
Further, the second exchange chip is connected with the golden finger;
and the second exchange chip outputs corresponding signal compensation in different link channel margin tests through the golden finger.
Further, the method for determining the number of the link channels comprises the following steps:
and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
Further, the setting of the link channels with different lengths between the first switching module and the second switching module according to the link attenuation degree further includes: and a jump cap is arranged on each link channel and used for realizing hardware switching.
Further, the chip to be tested for setting the equalizer includes but is not limited to a PCIe network card.
Furthermore, the testing device is connected with any equipment to be tested of a server, a switch or a computer through a golden finger.
A method for testing parameters of an equalizer is realized based on a device for testing the parameters of the equalizer, and comprises the following steps:
setting the voltage output of a chip to be tested;
selecting a first link channel, and performing margin test according to the voltage output of the chip to be tested to obtain the signal attenuation of the first link channel;
switching other link channels except the first link channel to finish the attenuation test of all the link channels;
receiving signal attenuation of all link channels through an equalizer; and obtaining the optimal signal compensation of different link channels according to the signal attenuation of all the link channels.
Further, the signal attenuation of all link channels is received by an equalizer; obtaining the optimal signal compensation of different link channels according to the signal attenuation of all the link channels, and writing the optimal signal compensation of different link channels into the storage device of the chip to be tested.
Further, the writing of the optimization parameters of the equalizer to be tested further includes determining the number of link channels; the specific process for determining the number of the link channels comprises the following steps: and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
Further, the method for evaluating the attenuation initial value of the link channel to the chip to be tested comprises: and searching the attenuation initial value of the chip to be tested in the link channel design standard specification.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
the invention has proposed testing device and test method of a equalizer parameter, the testing device includes setting up the chip to be tested of the equalizer, first exchange module and second exchange module, the chip to be tested is used for adjusting the voltage output size when the equalizer parameter tests; the chip to be tested is in communication connection with the first switching module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; the first switching module is used for receiving the voltage output of the chip to be tested, the first switching module and the second switching module jointly realize the switching of different link channels to obtain the signal attenuation of different links, and the equalizer is used for obtaining the signal compensation of different link channels according to the signal attenuation of different links. The method can adopt one-time test to finish the adjustment of the optimal equalizer parameters by different devices, thereby saving time and improving test effect.
According to the invention, the switching of channels with different lengths is realized by adopting two switching modules, the first switching module is used for receiving signals output by a chip to be tested and then transmitting the signals to the second switching module, if only a single switching module is used, all the channels with different lengths are connected to gold fingers through the signals of the switching module, the reflection effect can be caused by other channels, the quality of the signals can be greatly influenced, the second switching module is designed to be added for blocking the reflection effect, only the signal sent by the bypass from the first switching chip is needed, the channel receiving the signals can be a terminal in the second switching module, and the reflection phenomenon caused by the mutual influence among the channels can be avoided.
The invention also provides a method for testing parameters of the equalizer, for a tester, only one device can be installed in a single PCIe slot at one time, when a product needs to be matched with a plurality of devices, much manpower and time are consumed for carrying out optimization testing.
Drawings
Fig. 1 is a schematic diagram of an apparatus for testing equalizer parameters according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a method for testing equalizer parameters according to embodiment 2 of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
Example 1
The embodiment 1 of the invention provides a device for testing parameters of an equalizer, which comprises a chip to be tested, a first switching module and a second switching module, wherein the chip to be tested is provided with the equalizer;
the chip to be tested is used for adjusting the voltage output during the parameter test of the equalizer; the chip to be tested is in communication connection with the first switching module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; the first switching module is used for receiving the voltage output of the chip to be tested, the first switching module and the second switching module jointly realize the switching of different link channels to obtain the signal attenuation of different links, and the equalizer is used for obtaining the signal compensation of different link channels according to the signal attenuation of different links.
The second exchange chip is connected with the golden finger;
and the second exchange chip outputs corresponding signal compensation in different link channel margin tests through the golden finger.
Fig. 1 is a schematic diagram of an apparatus for testing equalizer parameters according to embodiment 1 of the present invention. In the testing device, when the chip to be tested is a PCIE network card, a Mellanox Connect-6 chip is selected to support PCIe4.0x16. During testing, the output voltage of the Mellanox Connect-6 chip and the parameters of the equalizer are adjusted, and the output voltages of most of different chips are responded by the test after the output voltages are adjusted. The Broadcom/Mellanox et al chips have different output voltages and if experiments were conducted with various voltage range outputs in this experiment, they could be directly compared from the database to cover the parameters that need to be adjusted for different chip designs. The equalizer is a hard device or circuit for compensating the attenuation of signals, which is done by the turbo decoder on the chip, so that the chip control is needed to adjust the equalizer, and in table 1, (C-1/C +1), different parameter combinations are needed to cope with the proper signal compensation for different PCIe channel attenuations, and set1-10 defined by the association can be in most cases, but actually can be subdivided into different sets, so that the trial design is needed, and besides the PCIe design can be in most products, a more rigorous solution can be found.
The chip to be tested is in communication connection with the first exchange module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; different length channels are designed for the entire PCIe4.0 link, and can be evaluated according to the length of each product channel or different slots. According to the evaluation of the channel attenuation reduction of the PCIe link, the total loss of the PCIe4.0 standard design is 28dB, the channel attenuation of the product design evaluation is provided by the requirement of a design department (different attenuation reduction are different for different PCIe slot lengths), and appropriate parameters are applied to the comparison database.
The method for determining the number of the link channels comprises the following steps:
and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
It can be seen that the evaluation of PCIe4 and AIC (… devices such as PCIe network card) is 8.0dB, so that the design will design ± 3dB channel attenuation with 8.0dB as the center, and add a switch control chip to both the end near the gold finger and the chip to be tested for channel switching. In the invention, two switches are used for switching different lengths in figure 1, 8dB +/-3 dB is taken as a reference, and every 0.5dB is a first-class distance, so that 13 groups of channels in total can be switched in loss.
8dB is the error of the PCIe4.0AIC association standard in the table, the total loss actually has the channel attenuation reduction of poor/standard/good which is 30/28/27dB respectively, so that the difference between the poor and the standard is 2dB, if a harsher product is designed, the concept of +/-3 dB is provided, and 0.5 is a tolerance value which is in line with the design within +/-3 dB and can be in line with the 27-30dB range regulated by the association at present.
The first switching module receives signals output from a chip to be tested, then descending signals are transmitted to the second switching module, each black line in the graph 1 represents a different long and weak channel, which means different attenuation degree of the channel, the channel length switching can be realized by only controlling the channel to be conducted by the first exchange module connected with the Mellanox chip, and why the second exchange module is used because only a single exchange module is used, if the signal passing through the exchange module is connected to all channels with different lengths, the gold finger can be caused by reflection effect of other channels, the quality of the signal can be greatly influenced, the second exchange module is arranged to be added for blocking the reflection effect, only the signal sent by the bypass from the first exchange chip is needed, the channel for receiving the signal in the bit can be a terminal in the second exchange module, and reflection phenomenon caused by mutual influence among the channels is avoided.
The second exchange chip in the test device is connected with the golden finger;
and the second exchange chip outputs corresponding signal compensation in different link channel margin tests through the golden finger.
The testing device for the equalizer parameters uses the exchange module to switch the length of the channels, can add the jump cap of the hardware between the channels, and conducts the jump cap to execute the hardware switching according to the length needed to be used, thereby being capable of executing the channel switching by both the software and the hardware.
The chip to be tested, on which the equalizer is set in embodiment 1 of the present invention, includes but is not limited to a PCIe network card. Other chips to be tested may be provided with the equalizer.
The testing device is connected with any equipment to be tested of a server, a switch or a computer through a golden finger. The testing device designs that the golden finger is partially inserted into the slot aiming at the standard PCIe slot, and the CPU on the sensing object can be communicated with the PCIe protocol between the Mellanox reduced chips.
Example 2
Based on the testing device for the equalizer parameters provided in embodiment 1 of the present invention, embodiment 2 of the present invention also provides a testing method for the equalizer parameters. Fig. 2 is a flowchart of a method for testing equalizer parameters according to embodiment 2 of the present invention.
In step S201, the voltage output of the chip to be tested is set.
The Mellanox Connect-6 chip is selected to support PCIe4.0x16. During testing, the output voltage of the Mellanox Connect-6 chip and the parameters of the equalizer are adjusted, and the output voltages of most of different chips are responded by the test after the output voltages are adjusted. The Broadcom/Mellanox et al chips have different output voltages and if experiments were conducted with various voltage range outputs in this experiment, they could be directly compared from the database to cover the parameters that need to be adjusted for different chip designs.
In step S202, a first link channel is selected, and a margin test is performed according to the voltage output of the chip to be tested, so as to obtain the signal attenuation of the first link channel;
in step S203, other link channels except the first link channel are switched, and the attenuation tests of all the link channels are completed.
In the invention, a first exchange module receives a signal output from a chip to be tested, then a descending signal is transmitted to a second exchange module, each black line in figure 1 represents a different long path, which means different path attenuation degree, the channel length switching can be realized by only controlling the channel to be conducted by the first exchange module connected with the Mellanox chip, and why the second exchange module is used because only a single exchange module is used, if the signal passing through the exchange module is connected to all channels with different lengths, the gold finger can be caused by reflection effect of other channels, the quality of the signal can be greatly influenced, the second exchange module is arranged to be added for blocking the reflection effect, only the signal sent by the bypass from the first exchange chip is needed, the channel for receiving the signal in the bit can be a terminal in the second exchange module, and reflection phenomenon caused by mutual influence among the channels is avoided.
In step S204, receiving signal attenuations of all link channels through an equalizer; and obtaining the optimal signal compensation of different link channels according to the signal attenuation of all the link channels.
Writing the optimized parameters of the equalizer to be tested further comprises determining the number of link channels; the specific process for determining the number of the link channels comprises the following steps: and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
The method for evaluating the attenuation initial value of the link channel to the chip to be tested comprises the following steps: and searching the attenuation initial value of the chip to be tested in the link channel design standard specification. It can be seen that the evaluation of PCIe4 and AIC (… devices such as PCIe network card) is 8.0dB, so that the design will design ± 3dB channel attenuation with 8.0dB as the center, and add a switch control chip to both the end near the gold finger and the chip to be tested for channel switching. In the invention, two switches are used for switching different lengths in figure 1, 8dB +/-3 dB is taken as a reference, and every 0.5dB is a first-class distance, so that 13 groups of channels in total can be switched in loss.
8dB is the error of the PCIe4.0AIC association standard in the table, the total loss actually has the channel attenuation reduction of poor/standard/good which is 30/28/27dB respectively, so that the difference between the poor and the standard is 2dB, if a harsher product is designed, the concept of +/-3 dB is provided, and 0.5 is a tolerance value which is in line with the design within +/-3 dB and can be in line with the 27-30dB range regulated by the association at present.
In step S205, obtaining the best signal compensation of different link channels according to the signal attenuation of all link channels further includes writing the best signal compensation of different link channels into the memory device of the chip to be tested.
For a tester, only one device can be installed in a single PCIe slot at one time, when a product needs to be matched with multiple devices, much labor and time are consumed for optimization testing, the invention can adopt one-time testing to finish different devices to adjust the optimal equalizer parameters, saves time, improves testing effect, and can write the corresponding optimization parameters into a chip to be tested in advance according to different products/different devices.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or changes which can be made by a person skilled in the art without creative efforts are still within the protection scope of the invention.
Claims (10)
1. The device for testing the parameters of the equalizer is characterized by comprising a chip to be tested, a first switching module and a second switching module, wherein the chip to be tested is provided with the equalizer;
the chip to be tested is used for adjusting the voltage output during the parameter test of the equalizer; the chip to be tested is in communication connection with the first switching module; link channels with different lengths are arranged between the first switching module and the second switching module according to the attenuation degree of the link; the first switching module is used for receiving the voltage output of the chip to be tested, the first switching module and the second switching module jointly realize the switching of different link channels to obtain the signal attenuation of different links, and the equalizer is used for obtaining the signal compensation of different link channels according to the signal attenuation of different links.
2. The device for testing parameters of an equalizer according to claim 1, wherein the second switch chip is connected to a gold finger;
and the second exchange chip outputs corresponding signal compensation in different link channel margin tests through the golden finger.
3. The apparatus of claim 1, wherein the method for determining the number of link channels comprises:
and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
4. The apparatus for testing equalizer parameters according to claim 1, wherein the setting of the link paths with different lengths between the first switching module and the second switching module according to the link attenuation degree further comprises: and a jump cap is arranged on each link channel and used for realizing hardware switching.
5. The device for testing parameters of an equalizer according to claim 1, wherein the chip to be tested for setting the equalizer includes but is not limited to a PCIe network card.
6. The device for testing parameters of an equalizer according to any one of claims 1 to 5, wherein the testing device is connected to a server, a switch or any device under test of a computer through a golden finger.
7. A method for testing parameters of an equalizer is realized based on a device for testing the parameters of the equalizer, and is characterized by comprising the following steps:
setting the voltage output of a chip to be tested;
selecting a first link channel, and performing margin test according to the voltage output of the chip to be tested to obtain the signal attenuation of the first link channel;
switching other link channels except the first link channel to finish the attenuation test of all the link channels;
receiving signal attenuation of all link channels through an equalizer; and obtaining the optimal signal compensation of different link channels according to the signal attenuation of all the link channels.
8. The method of claim 7, wherein the signal attenuations of all link paths are received by the equalizer; obtaining the optimal signal compensation of different link channels according to the signal attenuation of all the link channels, and writing the optimal signal compensation of different link channels into the storage device of the chip to be tested.
9. The method of claim 7, wherein the writing of the optimized parameters of the equalizer to be tested further comprises determining the number of link lanes; the specific process for determining the number of the link channels comprises the following steps: and evaluating the attenuation initial value of the link channel to the chip to be tested, setting an upper and lower amplitude range by taking the initial value as the center, and traversing by taking a first-level distance as a step length to obtain the number of the link channels.
10. The method of claim 9, wherein the method for evaluating the attenuation initial value of the link channel to the chip under test comprises: and searching the attenuation initial value of the chip to be tested in the link channel design standard specification.
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