CN114628498B - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN114628498B CN114628498B CN202210525998.1A CN202210525998A CN114628498B CN 114628498 B CN114628498 B CN 114628498B CN 202210525998 A CN202210525998 A CN 202210525998A CN 114628498 B CN114628498 B CN 114628498B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000002955 isolation Methods 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 230000009977 dual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
Abstract
The invention provides a semiconductor device which comprises a substrate, a first buried layer positioned on part of the substrate, an epitaxial layer positioned on the first buried layer and the substrate, a triode unit positioned in the epitaxial layer, a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region sequentially surround the triode unit, base regions of the first isolation region and the triode unit are of the same conductivity type, the second isolation region, an emitting region and a collecting region of the triode unit and the first buried layer are of the same conductivity type, and the second isolation region is connected with the first buried layer. The first buried layer and the second isolation region can form a protection ring to isolate the substrate from the triode unit, so that the noise of the substrate is prevented from influencing the performance of the triode unit; the triode unit is used as an effective triode in the semiconductor device, the collector region, the first isolation region and the second isolation region can form an additional triode, and the second isolation region and the substrate can also form a diode, so that the noise of the substrate is further isolated.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
Bipolar Junction Transistors (BJTs) are widely used in various types of analog circuits such as amplifiers, comparators, switching circuits, oscillating circuits, or bandgap reference circuits. At present, a vertical bipolar junction transistor is usually formed in an epitaxial layer of a substrate to form a triode unit, however, the isolation performance between the substrate and the triode unit is poor, and the performance of the triode unit is affected by the noise of the substrate. In order to improve the isolation performance between the substrate and the triode unit, a deep buried layer is usually required to be manufactured to completely surround the triode unit, although the deep buried layer can isolate a part of noise of the substrate, the isolation effect is limited, and the noise of the substrate still affects the performance of the triode unit, so that the performance of the device cannot be further improved.
Disclosure of Invention
The invention aims to provide a semiconductor device, which aims to solve the problem that the isolation performance between a substrate and a triode unit of the conventional semiconductor device cannot be further improved.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
a substrate;
a first buried layer located on a portion of the substrate;
the epitaxial layer is positioned on the first buried layer and the substrate;
the triode unit is positioned in the epitaxial layer and comprises an emitter region, a base region and a collector region; and the number of the first and second groups,
the first isolation region and the second isolation region are located in the epitaxial layer and sequentially surround the triode unit from inside to outside, the first isolation region and the base region are of the same conductive type, the second isolation region, the emitter region, the collector region and the first buried layer are of the same conductive type, and the second isolation region is connected with the first buried layer.
Optionally, the method further includes:
and the second buried layer is positioned on part of the first buried layer, the second buried layer and the first isolation region have the same conductivity type, and the first isolation region is connected with the second buried layer.
Optionally, the first isolation region and the second isolation region are used for applying the same voltage.
Optionally, the voltage is 0V-120V.
Optionally, the method further includes:
and the connecting well region is positioned between the second isolation region and the first buried layer, the connecting well region and the second isolation region have the same conductivity type, and the second isolation region is connected with the first buried layer through the connecting well region.
Optionally, the connection well region includes at least two stacked sub-well regions.
Optionally, the method further includes:
the drift region is positioned in the N-type epitaxial layer, the drift region and the collector region have the same conductivity type, and the emitter region, the base region and the collector region are all positioned in the drift region.
Optionally, the triode unit is an NPN triode unit or a PNP triode unit.
Optionally, the first isolation region includes a first well region and a first doped region located in the first well region, and the first well region and the first doped region have the same conductivity type; and/or the second isolation region comprises a second well region and a second doped region positioned in the second well region, and the second well region and the second doped region have the same conductivity type; and/or the base region comprises a third well region and a third doped region positioned in the third well region, and the third well region and the third doped region have the same conductivity type; and/or the collector region comprises a fourth well region and a fourth doped region positioned in the fourth well region, and the fourth well region and the fourth doped region have the same conductivity type.
Optionally, the emitter region is located in the third well region, the third doped region surrounds the emitter region, and the collector region surrounds the third well region.
Optionally, the thickness of the epitaxial layer is greater than or equal to 12 microns.
The semiconductor device provided by the invention comprises a substrate, a first buried layer positioned on part of the substrate, an epitaxial layer positioned on the first buried layer and the substrate, a triode unit positioned in the epitaxial layer, a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region sequentially surround the triode unit, base regions of the first isolation region and the triode unit have the same conductivity type, an emitter region and a collector region of the triode unit and the first buried layer have the same conductivity type, and the second isolation region is connected with the first buried layer. According to the invention, the first buried layer and the second isolation region can form a protection ring to isolate the substrate and the triode unit, so that the noise of the substrate is prevented from influencing the performance of the triode unit; meanwhile, the triode unit is used as an effective triode in the semiconductor device, the collector region, the first isolation region and the second isolation region can form an additional triode, and the second isolation region and the substrate can also form a diode, so that the substrate and the triode unit are further isolated, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view along a-a of the semiconductor device of fig. 1;
fig. 3 is an equivalent schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;
fig. 5 is a schematic top view of a semiconductor device according to a third embodiment of the present invention;
fig. 6 is a schematic sectional view along a-a of the semiconductor device in fig. 5;
fig. 7 is an equivalent schematic diagram of a semiconductor device according to a third embodiment of the present invention;
wherein the reference numerals are:
101-a substrate; 102-an epitaxial layer; 201-a first buried layer; 202-a second buried layer; 300-a triode unit; 301-an emission area; 302-base region; 302 a-a third doped region; 302 b-a third well region; 303-collector region; 303 a-a fourth doped region; 303 b-a fourth well region; 401 — a first isolation region; 401 a-a first doped region; 401 b-a first well region; 402-a second isolation region; 402 a-second doped region; 402 b-a second well region; 403-connecting the well region; 500-a drift region; 600-an isolation structure;
d11-a first NPN transistor; d21-a second NPN transistor; d12-a first PNP transistor; d22-a second PNP transistor; d31 — first diode; d32-second diode.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Fig. 1 is a schematic top view of a semiconductor device provided in this embodiment, and fig. 2 is a schematic cross-sectional view of the semiconductor device in fig. 1 along a direction a-a. As shown in fig. 1 and fig. 2, the present embodiment provides a semiconductor device, which includes a substrate 101, a first buried layer 201, an epitaxial layer 102, a triode unit 300, a first isolation region 401, and a second isolation region 402.
Specifically, the substrate 101 is a P-type substrate, and the first buried layer 201 is located on a portion of the substrate 101 to cover a portion of the top surface of the substrate 101; the epitaxial layer 102 is an N-type epitaxial layer, and the epitaxial layer 102 is located on the first buried layer 201 and the substrate 101 to cover the remaining top surfaces of the first buried layer 201 and the substrate 101.
It should be understood that the substrate 101 is not limited to be a P-type substrate, and the epitaxial layer 102 is also not limited to be an N-type epitaxial layer, in other embodiments, the substrate 101 may also be an N-type substrate, and the epitaxial layer 102 may also be a P-type epitaxial layer, which is not described herein again.
Further, a drift region 500 is provided in the epitaxial layer 102, the drift region 500 is located above the first buried layer 201, the transistor unit 300 is located in the drift region 500, and the drift region 500 may serve to isolate the substrate 101 from the transistor unit 300, so as to prevent noise in the substrate 101 from affecting the performance of the transistor unit 300.
In this embodiment, the drift region 500 extends downward from the top surface of the epitaxial layer 102 to the top surface of the first buried layer 201, that is, the bottom surface of the drift region 500 is in contact with the top surface of the first buried layer 201, but this should not be limited thereto, and the bottom surface of the drift region 500 may not be in contact with the top surface of the first buried layer 201, but may have a certain distance.
The triode unit 300 includes an emitter region 301, a base region 302, and a collector region 303. Specifically, the base region 302 includes a third well region 302b and a third doped region 302a, the third well region 302b and the third doped region 302a have the same conductivity type, and the third doped region 302a is located in the third well region 302b and is annular; the emitter region 301 is also located within the third well region 302b, and the emitter region 301 is surrounded by the third doped region 302a, the emitter region 301 having a different conductivity type than the third well region 302b and the third doped region 302 a; the collector region 303 includes a fourth well region 303b and a fourth doped region 303a, the fourth well region 303b and the fourth doped region 303a have the same conductivity type, the fourth doped region 303a is located in the fourth well region 303b and is annular, and the base region 302 is surrounded by the collector region 303. The emitter region 301, the base region 302, and the collector region 303 may be drawn out to serve as an emitter, a base, and a collector of the triode unit 300, respectively.
In this embodiment, the triode unit 300 is an NPN triode unit, so that the conductivity types of the emitter region 301 and the collector region 303 are both N-type, and the conductivity type of the base region 302 is P-type, that is: the conductivity types of the emitter region 301, the fourth well region 303b, the fourth doped region 303a, and the drift region 500 are all N-type, and the conductivity types of the third well region 302b and the third doped region 302a are all P-type.
With reference to fig. 1 and fig. 2, the first isolation region 401 is located in the epitaxial layer 102 and includes a first well region 401b and a first doped region 401a, the first well region 401b and the first doped region 401a have the same conductivity type, and the first doped region 401a is located in the first well region 401 b. In this embodiment, the first isolation region 401 and the base region 302 have the same conductivity type, so the conductivity type of the first isolation region 401 is P-type, that is: the conductivity types of the first well region 401b and the first doped region 401a are both P-type.
Further, the first isolation region 401 is annular and surrounds the triode unit 300, that is: the first well region 401b and the first doped region 401a are both ring-shaped to surround the triode unit 300.
With continued reference to fig. 1 and 2, the second isolation region 402 is disposed in the epitaxial layer 102 and includes a second well region 402b and a second doped region 402a, the second well region 402b and the second doped region 402a have the same conductivity type, and the second doped region 402a is disposed in the second well region 402 b. In this embodiment, the second isolation region 402, the emitter region 301, the collector region 303, and the first buried layer 201 have the same conductivity type, so the conductivity types of the second isolation region 402 and the first buried layer 201 are both N-type, that is: the conductivity types of the second well region 402b and the second doped region 402a are both N-type.
Further, the second isolation region 402 is annular and surrounds the first isolation region 401, that is: the second well region 402b and the second doped region 402a are both ring-shaped to surround the first isolation region 401. As can also be seen from fig. 1, the first isolation region 401 and the second isolation region 402 sequentially surround the triode unit 300 from inside to outside.
In this embodiment, the second isolation region 402 is connected to the first buried layer 201. Specifically, the epitaxial layer 102 further has a connection well region 403, and the connection well region 403 is located between the second well region 402b and the first buried layer 201 to connect the second well region 402b and the first buried layer 201, and further connect the second isolation region 402 and the first buried layer 201.
It is to be understood that, since the second well region 402b has a ring shape, the connecting well region 403 preferably has a ring shape; also, since the connection well region 403 is used to connect the second isolation region 402 and the first buried layer 201, the connection well region 403 and the second isolation region 402 and the first buried layer 201 should have the same conductivity type, that is: the conductivity type of the connection well 403 is N-type.
In this embodiment, the number of the connection well regions 403 is one, and in other embodiments, if the thickness of the epitaxial layer 102 is larger, the connection well regions 403 may include at least two stacked sub-well regions, so as to reduce the difficulty in manufacturing the connection well regions 403; of course, as an alternative embodiment, the connection well region 403 may also be omitted, and the first well region 401b is directly extended downward to the top surface of the first buried layer 201, so as to connect the second isolation region 402 with the first buried layer 201.
Optionally, the thickness of the epitaxial layer 101 may be greater than or equal to 12 micrometers, but should not be limited thereto.
It is understood that the isolation structures 600 are disposed between the emitter region 301 and the third doped region 302a, between the third doped region 302a and the fourth doped region 303a, between the fourth doped region 303a and the first doped region 401a, and between the first doped region 401a and the second doped region 402a, so as to avoid mutual influence between adjacent doped regions.
Fig. 3 is an equivalent schematic diagram of the semiconductor device provided in this embodiment. As shown in fig. 3, the transistor unit 300 forms a first NPN transistor D11, the collector region 303, the first isolation region 401 and the second isolation region 402 may form a second NPN transistor D21, and the second isolation region 402 and the substrate 101 may form a first diode D31. When the semiconductor device is in use, the first isolation region 401 and the second isolation region 402 are used for applying the same voltage, for example, a voltage of 0V to 120V may be applied, the first NPN transistor D11 is used as an active transistor, and the first buried layer 201 and the second isolation region 402 may form a guard ring to isolate the substrate 101 from the first NPN transistor D11, so as to prevent noise of the substrate 101 from affecting the performance of the first NPN transistor D11; meanwhile, the second NPN triode D21 and the first diode D31 can further isolate the first NPN triode D11 from the substrate 101, so that the noise of the substrate 101 is prevented from affecting the performance of the first NPN triode D11, and compared with the isolation with only one diode, the isolation effect is better.
Example two
Fig. 4 is a schematic cross-sectional view of the semiconductor device provided in this embodiment. As shown in fig. 4, the difference from the first embodiment is that, in this embodiment, the semiconductor device further includes a second buried layer 202.
Specifically, the second buried layer 202 is located on a portion of the first buried layer 201 to cover a top surface of the first buried layer 201. The second buried layer 202 may be considered to be located within the epitaxial layer 102, or may be considered to be sandwiched between the first buried layer 201 and the epitaxial layer 102, depending on the fabrication process of the second buried layer 202.
Further, the second buried layer 202 and the first isolation region 401 have the same conductivity type, and thus the conductivity type of the second buried layer 202 is P-type.
In this embodiment, the first isolation region 401 is connected to the second buried layer 202. Specifically, the first well region 401b extends down to the top surface of the second buried layer 202, thereby connecting the first isolation region 401 with the second buried layer 202. As an alternative embodiment, the first isolation region 401 may also be connected to the second buried layer 202 by using an additional connection well region, which is not illustrated here.
It is understood that, compared to the first embodiment, in the present embodiment, by adding the second buried layer 202, the second buried layer 202 and the first isolation region 401 may form another guard ring, and the dual guard ring structure may further isolate noise in the substrate 101, so as to improve performance of the semiconductor device.
EXAMPLE III
Fig. 5 is a schematic top view of the semiconductor device provided in the present embodiment, and fig. 6 is a schematic cross-sectional view of the semiconductor device in fig. 5 along the a-a direction. As shown in fig. 5 and fig. 6, the difference between the first and second embodiments is that in this embodiment, the transistor unit 300 is a PNP transistor unit.
Specifically, in this embodiment, the conductivity types of the emitter region 301 and the collector region 303 are both P-type, and the conductivity type of the base region 302 is N-type, that is: the conductivity types of the emitter region 301, the fourth well region 303b, the fourth doped region 303a, and the drift region 500 are all P-type, and the conductivity types of the third well region 302b and the third doped region 302a are all N-type.
Correspondingly, the first isolation region 401 and the base region 302 have the same conductivity type, so the conductivity type of the first isolation region 401 is N-type, that is: the conductivity types of the first well region 401b and the first doped region 401a are both N-type. The second isolation region 402, the emitter region 301, the collector region 303 and the first buried layer 201 have the same conductivity type, so the conductivity types of the second isolation region 402 and the first buried layer 201 are P-type, that is: the conductivity types of the second well region 402b and the second doped region 402a are both P-type.
Fig. 7 is an equivalent schematic diagram of the semiconductor device provided in this embodiment. As shown in fig. 7, the transistor unit 300 may form a first PNP transistor D12, the emitter region 301, the first isolation region 401, and the second isolation region 402 may form a second PNP transistor D22, and the second isolation region 402 and the epitaxial layer 102 may form a second diode D32. When the semiconductor device is used, the first isolation region 401 and the second isolation region 402 are used for applying the same voltage, for example, a voltage of 0V to 120V can be applied, the first PNP transistor D12 is used as an active transistor, and the first buried layer 201 and the second isolation region 402 can form a guard ring to isolate the substrate 101 from the first PNP transistor D12, so as to prevent noise of the substrate 101 from affecting the performance of the first PNP transistor D12; meanwhile, the second PNP triode D22 and the second diode D32 can further isolate the first PNP triode D12 from the substrate 101, so that the influence of noise of the substrate 101 on the performance of the first PNP triode D12 is avoided, and compared with the isolation with only one diode, the isolation effect is better.
In summary, in the semiconductor device provided in the embodiment of the present invention, the semiconductor device includes a substrate, a first buried layer located on a portion of the substrate, an epitaxial layer located on the first buried layer and the substrate, and a triode unit, a first isolation region and a second isolation region located in the epitaxial layer, where the first isolation region and the second isolation region sequentially surround the triode unit, base regions of the first isolation region and the triode unit have the same conductivity type, the second isolation region, an emitter region and a collector region of the triode unit and the first buried layer have the same conductivity type, and the second isolation region is connected to the first buried layer. In the invention, the first buried layer and the second isolation region can form a guard ring to isolate the substrate from the triode unit, so that the noise of the substrate is prevented from influencing the performance of the triode unit; meanwhile, the triode unit is used as an effective triode in the semiconductor device, the collector region, the first isolation region and the second isolation region can form an additional triode, and the second isolation region and the substrate can also form a diode, so that the substrate and the triode unit are further isolated, and the performance of the semiconductor device is improved.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (11)
1. A semiconductor device, comprising:
a substrate;
a first buried layer located on a portion of the substrate;
the epitaxial layer is positioned on the first buried layer and the substrate;
the triode unit is positioned in the epitaxial layer and comprises an emitter region, a base region and a collector region; and the number of the first and second groups,
the first isolation region and the second isolation region are located in the epitaxial layer and sequentially surround the triode unit from inside to outside, the first isolation region and the base region are of the same conductive type, the second isolation region, the emitter region, the collector region and the first buried layer are of the same conductive type, and the second isolation region is connected with the first buried layer.
2. The semiconductor device according to claim 1, further comprising:
and the second buried layer is positioned on part of the first buried layer, has the same conductivity type with the first isolation region, and is connected with the second buried layer by the first isolation region.
3. The semiconductor device according to claim 1 or 2, wherein the first isolation region and the second isolation region are used to apply the same voltage.
4. The semiconductor device according to claim 3, wherein the voltage is 0V to 120V.
5. The semiconductor device according to claim 1 or 2, further comprising:
and the connecting well region is positioned between the second isolation region and the first buried layer, the connecting well region and the second isolation region have the same conductivity type, and the second isolation region is connected with the first buried layer through the connecting well region.
6. The semiconductor device of claim 5, wherein the link well region comprises at least two stacked sub-well regions.
7. The semiconductor device according to claim 1, further comprising:
the drift region is positioned in the N-type epitaxial layer, the drift region and the collector region have the same conductivity type, and the emitter region, the base region and the collector region are all positioned in the drift region.
8. The semiconductor device according to claim 1, wherein the transistor cell is an NPN transistor cell or a PNP transistor cell.
9. The semiconductor device of claim 1, wherein the first isolation region comprises a first well region and a first doped region located in the first well region, the first well region and the first doped region having a same conductivity type; and/or the second isolation region comprises a second well region and a second doped region positioned in the second well region, and the second well region and the second doped region have the same conductivity type; and/or the base region comprises a third well region and a third doped region positioned in the third well region, and the third well region and the third doped region have the same conductivity type; and/or the collector region comprises a fourth well region and a fourth doped region positioned in the fourth well region, and the fourth well region and the fourth doped region have the same conductivity type.
10. The semiconductor device of claim 1, wherein the emitter region is located within the third well region, the third doped region surrounds the emitter region, and the collector region surrounds the third well region.
11. The semiconductor device of claim 1, wherein the epitaxial layer has a thickness greater than or equal to 12 microns.
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|---|---|---|---|---|
| US5565701A (en) * | 1991-07-03 | 1996-10-15 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors |
| CN1604327A (en) * | 2003-09-29 | 2005-04-06 | 三洋电机株式会社 | Semiconductor integrated circuit device |
| CN1983626A (en) * | 2005-11-30 | 2007-06-20 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
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| CN114628498A (en) | 2022-06-14 |
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