CN113823678A - High-voltage NPN device - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
The invention relates to a high-voltage NPN device of an integrated JFET tube clamping structure, which comprises a low-voltage NPN triode and a JFET tube, wherein the low-voltage NPN triode is integrated with the JFET tube; the collector of the low-voltage NPN triode is connected with the source electrode of the JFET tube; the drain electrode of the JFET tube is used as the collector electrode of the high-voltage NPN device; and the base electrode and the emitter electrode of the low-voltage NPN triode are respectively used as the base electrode and the emitter electrode of the high-voltage NPN device. The invention can meet the requirement of high pressure resistance by using the conventional low pressure process design and manufacture without increasing the area of other devices.
Description
Technical Field
The invention relates to a high-voltage NPN device, in particular to a high-voltage NPN device integrated with a JFET tube clamping structure.
Background
In chip design, an NPN transistor is widely used for current amplification, signal processing, or electronic switching, and many applications require the NPN transistor to operate under high voltage conditions. In chip design, a boundary of 5V is generally used, low voltage is below 5V, and high voltage is higher than 5V. At present, in mainstream integrated circuit manufacturing processes (including Bipolar, BiCMOS, BCD and the like), an epitaxial process is adopted for manufacturing an NPN transistor with good performance, and most devices are manufactured in the epitaxial layer. The NPN transistor is formed with other devices during the fabrication process. If it is desired to fabricate a high voltage NPN device, thicker epitaxy, deeper isolation and base diffusions are used, which necessarily results in increased spacing between the individual diffusions with a corresponding dramatic increase in the size of the NPN and most devices. For a product with only an NPN tube or a part of an NPN tube operating under high voltage, the area of most devices is increased due to the requirement of a small number of high voltage devices, which is a very poor design for cost performance. .
Disclosure of Invention
The invention aims to provide a high-voltage NPN device integrated with a JFET tube clamping structure, which is designed and manufactured by using a conventional low-voltage process, does not need to increase the area of other devices, and can meet the requirement of high voltage resistance.
The technical scheme for realizing the purpose of the invention is as follows:
a high-voltage NPN device comprises a low-voltage NPN triode and is characterized by further comprising a JFET (junction field-effect transistor) tube, wherein the low-voltage NPN triode is integrated with the JFET tube; the collector of the low-voltage NPN triode is connected with the source electrode of the JFET tube; the drain electrode of the JFET tube is used as the collector electrode of the high-voltage NPN device; and the base electrode and the emitter electrode of the low-voltage NPN triode are respectively used as the base electrode and the emitter electrode of the high-voltage NPN device.
Furthermore, an N-type epitaxial island is arranged above the P-type substrate, and a first N-type buried layer and a second N-type buried layer are sequentially arranged between the lower end of the N-type epitaxial island and the P-type substrate from left to right; a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the N-type epitaxial island, the second P well region is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top and are used as a source electrode of the JFET tube and a collector electrode of the low-voltage NPN triode;
a P base diffusion area is arranged in the N-type epitaxial island, the P base diffusion area is located on the right side of the second deep N-well diffusion area and the right side of the second N + diffusion area, a P + diffusion area and a third N + diffusion area are arranged in the P base diffusion area and correspond to the left end and the right end respectively, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and serves as a base leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the third N + diffusion area through a contact hole and a metal wire and serves as a leading-out end of an emitting electrode of the low-voltage NPN triode.
Furthermore, a first P-well region and a third P-well region are arranged on two sides of the N-type epitaxial island, the first P-well region is positioned on the left side of the first deep N-well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P-well region; the third P well region is positioned on the right side of the Pbase diffusion region, and a second P-type buried layer is connected below the third P well region.
Furthermore, the P-type substrate, the second P-well region and the N-type epitaxial island corresponding to the drain region of the JFET transistor and the outer side of the gate all adopt a light doped silicon material with withstand voltage or high withstand voltage; the JFET tube drain region and the N-type epitaxial island outside the grid electrode are N-type epitaxial island regions corresponding to the position between the first deep N-well diffusion region and the second deep N-well diffusion region.
Furthermore, an N-type epitaxial island is arranged above the P-type substrate, and a second N-type buried layer is arranged between the lower end of the N-type epitaxial island and the P-type substrate; a first N + diffusion region is arranged at the upper end of the N-type epitaxial island and is positioned on the left side of the second N-type buried layer;
ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET tube and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the N-type epitaxial island and is positioned between the first N + diffusion region and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
the second N-type buried layer is used as a source electrode of the JFET tube and a collector electrode of the low-voltage NPN triode;
and a P base diffusion area is arranged in the N-type epitaxial island and is positioned above the second N-type buried layer, a P + diffusion area and a third N + diffusion area are respectively arranged in the P base diffusion area corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and is used as a base leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the third N + diffusion area through the contact hole and the metal wire and is used as a leading-out end of an emitting electrode of the low-voltage NPN triode.
Furthermore, a first N-type epitaxial island and a second N-type epitaxial island are arranged on the P-type substrate from left to right adjacently or at intervals, and a first N-type buried layer and a second N-type buried layer are sequentially arranged between the lower end of the first N-type epitaxial island and the P-type substrate from left to right; a third N-type buried layer is arranged between the lower end of the second N-type epitaxial island and the P-type substrate;
a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the first N-type epitaxial island and is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top, and ohmic contact is formed above the second N + diffusion region through a contact hole and a metal wire and is used as a source electrode leading-out end of the JFET tube;
a third deep N-well diffusion region and a third N + diffusion region are sequentially connected above the third N-type buried layer from bottom to top, and ohmic contact is formed above the third N + diffusion region through a contact hole and a metal wire and is used as a collector leading-out end of the low-voltage NPN triode; a collector leading-out end of the low-voltage NPN triode is connected with a source leading-out end of the JFET tube;
a P base diffusion region is arranged in the second N-type epitaxial island, the P base diffusion region is located on the right side of the third deep N-well diffusion region and the third N + diffusion region, a P + diffusion region and a fourth N + diffusion region are respectively arranged in the P base diffusion region corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion region through a contact hole and a metal wire and serves as a base leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the fourth N + diffusion region through the contact hole and the metal wire and serves as a leading-out end of an emitter of the low-voltage NPN triode.
Furthermore, a first P-well region is arranged on the left side of the first N-type epitaxial island, the first P-well region is located on the left side of the first deep N-well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P-well region; a fourth P well region is arranged on the right side of the second N-type epitaxial island and located on the right side of the P base diffusion region, and a third P-type buried layer is connected below the fourth P well region; and a third P-type well region is arranged between the first N-type epitaxial island and the second N-type epitaxial island, is positioned between the second deep N-well diffusion region and the third deep N-well diffusion region, and is connected with a second P-type buried layer below the third P-type well region.
Furthermore, the P-type substrate, the second P-well region and the first N-type epitaxial island corresponding to the drain region of the JFET transistor and the outer side of the gate all adopt a voltage-resistant or high-voltage-resistant lightly doped silicon material; the JFET tube drain region and the first N-type epitaxial island outside the grid electrode are the first N-type epitaxial island region between the first deep N-well diffusion region and the second deep N-well diffusion region.
Furthermore, a first N-type epitaxial island and a second N-type epitaxial island are arranged on the P-type substrate from left to right adjacently or at intervals, and a first N + diffusion region and a second N + diffusion region are sequentially arranged at the upper end of the first N-type epitaxial island from left to right; a third N + diffusion region is arranged at the upper end of the second N-type epitaxial island;
ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET tube and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the first N-type epitaxial island and is positioned between the first N + diffusion region and the second N + diffusion region, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
ohmic contact is formed above the second N + diffusion region through a contact hole and a metal wire and is used as a source electrode leading-out end of the JFET tube;
ohmic contact is formed above the third N + diffusion region through a contact hole and a metal wire and is used as a collector leading-out end of the low-voltage NPN triode; a collector leading-out end of the low-voltage NPN triode is connected with a source leading-out end of the JFET tube; a third N-type buried layer is arranged below the third N + diffusion region;
a P base diffusion area is arranged in the second N-type epitaxial island and located on the right side of the third N + diffusion area, a P + diffusion area and a fourth N + diffusion area are arranged in the P base diffusion area and correspond to the left end and the right end respectively, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and serves as a base electrode leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the fourth N + diffusion area through the contact hole and the metal wire and serves as an emitting electrode leading-out end of the low-voltage NPN triode.
Furthermore, the P-type substrate, the second P-well region and the first N-type epitaxial island corresponding to the drain region of the JFET transistor and the outer side of the gate all adopt a voltage-resistant or high-voltage-resistant lightly doped silicon material; the JFET tube drain region and the first N-type epitaxial island on the outer side of the grid electrode are the first N-type epitaxial island region between the first N + diffusion region and the second N + diffusion region.
The invention has the following beneficial effects:
the low-voltage NPN triode comprises a low-voltage NPN triode and a JFET (junction field effect transistor), wherein the low-voltage NPN triode is integrated with the JFET; the collector of the low-voltage NPN triode is connected with the source electrode of the JFET tube; the drain electrode of the JFET tube is used as the collector electrode of the high-voltage NPN device; and the base electrode and the emitter electrode of the low-voltage NPN triode are respectively used as the base electrode and the emitter electrode of the high-voltage NPN device. According to the invention, the JFET tube connected in series is added on the collector electrode of the low-voltage NPN tube to play a role of voltage clamping, so that a high-voltage resistant NPN device is formed, and the NPN device capable of working at high voltage is manufactured on the premise of not increasing the manufacturing cost and the area of other devices.
When designing a chip, the NPN working under high voltage uses the structure, other devices still use conventional low-voltage devices, and the manufacture of the chip can continue to use a low-voltage process. The method has the advantages of effectively simplifying the design of an analog circuit, simplifying the manufacturing process of a high-voltage circuit, improving the cost performance of products and increasing the competitiveness of the products. The invention further provides a specific structural design that the JFET tube and the low-voltage NPN triode are positioned in the same N-type epitaxial island and are respectively positioned in two adjacent or separated N-type epitaxial islands, thereby further effectively ensuring that the high-voltage resistance requirement is met on the premise of not increasing the area of other devices, further effectively simplifying the design of an analog circuit, simplifying the manufacturing process of a high-voltage circuit and improving the cost performance of products.
Drawings
FIG. 1 is a circuit schematic of the present invention;
FIG. 2 is a schematic structural diagram of a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a third embodiment of the present invention.
Detailed Description
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
As shown in fig. 1, the low-voltage NPN transistor T1 and the JFET transistor T2 are included, and the low-voltage NPN transistor T1 is integrated with the JFET transistor T2; the collector of the low-voltage NPN triode T1 is connected with the source electrode of the JFET tube T2; the drain electrode of the JFET tube T2 is used as the collector electrode of the high-voltage NPN device; the base and emitter of the low voltage NPN transistor T1 function as the base and emitter of the high voltage NPN device, respectively.
Based on the circuit structure, the specific structure of the high-voltage NPN device is as follows:
the first embodiment is as follows:
as shown in fig. 2, an N-type epitaxial island is disposed above a P-type substrate, and a first N-type buried layer and a second N-type buried layer are sequentially disposed from left to right between the lower end of the N-type epitaxial island and the P-type substrate;
a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the N-type epitaxial island, the second P well region is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top and are used as a source electrode of the JFET tube and a collector electrode of the low-voltage NPN triode;
a P base diffusion area is arranged in the N-type epitaxial island, the P base diffusion area is located on the right side of the second deep N-well diffusion area and the right side of the second N + diffusion area, a P + diffusion area and a third N + diffusion area are arranged in the P base diffusion area and correspond to the left end and the right end respectively, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and serves as a base leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the third N + diffusion area through a contact hole and a metal wire and serves as a leading-out end of an emitting electrode of the low-voltage NPN triode.
A first P well region and a third P well region are arranged on two sides of the N-type epitaxial island, the first P well region is positioned on the left side of the first deep N well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P well region; the third P well region is positioned on the right side of the P base diffusion region, and a second P-type buried layer is connected below the third P well region.
First field, second field, fourth field are equipped with respectively above first P well region, second P well region, the third P well region, be equipped with the third field between second N + diffusion zone and the P base diffusion zone, be three active area between four fields.
The P-type substrate, the second P well region and the N-type epitaxial island corresponding to the drain region of the JFET tube and the outer side of the grid are all made of a voltage-resistant or high-voltage-resistant lightly-doped silicon material; the JFET tube drain region and the N-type epitaxial island outside the grid electrode are N-type epitaxial island regions corresponding to the position between the first deep N-well diffusion region and the second deep N-well diffusion region.
In implementation, the first N-type buried layer and the first deep N-well diffusion region, the second N + diffusion region and the second deep N-well diffusion region may not be provided, and the size of the second N-type buried layer may be reduced.
When the high-voltage NPN device works, high voltage applied to the high-voltage NPN device is directly transmitted to the drain region of the JFET tube. Even in a low-voltage process, because the P-type substrate, the second P-well region, the N-type epitaxial island corresponding to the JFET drain region and the outer side of the grid are all made of a voltage-resistant lightly-doped silicon material, and the doping concentration is low, the junction breakdown voltage among the N-type epitaxial island, the second P-well region and the P-type substrate is also over 20V. When the voltage from the drain electrode and the source electrode of the JFET tube to the P-type substrate does not exceed the junction breakdown voltage, the JFET tube can work normally. When the high-voltage NPN device works, the JFET tube works in a pinch-off region or a saturation region, and the source voltage of the JFET tube does not exceed the pinch-off voltage Vp at the highest, so that the clamping effect is achieved, the collector voltage of the low-voltage NPN tube does not exceed the pinch-off voltage Vp of the JFET tube at the highest, and the low-voltage NPN device can work normally. Therefore, when the JFET tube and the low-voltage NPN tube are combined together to form a high-voltage NPN device, the high-voltage NPN device can work under the condition of a high voltage which is far larger than 5V.
Example two:
as shown in fig. 3, a first N-type epitaxial island and a second N-type epitaxial island are adjacently arranged above a P-type substrate from left to right, and a first N-type buried layer and a second N-type buried layer are sequentially arranged between the lower end of the first N-type epitaxial island and the P-type substrate from left to right; a third N-type buried layer is arranged between the lower end of the second N-type epitaxial island and the P-type substrate;
a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the first N-type epitaxial island and is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top, and ohmic contact is formed above the second N + diffusion region through a contact hole and a metal wire and is used as a source electrode leading-out end of the JFET tube;
a third deep N-well diffusion region and a third N + diffusion region are sequentially connected above the third N-type buried layer from bottom to top, and ohmic contact is formed above the third N + diffusion region through a contact hole and a metal wire and is used as a collector leading-out end of the low-voltage NPN triode; a collector leading-out end of the low-voltage NPN triode is connected with a source leading-out end of the JFET tube;
a P base diffusion region is arranged in the second N-type epitaxial island, the P base diffusion region is located on the right side of the third deep N-well diffusion region and the third N + diffusion region, a P + diffusion region and a fourth N + diffusion region are respectively arranged in the P base diffusion region corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion region through a contact hole and a metal wire and serves as a base leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the fourth N + diffusion region through the contact hole and the metal wire and serves as a leading-out end of an emitter of the low-voltage NPN triode.
A first P-type well region is arranged on the left side of the first N-type epitaxial island, the first P-type well region is positioned on the left sides of the first deep N-well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P-type well region; a fourth P well region is arranged at the right side of the second N-type epitaxial island,
the fourth P well region is positioned on the right side of the P base diffusion region, and a third P-type buried layer is connected below the fourth P well region; and a third P-type well region is arranged between the first N-type epitaxial island and the second N-type epitaxial island, is positioned between the second deep N-well diffusion region and the third deep N-well diffusion region, and is connected with a second P-type buried layer below the third P-type well region.
In implementation, the first N-type buried layer, the first deep N-well diffusion region, the second N-type buried layer, and the second deep N-well diffusion region may not be provided. Or the third deep N-well diffusion region is not arranged, and the size of the third N-type buried layer is reduced.
The P-type substrate, the second P well region and the first N-type epitaxial island corresponding to the drain region of the JFET tube and the outer side of the grid are all made of a pressure-resistant lightly-doped silicon material; the JFET tube drain region and the first N-type epitaxial island outside the grid electrode are the first N-type epitaxial island region between the first deep N-well diffusion region and the second deep N-well diffusion region.
Example three:
as shown in fig. 4, the third embodiment is different from the second embodiment mainly in that the first N-type epitaxial island and the second N-type epitaxial island are spaced apart from each other, and other components may be disposed at the spacing. Although this increases the device area, the layout flexibility is increased, and the characteristics of the high-voltage NPN device formed by the high-voltage NPN device are unchanged.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. A high-voltage NPN device comprises a low-voltage NPN triode and is characterized by further comprising a JFET (junction field-effect transistor) tube, wherein the low-voltage NPN triode is integrated with the JFET tube; the collector of the low-voltage NPN triode is connected with the source electrode of the JFET tube; the drain electrode of the JFET tube is used as the collector electrode of the high-voltage NPN device; and the base electrode and the emitter electrode of the low-voltage NPN triode are respectively used as the base electrode and the emitter electrode of the high-voltage NPN device.
2. The high-voltage NPN device of claim 1, wherein an N-type epitaxial island is arranged above a P-type substrate, and a first N-type buried layer and a second N-type buried layer are arranged between the lower end of the N-type epitaxial island and the P-type substrate in sequence from left to right;
a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the N-type epitaxial island, the second P well region is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top and are used as a source electrode of the JFET tube and a collector electrode of the low-voltage NPN triode;
and a Pbase diffusion area is arranged in the N-type epitaxial island, the Pbase diffusion area is positioned on the right side of the second deep N-well diffusion area and the second N + diffusion area, a P + diffusion area and a third N + diffusion area are respectively arranged in the Pbase diffusion area corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and is used as a base electrode leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the third N + diffusion area through the contact hole and the metal wire and is used as an emitting electrode leading-out end of the low-voltage NPN triode.
3. The high voltage NPN device according to claim 2, characterized in that: a first P well region and a third P well region are arranged on two sides of the N-type epitaxial island, the first P well region is positioned on the left side of the first deep N well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P well region; the third P well region is positioned on the right side of the Pbase diffusion region, and a second P-type buried layer is connected below the third P well region.
4. The high voltage NPN device according to claim 2, characterized in that: the P-type substrate, the second P well region and the N-type epitaxial island corresponding to the drain region of the JFET tube and the outer side of the grid are all made of a voltage-resistant or high-voltage-resistant lightly-doped silicon material; the JFET tube drain region and the N-type epitaxial island outside the grid electrode are N-type epitaxial island regions corresponding to the position between the first deep N-well diffusion region and the second deep N-well diffusion region.
5. The high-voltage NPN device as claimed in claim 1, wherein an N-type epitaxial island is provided above a P-type substrate, and a second N-type buried layer is provided between the lower end of the N-type epitaxial island and the P-type substrate; a first N + diffusion region is arranged at the upper end of the N-type epitaxial island and is positioned on the left side of the second N-type buried layer;
ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET tube and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the N-type epitaxial island and is positioned between the first N + diffusion region and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
the second N-type buried layer is used as a source electrode of the JFET tube and a collector electrode of the low-voltage NPN triode;
and a Pbase diffusion region is arranged in the N-type epitaxial island, the Pbase diffusion region is positioned above the second N-type buried layer, a P + diffusion region and a third N + diffusion region are respectively arranged in the Pbase diffusion region corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion region through a contact hole and a metal wire to be used as a base electrode leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the third N + diffusion region through the contact hole and the metal wire to be used as an emitting electrode leading-out end of the low-voltage NPN triode.
6. The high voltage NPN device according to claim 1, characterized in that: a first N-type epitaxial island and a second N-type epitaxial island are arranged on the P-type substrate from left to right adjacently or at intervals, and a first N-type buried layer and a second N-type buried layer are sequentially arranged between the lower end of the first N-type epitaxial island and the P-type substrate from left to right; a third N-type buried layer is arranged between the lower end of the second N-type epitaxial island and the P-type substrate;
a first deep N-well diffusion region and a first N + diffusion region are sequentially connected above the first N-type buried layer from bottom to top, and ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the first N-type epitaxial island and is positioned above the position between the first N-type buried layer and the second N-type buried layer, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
a second deep N-well diffusion region and a second N + diffusion region are sequentially connected above the second N-type buried layer from bottom to top, and ohmic contact is formed above the second N + diffusion region through a contact hole and a metal wire and is used as a source electrode leading-out end of the JFET tube;
a third deep N-well diffusion region and a third N + diffusion region are sequentially connected above the third N-type buried layer from bottom to top, and ohmic contact is formed above the third N + diffusion region through a contact hole and a metal wire and is used as a collector leading-out end of the low-voltage NPN triode; a collector leading-out end of the low-voltage NPN triode is connected with a source leading-out end of the JFET tube;
and a Pbase diffusion area is arranged in the second N-type epitaxial island, the Pbase diffusion area is positioned on the right side of the third deep N-well diffusion area and the third N + diffusion area, a P + diffusion area and a fourth N + diffusion area are respectively arranged in the Pbase diffusion area corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire and is used as a base electrode leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the fourth N + diffusion area through a contact hole and a metal wire and is used as an emitting electrode leading-out end of the low-voltage NPN triode.
7. The high voltage NPN device according to claim 6, characterized in that: a first P-type well region is arranged on the left side of the first N-type epitaxial island, the first P-type well region is positioned on the left sides of the first deep N-well diffusion region and the first N + diffusion region, and a first P-type buried layer is connected below the first P-type well region; a fourth P well region is arranged on the right side of the second N-type epitaxial island, the fourth P well region is positioned on the right side of the Pbase diffusion region, and a third P-type buried layer is connected below the fourth P well region; and a third P-type well region is arranged between the first N-type epitaxial island and the second N-type epitaxial island, is positioned between the second deep N-well diffusion region and the third deep N-well diffusion region, and is connected with a second P-type buried layer below the third P-type well region.
8. The high voltage NPN device according to claim 7, characterized in that: the P-type substrate, the second P well region and the first N-type epitaxial island corresponding to the drain region of the JFET tube and the outer side of the grid are all made of a voltage-resistant or high-voltage-resistant lightly-doped silicon material; the JFET tube drain region and the first N-type epitaxial island outside the grid electrode are the first N-type epitaxial island region between the first deep N-well diffusion region and the second deep N-well diffusion region.
9. The high voltage NPN device according to claim 1, characterized in that: a first N-type epitaxial island and a second N-type epitaxial island are arranged on the P-type substrate from left to right adjacently or at intervals, and a first N + diffusion region and a second N + diffusion region are sequentially arranged at the upper end of the first N-type epitaxial island from left to right; a third N + diffusion region is arranged at the upper end of the second N-type epitaxial island;
ohmic contact is formed above the first N + diffusion region through a contact hole and a metal wire and is used as a drain electrode of the JFET tube and a collector leading-out end of the high-voltage NPN device;
a second P well region is arranged in the first N-type epitaxial island and is positioned between the first N + diffusion region and the second N + diffusion region, and the second P well region is connected with a P-type substrate right below the second P well region and is used as a grid electrode of the JFET tube;
ohmic contact is formed above the second N + diffusion region through a contact hole and a metal wire and is used as a source electrode leading-out end of the JFET tube;
ohmic contact is formed above the third N + diffusion region through a contact hole and a metal wire and is used as a collector leading-out end of the low-voltage NPN triode; a collector leading-out end of the low-voltage NPN triode is connected with a source leading-out end of the JFET tube; a third N-type buried layer is arranged below the third N + diffusion region;
and a Pbase diffusion area is arranged in the second N-type epitaxial island, the Pbase diffusion area is positioned on the right side of the third N + diffusion area, a P + diffusion area and a fourth N + diffusion area are respectively arranged in the Pbase diffusion area corresponding to the left end and the right end, ohmic contact is formed above the P + diffusion area through a contact hole and a metal wire to be used as a base electrode leading-out end of the low-voltage NPN triode, and ohmic contact is formed above the fourth N + diffusion area through the contact hole and the metal wire to be used as an emitting electrode leading-out end of the low-voltage NPN triode.
10. The high voltage NPN device according to claim 1, characterized in that: the P-type substrate, the second P well region and the first N-type epitaxial island corresponding to the drain region of the JFET tube and the outer side of the grid are all made of a voltage-resistant or high-voltage-resistant lightly-doped silicon material; the JFET tube drain region and the first N-type epitaxial island on the outer side of the grid electrode are the first N-type epitaxial island region between the first N + diffusion region and the second N + diffusion region.
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Application publication date: 20211221 |