CN114598169B - Control method for synchronous rectification BUCK circuit in DCM mode - Google Patents
Control method for synchronous rectification BUCK circuit in DCM mode Download PDFInfo
- Publication number
- CN114598169B CN114598169B CN202210303303.5A CN202210303303A CN114598169B CN 114598169 B CN114598169 B CN 114598169B CN 202210303303 A CN202210303303 A CN 202210303303A CN 114598169 B CN114598169 B CN 114598169B
- Authority
- CN
- China
- Prior art keywords
- voltage
- capacitor
- transistor
- power tube
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 75
- 230000002829 reductive effect Effects 0.000 claims description 26
- 230000010355 oscillation Effects 0.000 claims description 23
- 238000001514 detection method Methods 0.000 claims description 20
- 102220592496 Non-homologous end-joining factor 1_Q11A_mutation Human genes 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 101000746134 Homo sapiens DNA endonuclease RBBP8 Proteins 0.000 claims description 7
- 101000969031 Homo sapiens Nuclear protein 1 Proteins 0.000 claims description 7
- 102100021133 Nuclear protein 1 Human genes 0.000 claims description 7
- 238000005070 sampling Methods 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 description 10
- 238000004146 energy storage Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a control method for a synchronous rectification BUCK circuit in a DCM (discontinuous mode), which belongs to the technical field of power supply control and comprises a capacitor C1, a diode D1, a power tube Q1, an inductor L1, a resistor R1, a capacitor Co, a resistor Ro, a capacitor C2, a diode D2 and a power tube Q2, wherein a source electrode of the power tube Q1 is connected with a cathode of the diode D1, the capacitor C1 and a power source VIN+, and the other end of the capacitor C1 is connected with an anode of the diode D1, a drain electrode of the power tube Q1, the inductor L1, the capacitor C2, a cathode of the diode D2 and a drain electrode of the power tube Q2.
Description
Technical Field
The invention relates to the technical field of power supply control, in particular to a control method for a synchronous rectification BUCK circuit in a DCM mode.
Background
With the rapid development of technology and the changing demands of working and learning modes of people, consumer electronic products such as mobile terminals are becoming more and more important roles, and the requirements of people on the performances of the consumer electronic products are becoming more and more severe. The working time is a very important index in various performance indexes of the mobile terminal consumer electronic products. The mobile terminal is mostly powered by a battery, but the battery voltage will float along with the charging and discharging process of the battery, and a power management system is needed to stabilize the power supply voltage of each circuit module. The synchronous rectification BUCK circuit is widely adopted with the advantages of simple structure, stable performance and the like, but when the BUCK circuit works under light load, the BUCK circuit enters a DCM (Continuous Conduction Mode) mode, so that the improvement of the electric energy conversion efficiency of the synchronous rectification BUCK circuit under the DCM mode has very important significance for prolonging the standby time and the low-power output time of the mobile terminal.
Synchronous rectification BUCK circuits typically operate in DCM mode at low power outputs while avoiding reverse current flow through the shunt tubes. In recent years, in order to improve efficiency at low power output, some techniques have been applied to synchronous rectification BUCK circuits. For example, frequency modulation mode (PFM, pulse Width Modulation): along with the reduction of power output, the switching frequency of the power tube is actively reduced, and the switching frequency of the power tube is reduced, so that the switching loss is reduced to improve the efficiency, but the mode has a lower limit of frequency reduction due to the limitation of human hearing frequency spectrum, and the switching frequency is usually kept above 20 KHz; in addition, under some scenes with less severe requirements on output voltage ripple, the switching loss of the power tube can be reduced by adopting a Burst Mode (Burst Mode), so as to improve the electric energy conversion efficiency, and the basic principle is as follows: by adopting a certain control mechanism, the driving pulses of the power tube are clustered, the driving pulses in the clusters keep a certain switching frequency, and time intervals appear among the pulse clusters, so that the number of the driving pulses in unit time is reduced, the average switching frequency is equivalently reduced, and the switching loss is reduced.
When the BUCK circuit outputs low power, the principle of the method for improving efficiency is to adopt a mode of actively reducing the switching frequency or reducing the average switching frequency so as to achieve the purpose of reducing the switching loss and improving the efficiency. As shown in fig. 1, the topology structure of the synchronous rectification BUCK circuit is that Q1 is a main power tube, D1 is a body diode of Q1, Q2 is a freewheeling power tube, D2 is a body diode of Q2, C1 and C2 are drain-source parasitic capacitances of the power tubes Q1 and Q2, respectively, L1 is an energy storage inductance, R1 is a series parasitic resistance of the energy storage inductance, co is an output filter capacitance, ro is an equivalent load, VIN is an input voltage, and VOUT is an output voltage. The charge on the parasitic capacitor C1 can be released and generate heat through the Q1 conducting channel at the moment of Q1 opening, so that the efficiency of the BUCK circuit is reduced, and meanwhile, the working reliability of Q1 is also reduced. If the voltage on C1 is reduced to 50% of the original voltage when Q1 is turned on, the turn-on loss of Q1 can be reduced to 25% of the original voltage under ideal conditions, and the switching loss of Q1 can be reduced. Based on the above-mentioned control modes which are actually applied and used for improving the efficiency when the synchronous BUCK circuit outputs low power, a new control technology is provided, the turn-on voltage of the main power tube is reduced, the turn-on loss of the main power tube is reduced, and the light load efficiency of the synchronous rectification BUCK circuit working in the DCM mode is further improved.
Disclosure of Invention
The present invention is directed to a control method for a synchronous rectification BUCK circuit in DCM to solve the above-mentioned problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a control method for a synchronous rectification BUCK circuit in a DCM mode comprises a capacitor C1, a diode D1, a power tube Q1, an inductor L1, a resistor R1, a capacitor Co, a resistor Ro, a capacitor C2, a diode D2 and a power tube Q2, wherein a source electrode of the power tube Q1 is connected with a cathode of the diode D1, the capacitor C1 and a power source VIN+, the other end of the capacitor C1 is connected with an anode of the diode D1, a drain electrode of the power tube Q1, the inductor L1, the capacitor C2, a cathode of the diode D2 and a drain electrode of the power tube Q2, the other end of the inductor L1 is connected with a capacitor Co and a resistor Ro through the resistor R1, the other end of the capacitor Co, the other end of the resistor Ro and the power source VIN-, a grid electrode of the power tube Q1 is connected with a driving signal DRVA, a grid electrode of the power tube Q2 is connected with a driving signal DRVB, the drain voltage of the power tube Q1 is VOUT, the voltage at two ends of the resistor R1 is VOUT, the voltage is also comprises a sampling and holding circuit and a timer circuit, the voltage is controlled by a voltage cycle of the sampling circuit and the voltage is recorded in a voltage cycle of the voltage-controlled oscillation circuit to be the voltage-cycle of the voltage-controlled to be VREF 4; after 4 frequency division is carried out by a counter circuit, a peak detection signal of a voltage Va is obtained, the sampling and holding circuit comprises a high-speed comparator COM1, an RC differential unit, a waveform conversion module and a capacitor memory circuit, the turn-off moment of a power tube Q2, namely, the falling edge of a DRVB starts to turn off a transistor Q11 and turn on a transistor Q11A, a constant current source I2 starts to charge a capacitor C11, at the moment, the voltage Va starts to rise, VOUT and Va after the same proportion is reduced are compared by the high-speed comparator COM1, the voltage Va is detected to pass through the VOUT moment, the rising edge is extracted by an RC differential unit, the transistor Q11 is turned on and the transistor Q11A is turned off when the rising edge pulse occurs by the RC differential unit, the voltage VREF of the capacitor C11 records 1/4 oscillation period information of the voltage Va, the capacitor C11 is reset at the proper moment of each switching period, the timing circuit comprises a high-speed comparator COM2, a transistor Q12, a capacitor C12 and a constant current source I1 are charged, the voltage of the capacitor C12 is compared with the VREF through the high-speed comparator COM2, the voltage of the capacitor C12 is controlled to be turned on and the capacitor C12 is rapidly turned off when the voltage of the capacitor C12 is more than the high-speed comparator COM 12, and the voltage C12 is rapidly discharged in a process of the high-speed pulse cycle, and the voltage C12 is narrower than the voltage C12 is obtained; after the frequency division by the counter circuit 4, the peak detection pulse of the voltage Va waveform is extracted correctly, and after the peak detection pulse of the voltage Va oscillation waveform is extracted, a clock signal CLK is combined to generate a driving signal for the power tube Q1, so that the switching loss of the Q1 is reduced.
As a further aspect of the invention: different capacitors C1, C2, L1 correspond to different oscillation periods of Va, different oscillation periods corresponding to different voltages VREF.
As a further aspect of the invention: the two input ends of the high-speed comparator COM1 are respectively connected with the voltages VOUT and Va through the same-proportion resistor voltage dividing network.
As a further aspect of the invention: the two input ends of the high-speed comparator COM2 are respectively connected to the capacitor C12 and the voltage VREF.
As a further aspect of the invention: the capacitance values of the capacitors C11 and C12 are equal, the current values of the constant current sources I1 and I2 are equal, the period length of the COM2 output pulse is the same as the charging time of the capacitor C11, namely the COM2 output pulse frequency is 4 times of the oscillation frequency of the voltage Va.
As a further aspect of the invention: the capacitor memory circuit comprises a capacitor C11, a constant current source I2, a transistor Q11A and a transistor Q11B, wherein a grid electrode of the transistor Q11 is connected with the waveform conversion module, a drain electrode of the transistor Q11 is connected with the constant current source I2 and a source electrode of the transistor Q11A, a source electrode of the transistor Q11 is connected with the capacitor C11, a source electrode of the transistor Q11B and a grounding end, a drain electrode of the transistor Q11A is connected with the other end of the capacitor C11 and a drain electrode of the transistor Q11B, and a grid electrode of the transistor Q11B is connected with a reset signal.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the peak detection circuit is used for enabling the drain-source voltage to be the lowest when the main power tube Q1 is turned on, so that the turn-on loss of the Q1 is greatly reduced, and the light load efficiency of the synchronous rectification BUCK circuit working in a DCM mode is further improved.
Drawings
FIG. 1 is a topology circuit diagram of a synchronous rectification BUCK circuit;
fig. 2 is an equivalent circuit diagram of fig. 1 before the freewheel power transistor Q2 is turned off to the main power transistor Q1 is turned on in DCM;
FIG. 3 is a schematic block diagram of generating a main power transistor Q1 driving signal in DCM;
FIG. 4 is a circuit diagram of peak detection;
FIG. 5 is a waveform diagram of important nodes of a synchronous rectification BUCK circuit in DCM mode;
fig. 6 is a waveform diagram of COM2, va and the peak detection signal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1: referring to fig. 1, a control method of a synchronous rectification BUCK circuit in DCM mode is shown in fig. 1, and the synchronous rectification BUCK circuit includes a capacitor C1, a diode D1, a power tube Q1, an inductor L1, a resistor R1, a capacitor Co, a resistor Ro, a capacitor C2, a diode D2 and a power tube Q2, wherein a source electrode of the power tube Q1 is connected with a cathode of the diode D1, the capacitor C1 and a power source vin+, another end of the capacitor C1 is connected with an anode of the diode D1, a drain electrode of the power tube Q1, the inductor L1, the capacitor C2, a cathode of the diode D2 and a drain electrode of the power tube Q2, another end of the inductor L1 is connected with a resistor Ro through the resistor R1, another end of the capacitor C2 is connected with an anode of the diode D2, another end of the capacitor Co, another end of the resistor Ro and the power source VIN-, a gate electrode of the power tube Q1 is connected with a driving signal DRVA, a gate electrode of the power tube Q2 is connected with a driving signal DRVB, a drain voltage of the power tube Q1 is equal to a voltage Ro. If the conditions of the power tube, the DRVA/DRVB driving voltage, the input/output voltage, the load and the like are kept unchanged, the conduction resistance of the power tube is certain, the average current flowing through the power tube is related to the average current of the energy storage inductor and the load current, no matter which control technology is adopted in the low-power output of the BUCK circuit, the conduction loss of the power tube is almost equivalent, and therefore, the key of the improvement of the efficiency is how to reduce the switching loss of the power tube.
When the synchronous rectification BUCK circuit is at low power output, the DCM operation mode is entered. After the main power tube Q1 is turned off, the current of the energy storage inductor L1 starts to decrease, so as to avoid the occurrence of reverse current decreasing efficiency in the freewheeling power tube Q2, and generally turn off Q2 when the current of L1 is 0. At this time, Q1 and Q2 are both in an off state, and the equivalent circuit of fig. 1 is shown in fig. 2 before the main power transistor Q1 is turned on next time. In fig. 1, since the output capacitance Co is larger and the output impedance is smaller, the output capacitance Co can be ideally equivalent to the constant voltage source VOUT in fig. 2, C1 and C2 are drain-source parasitic capacitances of the power transistors Q1 and Q2, and R1 is a parasitic resistance of the energy storage inductance L1. The capacitors C1 and C2 and the inductor L1 resonate, and in an ideal condition, constant amplitude oscillation occurs, but the oscillation amplitude is attenuated due to the presence of R1.
The waveforms of the voltage Va at the point a and the current IL in the energy storage inductor L1 during the period from the turning-off of the freewheeling power tube Q2 to the turning-on of the main power tube Q1 are shown in the time intervals t0-t1 and t2-t5 in fig. 5. The reason why the signal waveforms are different in the time intervals t0-t1, t2-t5 in fig. 5 is that: in DCM mode, the duty ratio of the drive of the BUCK circuit is gradually reduced along with the reduction of the power output, the time from the turn-off of the follow current power tube Q2 to the turn-on of the main power tube Q1 is prolonged, and the signal waveform in the time interval t2-t5 appears when the power output of the BUCK circuit is lower.
In the initial state of the resonant network in fig. 2, the L1 current is 0, the C1 voltage is VIN, and the C2 voltage is 0. Taking t2 in fig. 5 as a time starting point, the voltage at point a can be derived from kirchhoff voltage and current law:
wherein the angular frequency of oscillation
Resonant network quality factor
Vout is the output voltage. Generally, the parasitic resistance of the energy storage inductor and the parasitic capacitance of the power tube are smaller, so that the resonant network has a relatively large quality factor, namely the voltage amplitude oscillation at the point a according to the formula (1) is attenuated slowly.
The charge on the parasitic capacitance C1 of the main power transistor Q1 in fig. 1 is released and generates heat through the Q1 conduction channel at the moment of turn-on. Due to a capacitive loading energy of 0.5 x c x u 2 (C is capacitance and U is capacitance voltage), the energy of the main power on loss can be reduced by square times by reducing the parasitic capacitance voltage. Although the switching frequency and the voltage at the Va point of the synchronous rectification BUCK circuit are both periodically changed, in the DCM mode, the duty ratio of the main power tube Q1 in fig. 1 is changed when different powers are output, so that the voltage at the Va point has uncertainty when the main power tube is turned on, that is, the voltage at the C1 point is uncertain, and then the turn-on loss of Q1 also has randomness. In order to improve the efficiency of the synchronous rectification BUCK circuit under the DCM mode, the switching loss of the main power tube Q1 can be reduced by a method of ensuring the lowest voltage of the C1 when the main power tube Q1 is turned on.
In fig. 3, after the zero-crossing detection circuit detects that the synchronous rectification BUCK circuit works in the DCM mode, the peak detection circuit is started to detect the voltage at the point a. As expressed by equation (1), a plurality of peak detection signals may be detected during the ringing process of the Va point voltage, but only the peak detection signal after the arrival of the clock signal CLK is enabled, and the previous peak detection signal is uniformly discarded. When receiving the effective peak detection signal, the main power tube Q1 is turned on, and the main power tube is turned on at the time shown as time t1 and time t5 in FIG. 5.
As can be seen from equation (1), the Va voltage amplitude oscillates exponentially around the output voltage VOUT, and the time required for each pass of VOUT voltage is equal although the Va amplitude gradually decreases. Based on the basic facts, the enabled wave crest detection circuit is specifically realized as shown in fig. 4 and mainly comprises a sampling and holding circuit, a timing circuit and a counter circuit, wherein the sampling and holding circuit records 1/4 oscillation period information of Va voltage in the form of voltage VREF, and different oscillation periods correspond to different voltages VREF; the timing circuit is controlled by VREF, and the voltage is restored to a pulse signal with the frequency being 4 times that of Va voltage oscillation; and 4 frequency division is carried out by a counter circuit to obtain a wave crest detection signal of the Va voltage. The capacitors C11 and C12 have equal capacitance values, and the constant current sources I1 and I2 have equal current values. The sampling hold circuit comprises a high-speed comparator COM1, an RC differential unit, a waveform conversion and a capacitor memory circuit, wherein the turn-off time of a follow current power tube Q2, namely, the falling edge of a DRVB starts to turn off Q11 and turn on Q11A, a constant current source I2 starts to charge C11, the voltage Va starts to rise at the moment, the voltage Va is compared through the high-speed comparator after the voltage Va is reduced in the same proportion, the voltage Va is detected to pass through the VOUT time, the rising edge is extracted through the RC differential unit, when the rising edge pulse occurs in the RC differential unit, the Q11 is turned on and the Q11A is turned off, the voltage VREF of the C11 records 1/4 oscillation period information of the voltage Va, and the BUCK circuit resets the C11 at the proper time of each switching period. The timing circuit comprises a high-speed comparator COM2, a transistor Q12, a capacitor C12 and a constant current source I1, wherein the voltage of the capacitor C12 is compared with VREF through the high-speed comparator COM2, the COM2 outputs to control the on and off of the Q12, when the voltage of the C12 reaches VREF, the COM2 generates a narrow pulse to turn on the Q12 to discharge the C12, the COM2 outputs are rapidly pulled down to turn off the Q12, and the constant current source I1 charges the C12 again; since the capacitance values of the capacitors C11 and C12 are equal, and the current values of the constant current sources I1 and I2 are equal, the COM2 output pulse period length is the same as the C11 charging time, i.e. the COM2 output pulse frequency is 4 times the Va voltage oscillation frequency. After the counter circuit is divided by 4, the peak detection pulse of the Va voltage waveform can be accurately extracted. Fig. 6 shows waveforms of COM2 output signal, peak detection signal, and Va voltage in fig. 4.
After the peak pulse of the Va voltage oscillation waveform is extracted, a clock signal CLK is combined to generate a driving signal for the main power transistor Q1 in fig. 1, for example, Q1 is turned on at time t1 and time t5 in fig. 5, and at this time, the parasitic capacitance voltage of Q1 is the lowest, that is, the turn-on loss is the smallest, so that the Q1 switching loss is reduced. Therefore, through Va voltage peak detection, the invention realizes the minimization of the turn-on loss of the main power tube, and improves the electric energy conversion efficiency of the synchronous rectification BUCK circuit working in the DCM mode.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (6)
1. The control method for the synchronous rectification BUCK circuit in the DCM mode comprises a capacitor C1, a diode D1, a power tube Q1, an inductor L1, a resistor R1, a capacitor Co, a resistor Ro, a capacitor C2, a diode D2 and a power tube Q2, wherein a source electrode of the power tube Q1 is connected with a cathode of the diode D1, the capacitor C1 and a power supply VIN+, the other end of the capacitor C1 is connected with an anode of the diode D1, a drain electrode of the power tube Q1, the inductor L1, the capacitor C2, a cathode of the diode D2 and a drain electrode of the power tube Q2, the other end of the inductor L1 is connected with a capacitor Co and a resistor Ro through the resistor R1, the other end of the capacitor Co, the other end of the resistor Ro and the power supply VIN-, a grid electrode of the power tube Q1 is connected with a driving signal DRVA, a grid electrode of the power tube Q2 is connected with a driving signal DRVB, a drain voltage of the power tube Q1 is VOUT, the voltage at two ends of the resistor R is VOUT, the control circuit is characterized by further comprising a holding circuit, the holding circuit and a voltage of the holding circuit and the holding circuit is in a voltage of a controlled oscillation cycle, the voltage is reduced in a voltage of the voltage-controlled oscillation circuit is in a form of being equal to a voltage-cycle voltage-controlled to be recorded by VREF, and the voltage-controlled voltage-cycle signal is recorded by the voltage-controlled circuit; after 4 frequency division is carried out by a counter circuit, a peak detection signal of a voltage Va is obtained, the sampling and holding circuit comprises a high-speed comparator COM1, an RC differential unit, a waveform conversion module and a capacitor memory circuit, the turn-off moment of a power tube Q2, namely, the falling edge of a DRVB starts to turn off a transistor Q11 and turn on a transistor Q11A, a constant current source I2 starts to charge a capacitor C11, at the moment, the voltage Va starts to rise, VOUT and Va after the same proportion is reduced are compared by the high-speed comparator COM1, the voltage Va is detected to pass through the VOUT moment, the rising edge is extracted by an RC differential unit, the transistor Q11 is turned on and the transistor Q11A is turned off when the rising edge pulse occurs by the RC differential unit, the voltage VREF of the capacitor C11 records 1/4 oscillation period information of the voltage Va, the capacitor C11 is reset at the proper moment of each switching period, the timing circuit comprises a high-speed comparator COM2, a transistor Q12, a capacitor C12 and a constant current source I1 are charged, the voltage of the capacitor C12 is compared with the VREF through the high-speed comparator COM2, the voltage of the capacitor C12 is controlled to be turned on and the capacitor C12 is rapidly turned off, and the voltage of the capacitor C12 is rapidly reduced to be more than the voltage of the capacitor C12 when the capacitor C12 is turned off, and the high-speed pulse voltage C12 is more than the capacitor C12 is rapidly turned off, and the pulse voltage is high, the pulse voltage is turned off, and the voltage is narrower than the capacitor C12 is subjected to be the high, and the voltage is subjected to the voltage to be the high; after the frequency division by the counter circuit 4, the peak detection pulse of the voltage Va waveform is extracted correctly, and after the peak detection pulse of the voltage Va oscillation waveform is extracted, a clock signal CLK is combined to generate a driving signal for the power tube Q1, so that the switching loss of the power tube Q1 is reduced.
2. The method according to claim 1, wherein different capacitors C1, C2, L1 correspond to different oscillation periods of Va, and different oscillation periods correspond to different voltages VREF.
3. The control method for a synchronous rectification BUCK circuit in DCM according to claim 1, wherein the two input terminals of the high-speed comparator COM1 are connected to voltages VOUT and Va respectively through a same proportional resistor divider network.
4. The control method for synchronous rectification BUCK circuit in DCM according to claim 1, wherein the two input terminals of the high-speed comparator COM2 are respectively connected to a capacitor C12 and a voltage VREF.
5. The control method for the synchronous rectification BUCK circuit in the DCM mode according to claim 1, wherein the capacitance values of the capacitors C11 and C12 are equal, the current values of the constant current sources I1 and I2 are equal, the period length of the COM2 output pulse is the same as the charging time of the capacitor C11, i.e. the COM2 output pulse frequency is 4 times the oscillation frequency of the voltage Va.
6. The control method for the synchronous rectification BUCK circuit in the DCM mode according to claim 1, wherein the capacitor memory circuit includes a capacitor C11, a constant current source I2, a transistor Q11A and a transistor Q11B, a gate of the transistor Q11 is connected to the waveform conversion module, a drain of the transistor Q11 is connected to the constant current source I2 and a source of the transistor Q11A, a source of the transistor Q11 is connected to the capacitor C11, a source of the transistor Q11B and a ground terminal, a drain of the transistor Q11A is connected to the other end of the capacitor C11 and a drain of the transistor Q11B, and a gate of the transistor Q11B is connected to the reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210303303.5A CN114598169B (en) | 2022-03-24 | 2022-03-24 | Control method for synchronous rectification BUCK circuit in DCM mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210303303.5A CN114598169B (en) | 2022-03-24 | 2022-03-24 | Control method for synchronous rectification BUCK circuit in DCM mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114598169A CN114598169A (en) | 2022-06-07 |
| CN114598169B true CN114598169B (en) | 2024-03-08 |
Family
ID=81810998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210303303.5A Active CN114598169B (en) | 2022-03-24 | 2022-03-24 | Control method for synchronous rectification BUCK circuit in DCM mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114598169B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116224057B (en) * | 2023-05-08 | 2023-08-11 | 中国科学院深海科学与工程研究所 | Switching tube switch performance test and loss analysis circuit and test method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997828A (en) * | 2014-05-12 | 2014-08-20 | 上海大学 | Electrolytic-capacitor-free LED driving power source based on Buck circuit |
| CN113346719A (en) * | 2021-06-11 | 2021-09-03 | 电子科技大学 | NMOS power tube floating gate voltage driving circuit in Buck converter |
| CN113809920A (en) * | 2021-08-19 | 2021-12-17 | 广州金升阳科技有限公司 | BUCK converter control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8520413B2 (en) * | 2011-08-17 | 2013-08-27 | Mks Instruments, Inc. | Adjustable resonant buck converter |
| US11271468B2 (en) * | 2018-08-30 | 2022-03-08 | Apple Inc. | High performance synchronous rectification in discontinuous current mode converters |
-
2022
- 2022-03-24 CN CN202210303303.5A patent/CN114598169B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997828A (en) * | 2014-05-12 | 2014-08-20 | 上海大学 | Electrolytic-capacitor-free LED driving power source based on Buck circuit |
| CN113346719A (en) * | 2021-06-11 | 2021-09-03 | 电子科技大学 | NMOS power tube floating gate voltage driving circuit in Buck converter |
| CN113809920A (en) * | 2021-08-19 | 2021-12-17 | 广州金升阳科技有限公司 | BUCK converter control method |
Non-Patent Citations (2)
| Title |
|---|
| 抑制Buck电路同步整流管漏极尖峰的方法;毛昭祺;吕征宇;;电力电子技术;20060225(01);全文 * |
| 过零电流自动切换的同步降压型DC-DC变换器;聂卫东;刘迎迎;韩海青;董怀朋;吴金;于宗光;;微电子学;20131220(06);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114598169A (en) | 2022-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109245569B (en) | Flyback converter and control circuit thereof | |
| CN103248207B (en) | Constant-current and constant-voltage fly-back converter based on primary side feedback | |
| US4720668A (en) | Zero-voltage switching quasi-resonant converters | |
| JPH06225517A (en) | Ac-dc converter | |
| CN111435819B (en) | Step-down hysteresis type switch converter and control method thereof | |
| CN103208934A (en) | Pulse width modulation switching power supply controller and switching power supply | |
| CN101227780A (en) | LED lamp set drive power supply device | |
| CN113162418B (en) | Self-adaptive quasi-resonance detection circuit and method | |
| CN101345481A (en) | Flyback zero voltage soft switch power source | |
| CN110995025A (en) | Switching power supply circuit | |
| CN114598169B (en) | Control method for synchronous rectification BUCK circuit in DCM mode | |
| CN103414323B (en) | Reduce the circuit of service time in current-control type switching regulators | |
| CN115065236B (en) | High-gain Sepic direct-current converter based on three-level boosting unit | |
| WO2023284302A1 (en) | Control method and controller for dc/dc converter | |
| CN114884356A (en) | Flyback converter and power supply system | |
| CN113541486B (en) | Interleaved diode capacitor network high-gain ZVT (zero voltage zero volt) direct current converter and auxiliary circuit | |
| CN102170227B (en) | Self-adaptive power tube adjusting circuit and method | |
| CN108391344B (en) | L ED driving system frequency conversion constant current control method based on switch capacitor converter | |
| CN117277748A (en) | Control device for selecting, switching and locking conduction trough of flyback switching power supply | |
| CN110611430A (en) | Switching power supply control circuit and method and switching power supply system | |
| CN112467989B (en) | Quasi-single-stage high-power-factor alternating current-direct current converter | |
| CN115085550A (en) | Step-down DC converter | |
| CN211266788U (en) | Switching power supply circuit | |
| CN111049387B (en) | TLC II type resonant circuit and power converter applied by same | |
| CN210490731U (en) | High step-up ratio DC conversion device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |