CN110611430A

CN110611430A - Switching power supply control circuit and method and switching power supply system

Info

Publication number: CN110611430A
Application number: CN201910900564.3A
Authority: CN
Inventors: 成东波
Original assignee: BCD Shanghai Micro Electronics Ltd
Current assignee: BCD Shanghai Micro Electronics Ltd
Priority date: 2019-09-23
Filing date: 2019-09-23
Publication date: 2019-12-24
Anticipated expiration: 2039-09-23

Abstract

The invention discloses a switch power supply control circuit and method and a switch power supply system, when a switch power supply has low bus voltage Vbus input, the output voltage Vout of a secondary side of the switch power supply is reduced, under the condition, the switch power supply control circuit of the invention can detect a feedback voltage V for feeding back the output voltage Vout of the secondary side of the switch power supply_FBThe full duty ratio of the waveform is determined, the problem of output power frequency ripple is determined to occur, and the peak voltage Vcs of the switching power supply is raised by K times (K)>1) Simultaneously, the ratio of the secondary side conduction time of the switching power supply to the switching period, Tons/Tsw, is reduced by K times, so that the product of Vcs + Tons/Tsw is kept unchanged, and then the constant current output of the switching power supply is kept; meanwhile, because the Tons/Tsw is reduced, namely the Tons is unchanged, the Tsw is increased, the turn-off time Toff for leading the primary side conduction time Tonp to be eaten is increased, and more space can be provided for the Tonp to adjust when the switching power supply has low bus voltage Vbus input, therebyThe problem of output power frequency ripple is optimized, and the output precision of the switching power supply is improved.

Description

Switching power supply control circuit and method and switching power supply system

Technical Field

The invention relates to the technical field of charging control, in particular to a switching power supply control circuit and method and a switching power supply system.

Background

The power supply is an indispensable component of each electronic device, and the performance of the power supply is directly related to the technical index of the electronic device and whether the electronic device can safely and reliably operate, while the current mainstream application is a Switch Mode power supply (Switch Mode). A switching power supply, also called a switching converter, is a power supply that makes an output voltage or an output current constant by adjusting a conduction ratio or a frequency of a switching device using modern power electronics technology. Compared with the traditional linear power supply, the switching power supply has the characteristics of small volume, good stability and high conversion efficiency, so that the switching power supply is widely applied to occasions such as chargers, power adapters, LED driving power supplies, wireless communication equipment, liquid crystal display power supply management, electronic refrigerators, Ethernet power supplies and the like.

As the switching power supply needs to adapt to different working conditions, the requirements on the dynamic response performance of the switching power supply are higher and higher. For example, when the switching power supply is applied to a charger of an electronic device (e.g., a mobile phone), the stability of the terminal voltage of the charger (i.e., the charged terminal, e.g., the mobile phone terminal) is an important measure of the performance of the charger. Referring to fig. 1, fig. 1 is a schematic diagram of a conventional charger (i.e., a primary side controlled switching power supply). The charger comprises a bridge rectifier circuit U1, a high-voltage filter capacitor C1, a primary winding Lp of a transformer, an auxiliary winding Laux of the transformer, a secondary winding Ls of the transformer, a switching power supply control circuit IC, a power switch tube M1 and the like. The primary winding Lp of the transformer, the auxiliary winding Laux of the transformer and the secondary winding Ls of the transformer form the transformer which is mainly used for electric isolation and energy transmission of input and output. The ac power source Vac generates a bus voltage Vbus through a bridge rectifier circuit U1, and the bus voltage Vbus supplies power to the primary side of the transformer. The grid electrode of the power switch tube M1 is connected with the driving end DRI of the switch power supply control circuit IC, the drain electrode is connected with one end of the primary winding Lp of the transformer, the source electrode is grounded through a series sampling resistor Rcs, and the common end of the source electrode of the power switch tube M1 and the sampling resistor Rcs is connected with the primary peak voltage or peak current sampling end CS end of the switch power supply control circuit IC. The other end of the primary winding Lp of the transformer is connected with the output end of the bridge rectifier circuit U1 to receive the bus voltage Vbus. The same-name end of the auxiliary winding Laux of the transformer is grounded by connecting two feedback resistors Rfb1 and Rfb2 which are connected in series to obtain a feedback voltage V_FBFor realizing the feedback of the secondary output voltage Vout to the switching power supply control circuit IC, in particular, the feedback voltage V because the voltage of the transformer auxiliary winding Laux has a turn ratio relationship with the voltage of the transformer secondary winding Ls_FBTwo feedback currents capable of reflecting the variation of the secondary output voltage VoutThe common end of the resistors Rfb1 and Rfb2 is connected with the FB end of the switching power supply output voltage feedback end of the control circuit IC. One end of the transformer auxiliary winding Laux is further connected with the anode of the diode Daux, the cathode of the diode Daux is connected with the common end of the resistor Rst and the capacitor C2, the resistor Rst and the capacitor C2 form an RC starting circuit, and the common end of the resistor Rst and the capacitor C2 is further connected with the VCC end of the switching power supply control circuit IC, so that the bus voltage Vbus is sampled to obtain the working voltage V required by the switching power supply control circuit IC_CC. One end of the secondary winding Ls of the transformer is connected with the anode of the diode Ds, and the other end of the secondary winding Ls of the transformer is grounded. A capacitor C3, a resistor R0 and a load RL are connected between the cathode of a diode Ds and the ground in parallel, the diode Ds are used for rectifying and stabilizing voltage, and the parallel capacitor C3 and the resistor R0 are used for forming a filter circuit for filtering the output voltage Vout.

In FIG. 2 is shown V_FBThe time-dependent curve, as can be seen from fig. 2, a switching period T of M1 during normal operation of the charger is actually divided into three phases: in the primary side conduction stage Tonp (Tonp is primary side conduction time), the secondary side conduction stage Tons (Tons is secondary side conduction time) and the primary side and secondary side both-off stage Toff (Toff is off time), referring to fig. 1, the primary side winding Lp stores energy in the primary side conduction stage Tonp, the energy stored in the primary side winding Lp is transmitted to the secondary side circuit in the secondary side conduction stage Tons, and the secondary side current gradually decreases to 0.

However, because the capacity of the input bus capacitor of the charger manufacturer tends to be smaller and smaller at present, and a switching power supply control circuit IC of a PSR (primary feedback) architecture generally adopts a DCM (discontinuous mode) working mode, the problem of output power frequency ripple (ripple) is caused under full load when low bus voltage is input, and the performance requirement of the product may not be met. Moreover, the output power frequency ripple problem exists in the switching power supply control circuit of the AC/DC full-series PFM (pulse frequency modulation) architecture, and the essential reasons are as follows: the constant current is realized by respectively fixing the peak voltage Vcs and the ratio Tons/Tsw (also called as the secondary side on-time duty ratio, wherein Tsw is Tonp + Tons + Toff), and obtaining a formula of the constant currentAnd Vbus Tonp ═ Lp ═ Vcs/Rcs, where Lp is the inductance of the primary winding of the transformer. When the low bus voltage is input and the load is full, the Vbus voltage can be changed with the frequency of the mains supply by taking 10ms as a cycle, when the Vbus is reduced to the bottom of a valley, Lp, Vcs and Rcs are not changed, and the Tonp is increased, so that the Toff time can be squeezed out, when the Toff time is reduced to 0, the Vbus is continuously reduced, and the Tonp is continuously increased, the output power is limited, therefore, under the condition that the output current is not changed, the output voltage Vout is reduced, and the power supply performance shows that the output power frequency ripple is increased, and even exceeds the specification when the output power frequency ripple is serious.

Therefore, how to improve the switching power supply control circuit and method and the switching power supply system design to reduce the output power frequency ripple of the switching power supply and improve the output accuracy is a problem that needs to be solved by those skilled in the art at present.

Disclosure of Invention

The invention aims to provide a switching power supply control circuit and method and a switching power supply system, which can reduce output power frequency ripples of a switching power supply and improve output precision.

In order to achieve the above object, the present invention provides a switching power supply control circuit, including:

the FB waveform detection circuit is used for feeding back the output voltage of the secondary side of the switching power supply in real time to obtain an FB waveform, and when the FB waveform is detected to be in a full duty ratio state, a QR mode trigger signal is generated to enable the switching power supply to enter a QR mode;

the mode switching circuit is connected with the FB waveform detection circuit and used for receiving the QR mode trigger signal, and when the QR mode trigger signal is effective, the primary peak voltage Vcs of the switching power supply is raised to K × Vcs, and meanwhile, the ratio Tons/Tsw of the secondary side conduction time Tons and the switching period Tsw of the switching power supply is reduced to Tons/K × Tsw, wherein K is greater than 1;

the constant current control circuit is connected with the mode switching circuit and is used for generating a constant current control logic signal according to the peak voltage and the ratio Tons/Tsw output by the mode switching circuit; and the number of the first and second groups,

and the driving circuit is connected with the constant current control circuit and the power switch tube of the switching power supply and is used for outputting a driving signal according to the constant current control logic signal so as to control the on-off of the power switch tube of the switching power supply.

Optionally, the FB waveform detection circuit determines that the FB waveform is in a full duty cycle state when it is detected that off-time Toff of the switching power supply occurring within a plurality of consecutive switching periods Tsw is smaller than a first set threshold under the condition that a current primary peak voltage Vcs of the switching power supply can reach a highest primary peak voltage value Vcs _ H.

Optionally, the FB waveform detection circuit generates a non-QR mode trigger signal to cause the switching power supply to exit the QR mode when a bus voltage of the switching power supply is increased or a load is reduced and when it is detected that the off-time Toff is greater than a second set threshold value for a plurality of consecutive switching periods Tsw.

Optionally, the FB waveform detection circuit includes:

the first enabling signal generating module is used for receiving an initialization signal and generating a first enabling signal according to a delay signal corresponding to the primary side conduction time Tonp of the switching power supply and a delay signal corresponding to the turn-off time Toff of the switching power supply;

the first clock signal generation module is used for receiving an initialization signal and generating a first clock signal according to the primary side peak voltage of the switching power supply and the primary side conduction time Tonp of the switching power supply;

the first counting module is used for continuously counting the rising edges of the first clock signal under the control of the first enabling signal so as to detect that the FB waveform has a full duty ratio state;

the first pulse generator is used for generating a first pulse signal according to the continuous counting result of the first counting module;

the second enabling signal generating module is used for receiving the initialization signal and generating a second enabling signal according to another delay signal corresponding to the turn-off time Toff of the switching power supply and the sampling time of the switching power supply;

the second clock signal generating module is used for receiving the initialization signal and generating a second clock signal according to the primary side conduction time Tonp of the switching power supply;

the second counting module is used for continuously counting the rising edge of the second clock signal under the control of a second enabling signal so as to detect the condition that the bus voltage of the switching power supply is increased or the load is lightened;

the second pulse generator is used for generating a second pulse signal according to the continuous counting result of the second counting module; and the number of the first and second groups,

and the QR mode triggering module is used for generating a QR mode triggering signal or a non-QR mode triggering signal according to the first pulse signal and the second pulse signal.

Optionally, the mode switching circuit includes a peak voltage switching circuit and a secondary on-time duty cycle switching circuit; the peak voltage switching circuit comprises a first switch, a second switch and a comparator, wherein the input end of the first switch is connected with a primary peak voltage signal Vcs, the control end of the first switch is connected with the non-QR mode trigger signal so that the first switch is conducted when the non-QR mode trigger signal is effective, the input end of the second switch is connected with a K-time peak voltage signal K x Vcs, the control end of the second switch is connected with the QR mode trigger signal so that the second switch is conducted when the QR mode trigger signal is effective, the output ends of the first switch and the second switch are both connected with the inverting input end of the comparator, the non-inverting input end of the comparator is connected with the peak voltage signal, and the output end of the comparator is connected with the input end of the constant current control circuit; the secondary side conduction time duty ratio switching circuit comprises a third switch and a fourth switch, an input end of the third switch is connected with a ratio signal Tons/Tsw (namely, a secondary side conduction time duty ratio), a control end of the third switch is connected with the non-QR mode trigger signal so that the third switch is conducted when the non-QR mode trigger signal is effective, an input end of the fourth switch is connected with a ratio signal Tons/K Tsw which is 1/K times of the ratio signal, a control end of the fourth switch is connected with the QR mode trigger signal so that the fourth switch is conducted when the QR mode trigger signal is effective, and output ends of the third switch and the fourth switch are connected with an input end of the constant current control circuit.

Optionally, the FB waveform detection circuit generates the QR mode trigger signal when detecting that the off-time Toff of the switching power supply occurring within a plurality of consecutive switching periods Tsw is less than a first set threshold under the condition that the current peak voltage Vcs of the switching power supply can reach the highest peak voltage value Vcs _ H; when the condition that the bus voltage of the switching power supply is increased or the load is lightened occurs, the non-QR mode trigger signal is generated when the condition that the turn-off time Toff is larger than a second set threshold value in a plurality of continuous switching periods Tsw is detected.

Based on the same inventive concept, the invention also provides a switching power supply system, which comprises the switching power supply control circuit and a power switch tube, wherein the power switch tube is connected with a driving circuit of the switching power supply control circuit.

Optionally, the switching power supply system further includes:

the input rectification filter circuit is used for converting the alternating voltage signal into a bus voltage signal;

the transformer is provided with a primary winding, a secondary winding and an auxiliary winding which are coupled with the input rectifying and filtering circuit, and a driving circuit in the switching power supply control circuit is coupled to the primary winding;

the output rectifying and filtering circuit is electrically connected with the secondary winding and is used for rectifying and filtering the output signal of the secondary winding;

the output voltage feedback circuit is connected between the auxiliary winding and the FB waveform detection circuit of the switching power supply control circuit and is used for sampling and feeding back the output voltage of the auxiliary winding; and the number of the first and second groups,

and the peak voltage sampling resistor is connected between the power switch tube and the ground, and the connection node of the peak voltage sampling resistor and the power switch tube is connected with the mode switching circuit of the switching power supply control circuit.

Based on the same inventive concept, the invention also provides a switching power supply control method, which comprises the following steps:

feeding back the output voltage of a secondary side of a switching power supply in real time to obtain an FB waveform, and generating a QR mode trigger signal when detecting that the FB waveform has a full duty ratio state so as to enable the switching power supply to enter a QR mode;

when the QR mode trigger signal is effective, raising the primary peak voltage Vcs of the switching power supply to K × Vcs, and simultaneously reducing the ratio (Tons/Tsw) of the secondary side conduction time (Tons) of the switching power supply and the switching period (Tsw) to (Tons/K × Tsw); and the number of the first and second groups,

and generating a constant current control logic signal according to the adjusted peak voltage and the ratio Tons/Tsw, and outputting a driving signal according to the constant current control logic signal to control the on-off of a power switch tube of the switching power supply.

Optionally, the step of the switching power supply entering the QR mode includes: under the condition that the peak voltage Vcs of the switching power supply can reach the highest peak voltage Vcs _ H, when the fact that the turn-off time Toff of the switching power supply in a plurality of continuous switching periods Tsw is smaller than a first set threshold value is detected, the FB waveform is judged to be in a full duty ratio state, a QR mode trigger signal is generated, and the switching power supply enters a QR mode according to the QR mode trigger signal; and the number of the first and second groups,

the step of the switching power supply exiting the QR mode includes: when the condition that the bus voltage of the switching power supply is increased or the load is lightened occurs, and when the condition that the turn-off time Toff is larger than a second set threshold value in a plurality of continuous switching periods Tsw is detected, generating a non-QR mode trigger signal, and exiting the QR mode by the switching power supply according to the non-QR mode trigger signal.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the case where the output voltage Vout of the secondary side of the switching power supply falls when the switching power supply has a low bus voltage Vbus input, the switching power supply control circuit of the present invention can detect that the secondary side is used for feeding back the switching power supplyOutput voltage Vout of the feedback voltage V_FBThe waveform has a full duty ratio, and the problem of output power frequency ripple is judged to occur, so that the peak voltage Vcs of the switching power supply is raised by K times (K is 1.1 or other numerical values), and meanwhile, the ratio Tons/Tsw of the secondary side conduction time of the switching power supply to the switching period is reduced by K times, so that the product of Vcs and Tons/Tsw is kept unchanged, and then the constant current output of the switching power supply is kept; meanwhile, because the Tons/Tsw is reduced, namely the Tons is unchanged, the Tsw is increased, the turn-off time Toff for the primary side conducting time Tonp to be eaten is increased, and more space can be provided for the Tonp to be adjusted when the switching power supply has low bus voltage Vbus input, so that the problem of output power frequency ripple is optimized, and the output precision of the switching power supply is improved. The technical scheme of the invention can be applied to respective switch power supply systems, such as a charger, a power adapter, an LED driving power supply, wireless communication equipment, liquid crystal display power supply management, an electronic refrigerator or an Ethernet power supply and the like, so as to enhance the dynamic response performance of the switch power supply systems.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a system schematic diagram of a conventional charger.

FIG. 2 is a feedback value V of the output voltage of the charger system shown in FIG. 1_FBTime profile.

Fig. 3 is a circuit schematic diagram of a switching power supply control circuit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a switching power supply system according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of an FB waveform detection circuit according to an embodiment of the present invention.

Fig. 6 is a timing diagram of the input signals and the switching power supply required by the FB waveform detection circuit according to the embodiment of the present invention.

Fig. 7 is a timing diagram of the input signal, each intermediate output signal, the QR trigger signal, and the feedback value of the output voltage of the switching power supply of the FB waveform detection circuit according to the embodiment of the present invention.

Fig. 8A is a schematic diagram of a peak voltage switching circuit in accordance with an embodiment of the present invention.

Fig. 8B is a schematic diagram of a secondary-side on-time duty cycle switching circuit according to an embodiment of the present invention.

Fig. 9 is a graph comparing the effect of output power frequency ripple between an embodiment of the present invention and the prior art.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be noted that, in this document, "the peak voltage Vcs of the switching power supply is raised by K times" means "the peak voltage Vcs of the switching power supply is amplified to K × Vcs before" and "the ratio Tons/Tsw is reduced by K times" means "the ratio Tons/Tsw is reduced to K times before, that is, reduced to Tons/K × Tsw". In addition, in this document, the low bus voltage refers to a bus voltage smaller than 80V, which is output after 220V rectification and filtration of the ac mains supply, the low bus voltage can be as low as about 70V, output power frequency ripple can be caused by low bus voltage input, and the problem of output power frequency ripple generally does not occur when the bus voltage is above 80V. The core of the technical scheme of the invention is to solve the problem of output power frequency ripple caused by the fact that the switching power supply has low bus voltage input.

Referring to fig. 3 and 4, the present invention provides a switching power supply control circuit 10 for reducing the problem of output power frequency ripple caused by the switching power supply having a low bus voltage Vbus input, where the switching power supply control circuit 10 includes: an FB waveform detection circuit 101, a mode switching circuit 102, a constant current control circuit 103, and a drive circuit 104. The switching power supply control circuit is provided with a power supply end VCC, a switching power supply output voltage feedback end FB, a primary side peak voltage or peak current sampling end CS and a driving end DRI. The switching power supply control circuit can be a controller chip and can be connected into a switching power supply system under primary side feedback control so as to sample primary side peak voltage Vcs and peak current Ipk of the switching power supply system and drive a power switching tube of the switching power supply system to work, and further control the secondary side output voltage Vout of the switching power supply system.

Referring to fig. 3 to fig. 5, the FB waveform detecting circuit 101 is connected to the output voltage feedback terminal FB, and the output terminal thereof is connected to the input terminal of the mode switching circuit 102. The FB waveform detection circuit 101 is used for feeding back the output voltage Vout of the secondary side of the switching power supply in real time to obtain an FB waveform V_FB(i.e. the feedback voltage V of the output voltage Vout_FBAnd upon detection of the FB waveform V), and the FB waveform V_FBAnd when the full duty ratio state occurs, a QR mode trigger signal is generated, so that the switching power supply enters a QR mode. When the switching power supply has a low bus voltage Vbus input, the output voltage Vout will drop under the condition of constant output current, and the feedback voltage V of the output voltage Vout_FBWill also drop correspondingly when the feedback voltage V_FBWhen the corresponding FB waveform appears in the full duty cycle state, the secondary on-time Tons of the switching power supply ends, and the next primary on-time Tonp is turned on immediately or after a very short time, so that there is substantially no Toff time within one complete switching period Tsw of the switching power supply, and thus, the FB waveform V is used for detecting the FB waveform V_FBThere are various design methods of the FB waveform detection circuit 101 in which the full duty state occurs, for example, the FB waveform detection circuit 101 is designed such that: when the magnitude relation between the sum of Tonp and Tons and the switching period Tsw is detected to be equal or nearly equal, the FB waveform is determined to be in a full duty cycle state. For another example, in the present embodiment, the FB waveform detection circuit 101 is designed to: the peak voltage of the current primary side of the switching power supply can reach the highest primary sideUnder the condition of a peak voltage value Vcs _ H (i.e., Vcs — H), when it is detected that the off-time Toff of the switching power supply in a plurality of consecutive switching cycles Tsw (e.g., 4 consecutive cycles) is smaller than a first set threshold (e.g., 1 μ s), it is determined that the full duty state of the FB waveform occurs, i.e., it is determined that the switching power supply has an output power frequency ripple problem, at this time, a QR mode trigger signal QR _ mode is generated to trigger the switching power supply to enter a QR mode (i.e., a quasi-resonant mode), and the switching power supply can enter the QR mode according to the QR mode trigger signal QR _ mode, and after the QR mode occurs, the QR mode signal QR _ mode is changed from 0 to 1, i.e., the QR mode signal is active when it is at a high level 1.

Specifically, referring to fig. 5, the FB waveform detecting circuit 101 of the present embodiment includes a first enable signal generating module 101a, a first clock signal generating module 101b, a first counting module 101c, a first pulse generator P1, a second enable signal generating module 101d, a second clock signal generating module 101e, a second counting module 101f, a first pulse generator P2, and a QR mode triggering module 101 g. The first Enable signal generating module 101a is configured to receive an initialization signal Init _ HL for initialization, and generate a first Enable signal Enable according to a delay signal (defined as the second signal PDON _ LEB) corresponding to a primary on-time Tonp of the switching power supply and a delay signal (defined as the first signal Toff _1 μ sLH) corresponding to an off-time Toff of the switching power supply. The first clock signal generation module 101b is configured to receive an initialization signal Init _ HL for initialization, and generate a first clock signal Clk1 according to a primary side peak voltage Vcs of the switching power supply and a primary side on-time Tonp of the switching power supply. The first counting module 101c is configured to continuously count rising edges of the first clock signal Clk1 (in this embodiment, rising edges of Clk1 are counted) under the control of the first Enable signal Enable to detect that the FB waveform has the full duty cycle state. The first pulse generator P1 is used for generating a first pulse signal ON _ QR _ pulse according to the result of the continuous counting of the first counting module number Clk 1. The second enable signal generating module 101d is configured to receive the initialization signal Init _ HL for initialization, and generate another delay signal (defined as a fifth signal Toff) according to the off time Toff of the switching power supply_4μ sLH) and V of the switching power supply_FBSample time (in this embodiment, one and the V are defined)_FBThe sampling time-dependent sixth signal SH) generates the second Enable signal Enable _4 μ s. The second clock signal generating module 101e is configured to receive the initialization signal Init _ HL for initialization, and generate the second clock signal Clk2 according to the primary side on-time Tonp of the switching power supply. The second counting module 101f is configured to count the rising edges of the second clock signal Clk2 continuously under the control of the second Enable signal Enable _4 μ s to detect the occurrence of the bus voltage Vbus rising or the load lightening of the switching power supply. The second pulse generator P2 is configured to generate a second pulse signal OFF _ QR _ pulse according to the result of the continuous counting of the second counting module 101 f. The QR mode trigger module 101g is configured to generate a QR mode trigger signal QR _ mode or a non-QR mode trigger signal QR _ mode _ N according to the first pulse signal ON _ QR _ pulse and the second pulse signal OFF _ QR _ pulse.

The first enable signal generating block 101a may include an RS flip-flop and a logic gate connected thereto, and the RS flip-flop in the first enable signal generating block 101a may be formed by cross-connecting input terminals and output terminals of the first Nor gate Nor1 and the second Nor gate Nor 2. The first counting module 101c is composed of cascaded first to third flip-flops TFF1 to TFF3, And the first clock signal generating module 101b includes an And gate And. The second enable signal generation block 101d may include another RS flip-flop and a logic gate connected thereto, and the RS flip-flop in the second enable signal generation block 101d may be formed by cross-connecting input terminals and output terminals of the fourth Nor gate Nor4 and the fifth Nor gate Nor 5. The second counting module 101f is composed of cascaded fourth to sixth flip-flops TFF4 to TFF 6. The second clock signal generation block 101e includes an inverter inv. The QR mode trigger module 101g may include still another RS flip-flop, and the RS flip-flops in the QR mode trigger module 101g may be formed by cross-connecting input and output terminals of the eighth Nor gate Nor8 and the ninth Nor gate Nor 9. In addition, the output end of the RS flip-flop of the first enable signal generating module 101a is connected to the third Nor gate 3 as the logic gate to which the RS flip-flop is connected, and the output end of the RS flip-flop of the second enable signal generating module 101d is sequentially connected to the sixth Nor gateThe gate Nor6 and the seventh Nor gate Nor7 serve as logic gates to which the RS flip-flop is connected. That is, the FB waveform detection circuit 101 of the present embodiment includes first to ninth Nor gates Nor1 to Nor9, an And gate ad, an inverter inv, first to sixth flip-flops TFF1 to TFF6, And first to second pulse generators P1 to P2. The specific circuit connection relationship is as follows: an input terminal of the first Nor gate Nor1 receives a first signal Toff _1 μ sLH, another input terminal of the first Nor gate Nor1 is connected to an output terminal of the second Nor gate Nor2 and an input terminal of a third Nor gate Nor3, and an output terminal of the first Nor gate Nor1 is connected to a first input terminal of the second Nor gate Nor 2; a third input end of the second Nor gate Nor2 is connected to a second signal PDON _ LEB; the output end of the third Nor gate Nor3 is connected to the asynchronous reset terminal preset of the first to third flip-flops TFF1 to TFF3 to transmit the first Enable signal Enable to the first to third flip-flops TFF1 to TFF3 so as to Enable the first to third flip-flops TFF1 to TFF3, one input end of the And gate ad is connected to the third signal PD _ ON, the other input end of the And gate ad is connected to the fourth signal Ipk _ high, And the output end of the And gate ad outputs the first clock signal Clk 1; the first to third flip-flops TFF1 to TFF3 are connected in series in sequence, i.e. the non-inverting output Q of the first flip-flop TFF1 is connected to the clock terminal Clk of the second flip-flop TFF2 to provide the signal Q1 to the second flip-flop TFF2, the non-inverting output Q of the second flip-flop TFF2 is connected to the clock terminal Clk of the third flip-flop TFF3 to provide the signal Q2 to the third flip-flop TFF3, And wherein the clock terminal Clk of the first flip-flop TFF1 is connected to the output of the And gate And to receive the first clock signal Clk1, the inverting output Qb of the third flip-flop TFF3 is connected to the input of the first pulse generator P1 to provide the signal Q3N to the first pulse generator P1, the output of the first pulse generator P1 is connected to an input of the eighth Nor gate 8 to provide the eighth Nor gate signal QR 4642, the ninth Nor gate 9 to the ninth Nor gate 8, an output terminal of the eighth Nor gate Nor8 is connected to a first input terminal of the ninth Nor gate Nor9, an input terminal of the fourth Nor gate Nor4 receives a fifth signal Toff _4 μ sLH, and another input terminal of the fourth Nor gate Nor4The input end of the fourth NOR gate Nor4 is connected with the output end of the fifth NOR gate Nor5 and an input end of the sixth NOR gate Nor6, and the output end of the fourth NOR gate Nor4 is connected with the first input end of the fifth NOR gate Nor 5; a third input terminal of the fifth Nor gate Nor5 receives a sixth signal SH; an output end of the fifth Nor gate Nor5 is connected with an input end of a sixth Nor gate Nor6, another input end of the sixth Nor gate Nor6 is connected with a seventh signal PDON _ reset _ N, an output end of the sixth Nor gate Nor6 is connected with an input end of the seventh Nor gate Nor7, an output end of the seventh Nor gate Nor7 is connected with an asynchronous reset terminal preset of the fourth to sixth flip-flops TFF4 to TFF6 to supply a second Enable signal Enable _4 μ s to the fourth to sixth flip-flops TFF4 to TFF6 to further Enable the fourth to sixth flip-flops TFF4 to TFF6, an input end of the inverter inv is connected with the third signal PD _ ON, an output end of the inverter inv outputs a second clock signal cik 2, fourth to sixth flip-flops TFF4 to TFF6, a fourth to sixth flip-flop TFF6 are connected in series, that is connected with an output end of the fifth flip-flop TFF 46q 4, a fifth flip-flop TFF 46q signal TFF4 is connected in series to the fifth flip-flop TFF 46q 4, to provide the signal Q2A to the sixth flip-flop TFF3, and wherein the clock terminal clk of the fourth flip-flop TFF4 is connected to the output of the inverter inv, the inverting output Qb of the sixth flip-flop TFF6 is connected to the input of the second pulse generator P2 to provide the signal Q3AN to the second pulse generator P2, the second input of the second Nor gate Nor2 and the further input of the third Nor gate Nor3, the second input of the fifth Nor gate Nor5 and the further input of the seventh Nor gate Nor7 are each connected to the initialization signal Init _ HL for initializing the FB waveform detection circuit, the output of the second pulse generator P2 is connected to the third input of the ninth Nor gate Nor9 to provide the second pulse signal OFF _ QR _ pulse to the ninth Nor gate Nor9, the further input of the eighth Nor gate 8 is connected to the ninth Nor gate Nor input 9 6, the further input of the ninth Nor gate is 8, an output terminal of the ninth Nor gate Nor9 outputs the QR mode trigger signal QR _ mode. Please refer to fig. 6, wherein the first signalToff _1 μ sLH is a signal delayed (for example, delayed by 1 μ s) from the start time of the off-time Toff of the switching power supply, and specifically, for example, is a signal that is high (i.e., the pulse width of the signal is Toff minus the first time threshold) from the time when the switching power supply enters the off-phase to the time when the switching power supply is greater than a set first time threshold (for example, 1 μ s) to the end of the off-phase, the third signal PD _ ON is equal to the primary ON-time Tonp of the switching power supply, the second signal PDON _ LEB is a signal obtained by delaying the primary ON-time Tonp by a predetermined time (for example, 500ns), the fourth signal Ipk _ high is a signal that is high when the primary peak voltage Vcs of the switching power supply can reach the highest primary peak voltage value Vcs _ H (which can also be directly represented by the highest peak current Ipk), and the fifth signal Toff _4 μ sLH is another signal delayed (for example) from the start time when the off-time Toff of the switching power supply is reached E.g. 4 mus), specifically for example, a signal that is high in a period from a time when the switching power supply enters the off-phase to a time when the off-phase is ended to a time when the time is greater than a set second time threshold (e.g. 4 mus) (i.e. the pulse width of the signal is Toff minus the second time threshold), and the sixth signal SH is a signal that is related to the V of the switching power supply_FBA signal related to the sampling time, for example, a signal that is high for a period of time at the end of the sampling time (i.e., a periodic pulse signal that can identify the length of the sampling period), and has a pulse width of, for example, 0.25 μ s to 0.5 μ s; the seventh signal PDON _ reset _ N is a signal that is low during a time period (i.e., 500ns in the figure) in which the second signal PDON _ LEB is delayed with respect to the third signal PD _ ON (i.e., a periodic pulse signal that can identify a length of the time period in which the second signal PDON _ LEB is delayed with respect to the third signal PD _ ON). Referring to fig. 7, fig. 7 shows timing charts of signals VFB, K × Vcs _ H, Vcs _ H, Vcs, Ipk _ high, PD _ ON, PDON _ LEB, Toff _1 μ sllh, Enable, Q1 to Q3, Q3N, ON _ QR _ pulse, SH, Toff _4 μ sLH, PDON _ reset _ N, Enable _4 μ s, Clk2, Q1A, Q2A, Q3A, Q3AN, OFF _ QR _ pulse, and QR mode trigger signal QR _ mode in the FB waveform detection circuit 101, where Q1 to Q3 are signals output from in-phase output terminals Q of the first to third flip-flops TFF1 to TFF3, respectively, Q1A, Q2A, and Q3A are signals output from the in-phase output terminals Q1A, Q2A, and Q3A, respectivelyAre signals output by the non-inverting output terminals Q of the fourth to sixth flip-flops TFF4 to TFF 6. As can be seen from fig. 7, when the QR mode is entered, the Vcs signal changes to K × Vcs, and the pulse peak changes from Vcs _ H to K × Vcs _ H.

As shown in fig. 5 to 7, the FB waveform detection circuit 101 is further configured to generate a non-QR mode trigger signal QR _ mode _ N when it detects that the off-time Toff greater than a second set threshold (e.g., 4 μ s) occurs within a plurality of consecutive switching periods Tsw when the bus voltage Vbus of the switching power supply is increased or the load is reduced (at this time, the Toff time is increased), so as to enable the switching power supply to exit the QR mode. The QR _ mode _ N signal is the negation of the QR _ mode signal and is active high 1. The first set threshold and the second set threshold are different, return difference setting is achieved, and therefore the switching power supply system can be prevented from being switched back and forth between the QR mode and the non-QR mode under a certain load state.

It should be noted that, in other embodiments of the present invention, the FB waveform detection circuit 101 may also adopt other circuit design manners to implement that the switching power supply enters the QR mode and exits the QR mode, and the technical solution of the present invention is not limited to the circuit design shown in fig. 5.

An input end of the mode switching circuit 102 is connected to an output end of the FB waveform detection circuit 101, and is configured to receive the QR mode trigger signal QR _ mode and the non-QR mode trigger signal QR _ mode _ N, and when the QR mode trigger signal QR _ mode is active (QR _ mode is a high level), raise a primary peak voltage Vcs of the switching power supply by K times, and reduce a ratio Tons/Tsw of a secondary side on-time Tons of the switching power supply to a switching period Tsw by K times, where K >1, that is, a duty ratio of the secondary side on-time is reduced from Tons/Tsw to tsns/K × w; when a non-QR mode trigger signal QR _ mode _ N is effective, a primary side peak voltage K multiplied by K of the switching power supply is converted back to Vcs, and meanwhile, the ratio of the secondary side conduction time Tons reduced by K times of the switching power supply to the switching period Tsw, namely, the duty ratio of the secondary side conduction time, is converted back to the Tons/Tsw from the Tons/K Tsw, so that the switching power supply exits the QR mode and enters a conventional constant-current control mode.

Referring to fig. 8A and 8B, the mode switching circuit 102 of the present embodiment includes a peak voltage switching circuit 1021 and a secondary on-time duty ratio switching circuit 1022. Referring to fig. 8A, the peak voltage switching circuit 1021 is configured to switch a primary peak voltage Vcs of the switching power supply according to whether a QR mode trigger signal QR _ mode is active, and specifically, the peak voltage switching circuit 1021 includes a first switch S1, a second switch S2, and a comparator P3, an input terminal of the first switch S1 is connected to the primary peak voltage signal Vcs, a control terminal of the first switch S1 is connected to the non-QR mode trigger signal QR _ N so that the first switch is turned on when the non-QR mode trigger signal QR _ mode _ N is active (i.e., QR _ mode _ N is 1), an input terminal of the second switch S2 is connected to K times the peak voltage signal K × Vcs, and a control terminal of the second switch S2 is connected to the QR mode trigger signal QR _ mode so that the second switch is turned on when the QR mode trigger signal QR _ mode _ N is active (i.e., QR _ mode — N is 1), the output ends of the first switch S1 and the second switch S2 are both connected to the inverting input end of the comparator P3, the non-inverting input end + of the comparator P3 is connected to the peak voltage signal Vcs, and the output end of the comparator P3 is connected to the input end of the constant current control circuit 103. Referring to fig. 8B, the secondary on-time duty ratio switching circuit 1022 is configured to switch a ratio Tons/Tsw of the switching power source (i.e., a secondary on-time duty ratio) according to whether a QR mode trigger signal QR _ mode is active, and specifically, the secondary on-time duty ratio switching circuit 1022 includes a third switch S3 and a fourth switch S4, an input terminal of the third switch S3 is connected to the ratio signal Tons/Tsw, a control terminal of the third switch S3 is connected to the non-QR mode trigger signal QR _ mode _ N to make the third switch conduct when the non-QR mode trigger signal QR _ mode _ N is active (i.e., QR _ mode _ N is 1), an input terminal of the fourth switch S4 is connected to the ratio signal Tons/K Tsw 1/K times (i.e., the secondary on-time duty ratio reduced by K times), and a control terminal of the fourth switch S4 is connected to the QR mode trigger signal QR mode _ mode to make the fourth switch S4 trigger the QR mode at the QR mode trigger mode When the signal QR _ mode is active (i.e., QR _ mode ═ 1), the outputs of the third switch S3 and the fourth switch S4 are connected to the input of the constant current control circuit 103.

The constant current control circuit 103 is connected to the mode switching circuit 102, and the constant current control circuit 103 is configured to generate a constant current control logic signal according to a peak voltage Vcs and a ratio Tons/Tsw currently output by the mode switching circuit 102. The driving circuit 104 is connected to the constant current control circuit 103 and the power switch tube M1 of the switching power supply, and the driving circuit 104 is configured to output a driving signal according to the constant current control logic signal to control on/off of the power switch tube M1 of the switching power supply, so that an output current Iout of the switching power supply is constant.

Due to the formula for realizing constant current output of the switching power supplyNp/Ns is the turn ratio of the transformer of the switching power supply, Np is the number of turns of the primary winding of the transformer, Ns is the number of turns of the secondary winding of the transformer, and when the ton/Tsw is limited due to the input of the low bus voltage Vbus of the switching power supply, the output voltage Vout of the secondary side drops, and the problem of output power frequency ripple can occur. Therefore, the technical solution of the present invention provides an output power frequency ripple detection mechanism and a mode switching mechanism, that is, when the output power frequency ripple problem occurs, the pulse of the switching power supply system is output in a full duty cycle manner, and the FB waveform detection circuit 101 detects the state (at this time, the feedback voltage V for feeding back the output voltage Vout condition of the secondary side of the switching power supply is detected)_FBThe waveform is present at the full occupation ratio), and in this state, a QR mode trigger signal QR _ mode is generated to control the next action, that is, when the FB waveform detection circuit 101 detects this state, the mode switching circuit 102 uses the QR mode trigger signal QR _ mode to raise Vcs by K times (K is 1.1 or another value), and at the same time, reduces the secondary on-time duty ratio Tons/Tsw by K times, which has the advantages: on one hand, the product of Vcs Tons/Tsw can be kept unchanged, namely the constant current value Iout is kept unchanged; secondly, because the Tons/Tsw is reduced, namely the Tons is unchanged, the Tsw is increased, the Toff available for the Tonp to eat is increased, more space can be provided for the Tonp to adjust when the low bus voltage Vbus is input, and the output power frequency line is optimizedThe wave problem. Referring to fig. 9, fig. 9 illustrates the problem of output power frequency ripple under the prior art and the scheme of the present invention, because the principle of implementing constant current output in the prior art is to fix Vcs, Tons/Tsw, and Vbus Tonp ═ Lp Vcs/Rcs, when Vbus decreases, Lp, Vcs, and Rcs do not change, Tonp will increase, Toff time will be squeezed out, when Toff time decreases to 0, Vbus will continue to decrease, and when Tonp continues to increase, output power will be limited, that is, Tons/Tsw is limited, and then the problem of output power frequency ripple that may exceed specification requirements, that is, the difference H1 between the highest point and the lowest point of output power frequency ripple is large, will occur; in the invention, Vcs is raised by K times, and Tons/Tsw is reduced by K times, so that the product of Vcs x Tons/Tsw can be kept unchanged, namely, the constant-current output value Iout is kept unchanged, and because Tons/Tsw is reduced, namely, Tons is unchanged, Tsw is increased, Tonp 'eaten' Toff is increased, more space can be provided for Tonp to adjust when Vbus is lower, so that the problem of output power frequency ripple is optimized, namely, the difference H2 between the highest point and the lowest point of the output power frequency ripple is smaller (H2)<H1)。

In summary, when the switching power supply has a low bus voltage Vbus input, the output voltage Vout of the switching power supply drops, and in this case, the switching power supply control circuit of the present invention can detect the feedback voltage V for feeding back the output voltage Vout of the secondary side of the switching power supply_FBWhen the waveform has a full duty ratio, the problem of output power frequency ripple is judged to occur, the peak voltage Vcs of the switching power supply is raised by K times (K is 1.1 or other numerical values), and the ratio Tons/Tsw of the secondary side conduction time of the switching power supply to the switching period is reduced by K times, so that the product of Vcs and Tons/Tsw is kept unchanged, and the constant current output of the switching power supply is kept; meanwhile, because the Tons/Tsw is reduced, namely the Tons is unchanged, the Tsw is increased, the turn-off time Toff for the primary side conducting time Tonp to be eaten is increased, and more space can be provided for the Tonp to be adjusted when the switching power supply has low bus voltage Vbus input, so that the problem of output power frequency ripple is optimized, and the output precision of the switching power supply is improved.

Based on the same inventive concept, referring to fig. 4, the present invention further provides a switching power supply system, which includes not only the switching power supply control circuit 10 and the power switch M1, but also: the device comprises an input rectifying filter circuit, a transformer, an output rectifying filter circuit, an output voltage feedback circuit, a primary side peak voltage or peak current sampling circuit and a power supply voltage sampling circuit. The transformer is provided with a primary winding Lp of the transformer, an auxiliary winding Laux of the transformer and a secondary winding Ls of the transformer, and is mainly used for electric isolation and energy transmission of input and output. The input rectifying filter circuit is used for converting an alternating voltage signal Vac into a bus voltage Vbus to supply power to a primary winding Lp of the transformer. The output rectifying and filtering circuit is electrically connected with the secondary winding Ls of the transformer and is used for rectifying and filtering the output voltage Vout of the secondary winding Ls. The output voltage feedback circuit is connected between the auxiliary winding Laux and the switching power supply control circuit 10, and is used for sampling and feeding back the output voltage Vout of the secondary winding Ls. The primary side peak voltage or peak current sampling circuit is configured to sample the primary side peak voltage Vcs and/or the peak current Ipk, and transmit a sampling result to the mode switching circuit 102. The supply voltage sampling circuit is configured to sample the bus voltage Vbus to provide the operating voltage Vcc for the switching power supply control circuit 10.

In this embodiment, the input rectifying and filtering circuit includes a bridge rectifying circuit U1 and an input filtering capacitor C1. The output rectifying and filtering circuit comprises an output filtering capacitor C3 and a rectifying diode Ds. The output voltage feedback circuit comprises a rectifying diode Daux and two feedback resistors Rfb1 and Rfb2 which are connected in series. The primary side peak voltage or peak current sampling circuit comprises a peak sampling resistor Rcs. The supply voltage sampling circuit comprises a sampling resistor Rst and a filter capacitor C2. The specific circuit connections in the switching power supply system of the present embodiment include:

one end of an input filter capacitor C1 is connected to the output end of the bridge rectifier circuit U1 and one end of the primary winding Lp of the transformer, the other end of the input filter capacitor C1 is grounded, an alternating current power supply Vac generates a bus voltage Vbus after being rectified by the bridge rectifier circuit U1 and filtered by the input filter capacitor C1, and the bus voltage Vbus supplies power to the primary side of the transformer. Power switch tubeThe grid electrode of the M1 is connected with the driving end DRI of the switch power supply control circuit 10, the drain electrode is connected with one end of the primary winding Lp of the transformer, the source electrode is grounded through a series peak value sampling resistor Rcs, and the common end of the source electrode of the power switch tube M1 and the peak value sampling resistor Rcs is connected with the primary peak voltage or peak current sampling end CS end of the switch power supply control circuit 10. The other end of the primary winding Lp of the transformer is connected with the output end of the bridge rectifier circuit U1 to receive the input Vbus. One end of the auxiliary winding Laux of the transformer is grounded by connecting two feedback resistors Rfb1 and Rfb2 which are connected in series to obtain a feedback voltage V_FBFor realizing the feedback of the secondary output voltage Vout to the switching power supply control circuit, in particular, the feedback voltage V because the voltage of the transformer auxiliary winding Laux has a turn ratio relationship with the voltage of the transformer secondary winding Ls_FBThe common end of the two feedback resistors Rfb1 and Rfb2 is connected to the FB end of the output voltage feedback end of the switching power supply control circuit 10, reflecting the change of the secondary output voltage Vout. One end of the transformer auxiliary winding Laux is further connected with the anode of the rectifier diode Daux, and the cathode of the rectifier diode Daux is connected with the common end of the sampling resistor Rst and the filter capacitor C2, so that the bus voltage Vbus is sampled to obtain the working voltage V required by the switching power supply control circuit 10_CC. The other end of the transformer auxiliary winding Laux is grounded, and the common end of the sampling resistor Rst and the filter capacitor C2 is also connected to the VCC terminal of the switching power supply control circuit 10. One end of a secondary winding Ls of the transformer is connected with the anode of the rectifier diode Ds, and the other end of the secondary winding Ls of the transformer is grounded. The output filter capacitor C3, the filter resistor R0 and the load RL are connected in parallel between the cathode of the rectifier diode Ds and the ground, the rectifier diode Ds is used for rectification and voltage stabilization, and the filter capacitor C3 and the filter resistor R0 which are connected in parallel are used for forming a filter circuit and filtering the output voltage Vout. The switching power supply control circuit 10 obtains V according to the feedback end of the output voltage of the switching power supply_FBV obtained from the power supply terminal_CCThe primary side peak voltage or peak current sampling end obtains V_CSAnd an internally preset reference voltage V_REFThe peak current Ipk of the primary winding Lp is adjusted to generate a corresponding PFM signal and output the PFM signal to the driving end DRI to control the on and off of the power switch tube M1, so as to realizeAnd energy is transmitted from the primary winding Lp of the transformer to the output end of the secondary winding Ls of the transformer to maintain constant current output.

When the switching power supply system of this embodiment normally operates, one switching period T of the power switch M1 is actually divided into three phases: in the primary side conduction stage Tonp (Tonp is primary side conduction time), the secondary side conduction stage Tons (Tons is secondary side conduction time) and the primary side and secondary side both-off stage Toff (Toff is off time), referring to fig. 4, the primary side winding Lp stores energy in the primary side conduction stage Tonp, the energy stored in the primary side winding Lp is transmitted to the secondary side circuit in the secondary side conduction stage Tons, and the secondary side current gradually decreases to 0.

In the switching power supply system of the embodiment, the switching power supply control circuit is adopted, so that the problem of output power frequency ripple is improved, and the output precision is improved. The switching power supply system can be any primary side control type switching power supply system, such as a charger, a power adapter, an LED driving power supply, wireless communication equipment, liquid crystal display power supply management, an electronic refrigerator or an Ethernet power supply and the like.

firstly, feeding back the output voltage of a secondary side of a switching power supply in real time to obtain an FB waveform, and generating a QR mode trigger signal when detecting that the FB waveform has a full duty ratio state so as to enable the switching power supply to enter a QR mode;

secondly, when the QR mode trigger signal is effective, raising the primary peak voltage Vcs of the switching power supply by K times, and simultaneously reducing the ratio Tons/Tsw of the secondary side conduction time Tons of the switching power supply and the switching period Tsw by K times;

and then, generating a constant current control logic signal according to the adjusted peak voltage and the ratio Tons/Tsw, and outputting a driving signal according to the constant current control logic signal to control the on-off of a power switch tube of the switching power supply so that the output current of the switching power supply is constant.

Referring to fig. 3 to fig. 8B, a switching power supply control method provided by the present invention can be implemented by the switching power supply control circuit 10 of the present invention, that is, after the switching power supply control circuit 10 of the present invention is connected to a switching power supply, when an output voltage Vout of the switching power supply drops, first, an FB waveform detection circuit 101 in the switching power supply control circuit 10 feeds back the output voltage Vout of a secondary side of the switching power supply in real time to obtain an FB waveform, and when it is detected that the FB waveform has a full duty cycle state, a QR mode trigger signal is generated to make the switching power supply enter a QR mode; then, receiving the QR mode trigger signal through a mode switching circuit 102 in the switching power supply control circuit 10, and when the QR mode trigger signal is valid, raising the primary peak voltage Vcs of the switching power supply by K times, and simultaneously reducing the ratio Tons/Tsw of the secondary side conduction time Tons of the switching power supply and the switching period Tsw by K times; then, a constant current control logic signal is generated by a constant current control circuit 103 in the switching power supply control circuit 10 according to the peak voltage and the ratio Tons/Tsw adjusted by the mode switching circuit 102, and a driving signal is output according to the constant current control logic signal; and then, a driving circuit in a switching power supply control circuit outputs a driving signal (generally, a PFM signal) according to the control logic signal to control the on/off of a power switch tube M1 of the switching power supply, so as to control the on/off of the power switch tube of the switching power supply, so that the output current of the switching power supply is constant.

In summary, when the switching power supply has a low bus voltage Vbus input, the output voltage Vout of the switching power supply drops, and in this case, the switching power supply control circuit and method and the switching power supply system of the present invention can detect the feedback voltage V for feeding back the output voltage Vout of the secondary side of the switching power supply_FBWhen the waveform has a full duty ratio, the problem of output power frequency ripple is judged to occur, the peak voltage Vcs of the switching power supply is raised by K times (K is 1.1 or other numerical values), and the ratio Tons/Tsw of the secondary side conduction time of the switching power supply to the switching period is reduced by K times, so that the product of Vcs and Tons/Tsw is kept unchanged, and the constant current output of the switching power supply is kept; at the same time, because the Tons/Tsw is reduced, namely the Tons is unchanged, the Tsw is increased, and the primary side can be conductedThe off time Toff of the time Tonp consumed is increased, and when the switching power supply has lower bus voltage Vbus input, more space can be provided for the Tonp to adjust, so that the problem of output power frequency ripple is optimized, and the output precision of the switching power supply is improved.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A switching power supply control circuit, comprising:

2. The switching power supply control circuit as claimed in claim 1 wherein said FB waveform detection circuit determines that said FB waveform is in a full duty cycle state when it detects that an off-time Toff of said switching power supply occurring within a plurality of consecutive switching periods Tsw is less than a first set threshold under the condition that a current primary peak voltage Vcs of the switching power supply can reach a highest primary peak voltage value Vcs _ H.

3. The switching power supply control circuit according to claim 2, wherein the FB waveform detection circuit generates a non-QR mode trigger signal to cause the switching power supply to exit QR mode when a bus voltage rise or a load reduction of the switching power supply occurs and when it is detected that the off-time Toff is greater than a second set threshold value for a consecutive plurality of the switching periods Tsw.

4. The switching power supply control circuit according to any one of claims 1 to 3, wherein the FB waveform detection circuit includes:

the first enabling signal generating module is used for receiving an initialization signal and generating a first enabling signal according to a delay signal corresponding to the primary side on-time Tonp of the switching power supply and a delay signal corresponding to the off-time Toff of the switching power supply;

5. The switching power supply control circuit according to claim 3, wherein the mode switching circuit includes a peak voltage switching circuit and a secondary on-time duty cycle switching circuit; the peak voltage switching circuit comprises a first switch, a second switch and a comparator, wherein the input end of the first switch is connected with a primary peak voltage signal Vcs, the control end of the first switch is connected with the non-QR mode trigger signal so that the first switch is conducted when the non-QR mode trigger signal is effective, the input end of the second switch is connected with a K-time peak voltage signal K x Vcs, the control end of the second switch is connected with the QR mode trigger signal so that the second switch is conducted when the QR mode trigger signal is effective, the output ends of the first switch and the second switch are both connected with the inverting input end of the comparator, the non-inverting input end of the comparator is connected with the peak voltage signal, and the output end of the comparator is connected with the input end of the constant current control circuit; the secondary side on-time duty ratio switching circuit comprises a third switch and a fourth switch, wherein the input end of the third switch is connected with a ratio signal Tons/Tsw, the control end of the third switch is connected with the non-QR mode trigger signal so that the third switch is switched on when the non-QR mode trigger signal is effective, the input end of the fourth switch is connected with a ratio signal Tons/K Tsw which is 1/K times of that of the fourth switch, the control end of the fourth switch is connected with the QR mode trigger signal so that the fourth switch is switched on when the QR mode trigger signal is effective, and the output ends of the third switch and the fourth switch are connected with the input end of the constant current control circuit.

6. The switching power supply control circuit according to claim 3, wherein the FB waveform detection circuit generates the QR mode trigger signal when detecting that an OFF time Toff of the switching power supply occurring within a plurality of consecutive switching periods Tsw is smaller than a first set threshold value, on a condition that a current peak voltage Vcs of the switching power supply can reach a highest peak voltage value Vcs _ H; and when the condition that the bus voltage Vbus of the switching power supply rises or the load is lightened occurs, generating the non-QR mode trigger signal when detecting that the turn-off time Toff is larger than a second set threshold value in a plurality of continuous switching periods Tsw.

7. A switching power supply system, characterized by comprising the switching power supply control circuit according to any one of claims 1 to 6 and a power switch tube, wherein the power switch tube is connected with a driving circuit of the switching power supply control circuit.

8. The switching power supply system according to claim 7, further comprising:

9. A switching power supply control method, comprising:

feeding back the output voltage of a secondary side of a switching power supply in real time to obtain an FB waveform, and generating a QR mode trigger signal when the FB waveform and a full duty ratio state are detected so that the switching power supply enters a QR mode;

10. The switching power supply control method according to claim 9, wherein the step of the switching power supply entering the QR mode includes: under the condition that the peak voltage Vcs of the switching power supply can reach the highest peak voltage Vcs _ H, when the fact that the turn-off time Toff of the switching power supply in a plurality of continuous switching periods Tsw is smaller than a first set threshold value is detected, the FB waveform is judged to be in a full duty ratio state, a QR mode trigger signal is generated, and the switching power supply enters a QR mode according to the QR mode trigger signal; and the number of the first and second groups,