CN102170227B - Self-adaptive power tube adjusting circuit and method - Google Patents

Self-adaptive power tube adjusting circuit and method Download PDF

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CN102170227B
CN102170227B CN 201110109227 CN201110109227A CN102170227B CN 102170227 B CN102170227 B CN 102170227B CN 201110109227 CN201110109227 CN 201110109227 CN 201110109227 A CN201110109227 A CN 201110109227A CN 102170227 B CN102170227 B CN 102170227B
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power
output
power tube
logic unit
time
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CN102170227A (en
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罗萍
甄少伟
张业
谢谦
赵越
张波
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a self-adaptive power tube adjusting circuit and a method thereof. Aiming at the problem that the power consumption of a switch voltage regulation power supply system is over high under the existing pulse width modulation mode, the self-adaptive power tube adjusting circuit is provided. The self-adaptive power tube adjusting circuit comprises a drive, a drive logic unit, a time digitizer and a control logic unit. The pulse width of pulse width modulation (PWM) waves is compared by the time digitizer an the control logic unit, system power consumption is indirectly compared under different power tube control codes, and the power tube control tube with minimum PWM pulse width is output, so as to find the optimal conduction number of the power tubes, so that under the condition of invariable output power, the input power is reduced, the system power consumption is reduced and the system efficiency is improved. Moreover, the invention also provides the self-adaptive power tube adjusting method based on the self-adaptive power tube adjusting circuit.

Description

A kind of adaptive power regulating circuit and method
Technical field
The invention belongs to power technique fields, relate to a kind of Buck circuit that is applied under pwm pattern.
Background technology
Switching power supply often adopts PWM mode PWM(Pulse Width Modulation), make the output voltage of converter keep stable by negative feedback control loop.The PWM specific implementation is: change if the variation of input voltage or load causes output voltage, sample circuit is sampled to output voltage, and itself and reference voltage are compared, and then decides the width of pulse according to variation, makes output voltage stabilization.During greater than reference voltage, pulsewidth will be reduced when the converter output voltage; Otherwise, increase pulsewidth, make thus the output voltage stabilization of converter.
In order to improve the efficient of switching power converters, reduce the power tube loss, more advanced power tube Driving technique has the resonant power technology that applies to high-power system to reach the soft switch of power tube and synchronous rectifier at present; The resonant drive technology drives loss to reach the recycling of power tube driving-energy, to reduce; Polyphase source, the switching tube that the multichannel of parallel connection topology is used for having the poor driving signal of out of phase is controlled, thus the raising system reduces ripple current to the adaptive capacity of load variations; Double frequency switch power technology etc.In low-voltage, small-power, the PIC field of high integration, owing to being subject to system bulk, peripheral component quantity, the restriction of the conditions such as application cost, above-mentioned Driving technique is not suitable for.Be easy to integrated and the lower characteristics of cost price, can satisfy above requirement and adopt the auxiliary technology of controlling of digital circuit to have.
Summary of the invention
The objective of the invention is to have proposed a kind of adaptive power regulating circuit and method in order to solve the too high problem of switching power supply system power dissipation under existing PWM mode.
detailed technology scheme of the present invention: a kind of adaptive power regulating circuit, comprise and drive and drive logical block, time-to-digit converter and control logic unit, wherein, the PWM input of the input of time-to-digit converter and driving and driving logical block is used for the outside PWM ripple of input, the output of time-to-digit converter is connected with the input of control logic unit, the output of control logic unit is connected with the power tube control code input of driving and driving logical block, the output that drives and drive logical block is the output of adaptive power regulating circuit and is used for the power ratio control pipe.
Wherein, described control logic unit is used for power output pipe control code, after described adaptive power regulating circuit resets, the maximum N=Nmax of power output pipe control code, wherein Nmax is the value that the control logic unit presets, and the register initial value of setting described time-to-digit converter is M, is output as K, the power tube control code subtracts certainly, N=N-1; Time-to-digit converter is exported K for detection of PWM ripple pulsewidth; If K＜M, the power tube control code continues from subtracting, and N=N-1, M=K, time-to-digit converter detect and be used for PWM ripple pulsewidth, and output K also continues judgement K value; If K〉M, the power tube control code is from adding, and N=N+1, time-to-digit converter detect and are used for PWM ripple pulsewidth, and output K also continues judgement K value.
Further, described control logic unit uses the ASIC application-specific integrated circuit (ASIC) to realize by hardware description language.
Further, described driving and driving logical block comprise driver element and drive logical block, wherein, drive logical block and comprise decoder and P NAND gate, and wherein, P is the power tube number, and P is no more than 2 Nmax, the output of decoder is connected with an input of P NAND gate respectively, and another input of P NAND gate is as the PWM input that drives and drive logical block.
Adaptive power control method based on above-mentioned adaptive power regulating circuit comprises the steps:
After step 1. adaptive power regulating circuit resets, the maximum N=Nmax of control logic unit power output pipe control code, wherein Nmax is the fixed value of control logic unit internal preset, the register initial value of setting-up time digital quantizer is M, be output as K, the power tube control code subtracts certainly, N=N-1;
Step 2. time-to-digit converter detects PWM ripple pulsewidth, output K;
If step 3. K＜M, the power tube control code continues certainly to subtract, N=N-1, and M=K returns to step 2; If K〉M, the power tube control code is from adding, and N=N+1 returns to step 2.
beneficial effect of the present invention: the invention provides a kind of adaptive power regulating circuit and method for the DC-DC converter, by time-to-digit converter and control logic unit, the pulsewidth that compares the PWM ripple, indirectly compared the system power dissipation under different capacity pipe control code, the power tube control code of output PWM ripple pulsewidth minimum, and then find the number of best power tube conducting, in the situation that power output is constant, reduce input power, reduce system power dissipation, improve system effectiveness, and the circuit in the present invention is digital circuit, oneself power consumption is low, chip occupying area is little.
Description of drawings:
Fig. 1 is adaptive power regulating circuit structural representation of the present invention.
Fig. 2 is the time-to-digit converter structural representation of the embodiment of the present invention.
Fig. 3 is driving and the logic module structure signal thereof of the embodiment of the present invention.
Fig. 4 is adaptive power control method schematic flow sheet of the present invention.
Inductive current and power tube current waveform schematic diagram when Fig. 5 is the stable output of the embodiment of the present invention.
Embodiment
The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.
as shown in Figure 1, a kind of adaptive power regulating circuit, comprise and drive and drive logical block, time-to-digit converter and control logic unit, wherein, the PWM input of the input of time-to-digit converter and driving and driving logical block is used for the outside PWM ripple of input, the output of time-to-digit converter is connected with the input of control logic unit, the output of control logic unit is connected with the power tube control code input of driving and driving logical block, the output that drives and drive logical block is the output of adaptive power regulating circuit and is used for the power ratio control pipe.
Wherein, described control logic unit is used for power output pipe control code, after described adaptive power regulating circuit resets, the maximum N=Nmax of power output pipe control code, wherein Nmax is the value that the control logic unit presets, and the register initial value of setting described time-to-digit converter is M, is output as K, the power tube control code subtracts certainly, N=N-1; Time-to-digit converter is exported K for detection of PWM ripple pulsewidth; If K＜M, the power tube control code continues from subtracting, and N=N-1, M=K, time-to-digit converter detect and be used for PWM ripple pulsewidth, and output K also continues judgement K value; If K〉M, the power tube control code is from adding, and N=N+1, time-to-digit converter are for detection of PWM ripple pulsewidth, and output K also continues judgement K value.Here power tube control code N has determined the number of power tube conducting.
Here, the control logic unit can be by hardware description language ASIC(Application Specific Integrated Circuit) application-specific integrated circuit (ASIC) realizes.
In Fig. 1, VIN is the input voltage of Buck circuit, is connected to the source electrode of P type power tube PMOS, and PMOS and diode DIODE, inductance L, capacitor C have consisted of simple Buck circuit together.The output voltage VO of Buck circuit produces corresponding PWM ripple by compensation and PWM generation unit.Drive and drive the power tube control code of logical block input PWM ripple and control logic unit output, the driving signal that output is corresponding, the corresponding power tube number of conducting, time-to-digit converter detects the PWM ripple simultaneously, detection power Guan Zaiyi the ON time that switch periods is interior, turn-off period at the power tube in this cycle, give the control logic unit with the output valve of time-to-digit converter.
Time-to-digit converter TDC structural representation as shown in Figure 2, the W(odd number) be connected to form ring oscillator before and after individual reverser, ph1 to phW is respectively the output clock of W reverser.Two bit counters is W-1 two digit counters, and input clock ph1 to phW-1 is that Gao Shigao counts at the PWM ripple.Counter is a W digit counter, and input clock phW is that height is counted at the PWM ripple, and low two with all Two bit counters outputs with Counter output compare, obtain comparison value, then all comparison value additions are obtained Y.The Counter output valve be multiply by W obtain Z.At last with the K that obtains of Y and Z addition.
Here, drive and drive logical block and comprise driver element and drive logical block, wherein, drive logical block and comprise decoder and P NAND gate, wherein, P is the power tube number, and P is no more than 2 Nmax, the output of decoder is connected with an input of P NAND gate respectively, and another input of P NAND gate is as the PWM input that drives and drive logical block.
Describe as an example of three power tube control codes example and drive and drive logical unit structure, as shown in Figure 3.Decoder is received the power tube control code S2 of control logic module output, S1, and S0, the output of process decoder is connected on a drive circuit with the PWM ripple through a NAND gate separately, drives a power tube.Always have 1 decoder, 7 NAND gate, 7 drive circuits and 7 power tubes.
Adaptive power control method based on above-mentioned adaptive power regulating circuit comprises the steps:
Fig. 4 is the schematic flow sheet of the adaptive power control method of adaptive power regulating circuit.Specifically be unfolded as follows:
After step 1. adaptive power regulating circuit resets, the maximum N=Nmax of control logic unit power output pipe control code, wherein Nmax is the value that the control logic unit presets, the register initial value of setting-up time digital quantizer is M, be output as K, the power tube control code subtracts certainly, N=N-1;
Step 2. time-to-digit converter detects PWM ripple pulsewidth, output K;
If step 3. K＜M, the power tube control code continues certainly to subtract, N=N-1, and M=K returns to step 2; If K〉M, the power tube control code is from adding, and N=N+1 returns to step 2.
Inductive current and power tube current waveform schematic diagram when Fig. 5 is stable output.T is switch periods, and d is duty ratio.t 0Be the starting point of a switch periods, this moment, power tube current and inductive current were i 0At t 0To t 0+ dT during this period of time in, the power tube conducting, inductive current and power tube current are all pressed slope Rise.At t 0+ dT is to t 0+ T during this period of time, power tube turn-offs, inductive current is pressed slope
Figure GDA00002856173400042
Descend, power tube current is 0.
Introduce specific works principle of the present invention below in conjunction with Fig. 5.When the adaptive power regulating circuit was stablized, output power of circuit was constant, if the power tube ON time reduces, input power reduces, and circuit efficiency improves.t 0Constantly, power tube begins conducting, and power tube current equals inductive current i 0, electric current is pressed slope
Figure GDA00002856173400043
Rise, wherein L is the inductance value of inductance L, and duty ratio is d, and switch periods is T.At t 0In+dT the moment, inductive current and power tube current are i 1=i 0+ m 1DT, this moment loop stability, in the constant situation of load, the output energy constant of establishing each switch periods is E o, the input energy in each switch periods is:
E i = ∫ t 0 t 0 + dT V in idt = ∫ t 0 t 0 + dT V in [ i 0 + m 1 ( t - t 0 ) ] dt = 1 2 m 1 d 2 T 2 + m 1 t 0 dT + i 0 dT
Can find out, d reduces along with duty ratio, the input ENERGY E iReduce efficient
Figure GDA00002856173400045
Increase.The present invention is exactly under stable case, the ON time when counting by detecting conducting different capacity pipe, and namely duty ratio, select the power tube number of duty ratio corresponding minimum to carry out conducting.
The loss of power tube is from two parts: conduction loss and switching loss.When the conducting power tube was maximum, switching loss was maximum, and conduction loss is minimum; When the conducting power tube is minimum be, switching loss is minimum, and conduction loss is maximum.There is a power tube conducting number between, makes switching loss and conduction loss sum minimum.The structure that can propose by Fig. 1 detects duty ratio, obtains optimal value.
Detecting duty ratio realizes by time-to-digit converter.The W(odd number) be connected to form ring oscillator before and after individual reverser, ph1 to phW is respectively the output clock of W reverser.Two bit counters is W-1 two digit counters, and input clock ph1 to phW-1 is that Gao Shigao counts at the PWM ripple, and Counter is a W digit counter, and input clock phW is that height is counted at the PWM ripple.Low two with all Two bit counters outputs with Counter output compare, and obtain comparison value, then all comparison value additions are obtained Y, the Counter output valve be multiply by W obtain Z, with the K that obtains of Y and Z addition, are PWM ripple pulsewidth at last.
After time-to-digit converter detected and finishes, with the register value of output valve and time-to-digit converter, namely current minimum value compared, and determines next power tube control code.
The power tube control code is delivered to and is driven and drive logical block, and by decoder, output is passed through power tube of a drive unit drives after being connected on a NAND gate with the PWM ripple respectively.Because power tube is PMOS, only have like this when the PWM ripple when being high, power tube just may conducting.
Can find out, adaptive power regulating circuit of the present invention and method are by comparing the pulsewidth of PWM ripple, indirectly compared the system power dissipation under different capacity pipe control code, export the power tube control code of PWM ripple pulsewidth minimum, find the number of best power tube conducting, in the situation that power output is constant, reduce input power, reduce system power dissipation, improve system effectiveness, and the circuit in the present invention is digital circuit, oneself power consumption is low, and chip occupying area is little.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood to that the protection range of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection range of claim of the present invention.

Claims (5)

1. adaptive power regulating circuit, it is characterized in that, comprise and drive and drive logical block, time-to-digit converter and control logic unit, wherein, the PWM input of the input of time-to-digit converter and driving and driving logical block is used for the outside PWM ripple of input, the output of time-to-digit converter is connected with the input of control logic unit, the output of control logic unit is connected with the power tube control code input of driving and driving logical block, the output that drives and drive logical block is the output of adaptive power regulating circuit and is used for the power ratio control pipe,
Described control logic unit is used for power output pipe control code, after described adaptive power regulating circuit resets, the maximum N=Nmax of power output pipe control code, wherein Nmax is the value that the control logic unit presets, the register initial value of setting described time-to-digit converter is M, be output as K, the power tube control code subtracts certainly, N=N-1; Time-to-digit converter is exported K for detection of PWM ripple pulsewidth; If K＜M, the power tube control code continues from subtracting, and N=N-1, M=K, time-to-digit converter are for detection of PWM ripple pulsewidth, and output K also continues judgement K value; If K〉M, the power tube control code is from adding, and N=N+1, time-to-digit converter are for detection of PWM ripple pulsewidth, and output K also continues judgement K value.
2. adaptive power regulating circuit according to claim 1, is characterized in that, described control logic unit uses the ASIC application-specific integrated circuit (ASIC) to realize by hardware description language.
3. adaptive power regulating circuit according to claim 1 and 2, is characterized in that, described driving and driving logical block comprise driver element and drive logical block, wherein, drive logical block and comprise decoder and P NAND gate, wherein, P is the power tube number, and P is no more than 2 Nmax, the output of decoder is connected with an input of P NAND gate respectively, and another input of P NAND gate is as the PWM input that drives and drive logical block.
4. an adaptive power control method, comprise the steps:
After step 1. adaptive power regulating circuit resets, the maximum N=Nmax of control logic unit power output pipe control code, wherein Nmax is the value that the control logic unit presets, the register initial value of setting-up time digital quantizer is M, be output as K, the power tube control code subtracts certainly, N=N-1;
Step 2. time-to-digit converter detects PWM ripple pulsewidth, output K;
If step 3. K＜M, the power tube control code continues certainly to subtract, N=N-1, and M=K returns to step 2; If K〉M, the power tube control code is from adding, and N=N+1 returns to step 2.
5. adaptive power control method according to claim 4, is characterized in that, described control logic unit uses the ASIC application-specific integrated circuit (ASIC) to realize by hardware description language.
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CN102457172A (en) * 2011-12-13 2012-05-16 上海微频莱机电科技有限公司 Switching power supply
CN102983719B (en) * 2012-11-30 2016-04-06 西安智海电力科技有限公司 Many Waveform Inputs adaptive power supply transducer
CN103576734B (en) * 2013-10-21 2015-06-17 电子科技大学 Dual-ring control self-adapting voltage adjusting method and device
CN106793050B (en) * 2017-01-04 2021-01-08 惠州Tcl移动通信有限公司 LTE (Long term evolution) turn-off power improvement method and system
CN109149912B (en) * 2018-09-15 2020-12-25 福州大学 Switching tube power loss and automatic adjusting circuit in switching power supply and working method

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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
TW448605B (en) * 1998-06-18 2001-08-01 Linear Techn Inc Voltage mode feedback burst mode circuit
US7821236B2 (en) * 2006-11-10 2010-10-26 Fujitsu Semiconductor Limited Control circuit for detecting a reverse current in a DC-DC converter
CN101090272A (en) * 2007-07-05 2007-12-19 复旦大学 Mixed digital pulse duration modulater suitable for digital power supply controller
CN101931323A (en) * 2010-08-05 2010-12-29 西安交通大学 Method for enhancing non-uniform variation grid width of light load efficiency of integrated switch DC-DC converter

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