CN1938932B - Discontinuous mode PFC controller with energy-saving modulator and its operating method - Google Patents
Discontinuous mode PFC controller with energy-saving modulator and its operating method Download PDFInfo
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- CN1938932B CN1938932B CN2004800427478A CN200480042747A CN1938932B CN 1938932 B CN1938932 B CN 1938932B CN 2004800427478 A CN2004800427478 A CN 2004800427478A CN 200480042747 A CN200480042747 A CN 200480042747A CN 1938932 B CN1938932 B CN 1938932B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The present invention discloses a ZCS discontinuous mode PFC controller having a power saving modulator. The controller turns on through the feedback resistor and the parasitic diode of the controller, thus eliminating the need for a startup resistor. To achieve ZCS, the inductor current is released to zero, while the switching signal is off, before the next switching cycle starts. In order to decrease the switching frequency for light load conditions, an off-time delay is inserted right before the start of every switching cycle. The off-time delay is modulated to be the function of the feedback voltage and supply voltage. When the supply voltage is lower than the limit voltage, the off-time delay will decrease to inhibit the decrease of a switching frequency therefore prevents a low supply voltage. The switching frequency is decreased in accordance with the decrease of the load. Consequently, the switching losses and power consumption for light load and no load conditions are reduced.
Description
Technical field
(power factor correction, PFC) controller and method of operation thereof particularly relate to a kind of discontinuous mode power factor correction controller and its method of operation that is used to have energy-saving modulator to the present invention relates to a kind of power factor correction.
Background technology
The topology of boosting (boost topology) is all integrated and utilized to most of power factor correction technologies, and it can be operated with continuous and discontinuous inductor current pattern under fixing or changeable switch frequency.Owing to apply and operate low peak current, therefore the continuous inductor current pattern with fixedly switching frequency operation is used for higher-power applications.For the application below 250 watts, use the discontinuous inductor current pattern of changeable switch frequency operation that several advantages are provided, comprise midget inductor, low cost, simple circuit and zero current switch (zero current switching, ZCS).The pulse duration of power factor correction (PFC) controller is controlled by voltage error amplifier, and it is compared with the sawtooth waveform that is produced by controller.Pulse duration changes along with line input and loading condition, is constant in half line input cycle (line cycle) but should keep.Therefore, voltage error amplifier is necessary to have the lower frequency bandwidth that is lower than the line incoming frequency.
ZCS comprises several advantages in application.An advantage is that before next switching cycle begins inductor current must be discharged into zero, and this produces high switching efficiency.Because the variation of inductor current equals the peak value inductor current, and electric current all begins in each cycle and turns back to zero, so current waveform has triangle, its mean value equals half of product that peak current multiply by its time.Therefore peak current will limit and just be the twice of average current.Because ZCS just switches on the edge of continuous and discontinuous current-mode, so will be in variable switching frequency operation.By line input and output load decision, the pulse duration of switching signal is modulated, and switching frequency can step-down for the heavy duty condition and response light-load conditions and uprising.Low bandwidth pulse width modulation (pulse wave width modulation, PWM) in conjunction with ZCS so that the power factor correction of input current nature to be provided.
In recent prior art, researched and developed the discontinuous current power factor correction controller of various ZCS at Power Factor Correction Control.Wherein, power factor correction controller comprises the ST6561 of French ST-Microelectronics company; The MC34262 of Colorado ON-Semiconductor company; And the TDA4862 of German Siemens company.All these controllers all are designed under light-load conditions and/or no-load condition with high frequencies of operation.The handoff loss and the switching frequency of power converter and power factor correcting step-up device are proportional, and wherein the power consumption and the inductor loss of the handoff loss of switching transistor, buffer (snubber) increase along with higher switching frequency.The shortcoming of the controller of front is under the high frequencies of operation under the light-load conditions, power converter is difficult to satisfy energy-conservation requirement, therefore, especially for underload and no-load condition, be desirable to provide a kind of power factor correction controller, its holding power factor correcting function and low power consumption is provided under underload.
Summary of the invention
The object of the present invention is to provide a kind of zero current to switch (ZCS) discontinuous mode power factor correction controller, so that the high efficiency power factor correction to be provided, and under light-load conditions, reduce the power consumption of power factor correction controller.
Another object of the present invention is to exempt startup resistor, to have saved power.
Another object of the present invention is to provide a kind of peak power output of power-limiting factor correcting controller that is used for so that the method for low-voltage variation to be provided.
The present invention relates to ZCS discontinuous mode power factor correction controller.When the line input voltage was applied to power factor correction converter, the feedback resistor of controller and parasitic diode started described controller.In case controller is enabled, transistor will switch feedback resistor, makes it become the voltage divider of voltage feedback loop.
For power factor correction, external resistor is used to determine the maximum turn-on time of switching signal, has therefore limited peak power output.When turn-offing switching signal, before next switching cycle begins, inductor current will be discharged into zero, and this has realized ZCS.
In order to reduce the switching frequency of light-load conditions, before beginning, inserts each switching cycle the shut-in time delay.Feedback voltage and the supply voltage obtained from voltage feedback loop are regarded as variable.Shut-in time postpones to be modulated to the function of feedback voltage and supply voltage.Threshold voltage is constant, and it defines underloaded level.
The low level of deboost definition supply voltage.In case feedback voltage reduces and is lower than threshold voltage, the shut-in time delay will correspondingly increase.When supply voltage was lower than deboost, the shut-in time postponed to reduce to suppress the minimizing of switching frequency, therefore, thereby prevents low supply voltage.Switching frequency reduces according to the minimizing of load.
Therefore, this has reduced handoff loss and power consumption under underload and the no-load condition.
Description of drawings
The present invention comprises accompanying drawing providing further understanding of the present invention, and accompanying drawing is incorporated in this specification and constituted its part.Graphic explanation embodiments of the invention, and be used from and explain principle of the present invention together with describing content one.
Fig. 1 is the schematic diagram of discontinuous mode power factor correction according to the preferred embodiment of the invention (PFC) transducer.
The waveform of the discontinuous mode power factor correction converter of the preferred embodiment of the present invention shown in Fig. 2 displayed map 1.
Fig. 3,4 and 5 is schematic diagrames of control circuit of the discontinuous mode power factor correction converter of the preferred embodiment of the present invention shown in Fig. 1.
Embodiment
Fig. 1 is the schematic diagram of discontinuous mode power factor correction according to the preferred embodiment of the invention (PFC) transducer.Power factor correction converter comprises electric bridge 10, inductor 20, rectifier 30 and capacitor 40.For feedback operation, power factor correction converter more comprises controller 100; Capacitor 41 and 43; Resistor 50,51 and 53; The voltage divider that comprises resistor 55 and resistor 56; Transistor 60 and 62 and diode 75.Via power factor correction converter, exchange the input of (AC) line and be converted to direct current (DC) output VO, wherein switch current 91 switchings come control energy via the AC of input inductor 20, rectifier 30 and capacitor 40.The purpose of power factor correction converter is that the electric current I AC Waveform Control with AC line input is a sinusoidal waveform, and it is identical with AC line input voltage VAC to keep the phase place of IAC.Via the rectification of electric bridge 10, VIN with respect to the ground connection of power factor correction converter always for just.
V
IN(t)＝V
Psin(ωt)
Wherein
(in root mean square " RMS " value) input current can be expressed as similarly:
I
IN(t)＝I
Psin(ωt)；
Wherein
Then the input power of power factor correction converter can be given as:
P
IN＝V
P×I
P/2
(η) introduces described equation with efficient, and power output is given as:
P
O＝P
IN×η
P
O＝V
P×I
P×η/2----------------------------------(1)
Equation 1 can be expressed as relevant with input current
I
P＝(2×P
O)/(V
P×η)---------------------------------(2)
When the conduction mode of border, the peak value switch current (IL-P) of inductor 20 just in time is the twice of average inductor current.
I
L-P＝2×I
P
I
L-P＝(4×P
O)/(V
P×η)------------------------------(3)
Switch current 91 deformation type is at that time showed.
I
L(t)＝(4×P
O)sin(ωt)/(V
P×η)----------------------------(4)
Switch current 91 also can solve inductor L is charged to peak current required turn-on time, for example I=L (di/dt).
T
ON＝I
L-P×L/V
P
T
ON＝(4×P
O×L)/(V
P 2×η)?----------------------------------(5)
T
OFF＝(I
L-P×L)/(V
O-V
P)
T
OFF＝(4×P
O×L)/[(η×V
P)×(V
O-V
P)]?-------------------(6)
T＝T
ON+T
OFF
Equation 5 can be expressed as relevant with power output.
P
O＝[V
P 2×η/(4×L)]×T
ON -------------------(7)
According to the equation 7 of front, it should be noted that power output is by TON control turn-on time.By limiting maximum turn-on time, peak power output will be restricted, especially for low-voltage variation, and the situation of brownout (brownout) for example.
When AC power was applied to power factor correction converter, the dc voltage on the output voltage VO produced via electric bridge 10, inductor 20, rectifier 30 and capacitor 40.By the parasitic diode 32 of feedback resistor 55 and controller 100, output voltage VO is charged to capacitor 41.Voltage VCC among the power supply terminal VCC of controller 100 (hereinafter being expressed as " VCC ") is the voltage level of capacitor 41.In case the voltage VCC in the capacitor 41 is higher than the actuation threshold threshold voltage of controller 100, controller 100 will be activated.In the moment that controller 100 starts, can connect transistor 62 at for example 2 volts the voltage that the reference terminal RT of controller 100 (hereinafter being expressed as " RT ") locates to set up.Simultaneously, resistor 56 ground connection.Resistor 55 and 56 forms the voltage divider of feedback loop.Therefore, resistance 55 and 56 combined resistance are connected to the back coupling terminal FB (hereinafter being expressed as " FB ") of controller 100.
FB and compensation terminal COM (hereinafter being expressed as " COM ") serve as the input terminal and the lead-out terminal of error amplifier 205, as shown in Figure 3 and as will be described in more detail below.Be connected capacitor 43 between FB and the COM in order to frequency compensation as the low frequency bandwidth below the line incoming frequency.The OUT lead-out terminal of controller 100 (hereinafter being expressed as " OUT ") output switching signal is with driving transistors 60.After controller 100 started, the additional winding of inductor 20 charged via the 75 pairs of capacitors 41 of diode that are arranged between power supply terminal VCC and the detecting terminal DET, and was controller 100 power supplies.Voltage in the capacitor 41 remains on and is higher than outage threshold voltage to keep operation and to prevent that voltage VCC is in low level in controller 100.
When the signal of the OUT of transistor 60 origin self-controllers 100 drives when connecting, inductor 20 is recharged via transistor 60.Resistor 53 sensing switch currents 91 and be connected to the input terminal VS (hereinafter being expressed as " VS ") of controller 100.As long as the voltage level at VS place is higher than deboost VR3, will cut off from the signal of OUT, this has realized that Cycle by Cycle (cycle-by-cycle) electric current that is used to switch limits.When transistor 60 was disconnected by the signal from OUT, the energy that is stored in the inductor 20 was discharged into output voltage VO by discharging current 92 via rectifier 30.Illustrate waveform among Fig. 2.In a single day discharging current 92 drops to zero, will detect no-voltage in the additional winding of inductor 20.The detecting terminal DET (hereinafter being expressed as " DET ") of controller 100 is connected to additional winding via resistor 51, is used to detect zero current condition.In case detect zero current condition, the shut-in time postpones td and just begins.After the shut-in time postponed td, controller 100 just can begin next switching cycle.The reference terminal RT of slave controller 1070 is connected to the maximum turn-on time of the resistor 50 decision switching signals signal of lead-out terminal (for example from) on ground (GND).
Referring to Fig. 3,4 and 5, it is the schematic diagram of preferred embodiment that is used for the control circuit 100 of the discontinuous mode power factor correction converter of the present invention shown in Fig. 1.Referring to Fig. 3, at first, control circuit 100 comprises a constant current source 315; Delayed current source 300; Error amplifier 205; Comparator 210,211,214 and 215; Inverter 221,222 and buffer 226; NAND gate 223,225; NOR gate 227 and set-reset flip-floop 228.Apply the voltage level in the detecting terminal that the electric current I R1 that is produced by constant current source 315 draws high controller 100.In case the voltage level of DET is detected as low signal, promptly the voltage level of DET is lower than first threshold voltage VR1, and comparator 210 is with the logic low state output signal so, and then via disconnecting transistor 231 with non-223 output.Then open the shut-in time delay td shown in beginning Fig. 2 by cutting off transistor 231.The electric current I d that is produced by delayed current source 300 begins capacitor 241 is charged, in case and the voltage level of capacitor 241 be higher than the second threshold voltage VR2, comparator 211 will be with the logic high state output signal.Via using set-reset flip-floop 228, decide switching signal PWM.The shut-in time delay can be set fourth as:
T
d＝(C
241×V
R2)/I
d?----------------------(8)
Wherein C241 is the electric capacity of capacitor 241.
Shut-in time postpones the function that td is modulated into feedback voltage and VCC voltage.Respectively with the output of comparator 211 with come the feedback voltage of self-feedback terminal to be applied to two inputs of set-reset flip-floop 228.To be applied to the input terminal of error amplifier 205 from the feedback voltage of FB, and reference voltage VR will be applied to another input terminal of error amplifier 205, and then produce once the voltage VCOM that amplifies from error amplifier 205.Then voltage VCOM is applied to the positive input terminal of comparator 214, and signal SAW is applied to negative input end of comparator 214.Then the output of comparator 214 is applied to an input terminal of NAND gate 223 and an input terminal of NAND gate 225.Another input terminal of NAND gate 225 is applied in the PULSE signal.To describe signal SAW and PULSE in detail after a while.Then the output of NAND gate 225 is applied to an input terminal of NOR gate 227.Another input terminal of NOR gate 227 is applied in the output of inverter 222.The output of inverter 222 is from the anti-phase signal of the output of comparator 215.As shown in fig. 1, comparator 215 input terminal is applied in the voltage of the current-sense terminal of self-controller 100.Another input terminal of comparator 215 is applied in the 3rd threshold voltage VR3.Via the voltage level, signal SAW and the PULSE that adjust VCOM, the shut-in time postpones to be modulated into by set-reset flip-floop 228 function of feedback voltage.
Referring to Fig. 3, can produce according to loading condition from the electric current I d in delayed current source 300.Circuit among Fig. 5 comprises first current mirror of being made up of transistor 273,274 and 275; Second current mirror of forming by transistor 277 and 278; And the 3rd current mirror of forming by transistor 291 and 292.The image current that transistor 270 and resistor 50 produce in first current mirror.The gate terminal of transistor 270 is couple to the output of operational amplifier (op-amplifier) 260.The positive input terminal of operational amplifier 260 is applied in the 7th threshold voltage VR7, and negative input end of operational amplifier 260 is couple to the source terminal and the resistor 50 of transistor 270.The image current of first current mirror is VR7/R50, thereby and two electric current I T1 and IT2 respectively according to the width/height of transistor 273 relative transistors 274 and 275 than generation.Therefore, electric current I T1 equals (VR7/R50) (N274/N273), and wherein N274, N273 are respectively the width/height ratio of transistor 274 and 273.Electric current I T2 equals (VR7/R50) (N275/N273), and wherein N275, N273 are respectively the width/height ratio of transistor 275 and 273.
Image current in second current mirror is produced by transistor 271 and resistor 282.The gate terminal of transistor 271 is couple to the output of operational amplifier 261.The positive input terminal of operational amplifier 261 is applied in VCOM, and as shown in Figure 3, and negative input end of operational amplifier 261 is couple to the source terminal of transistor 271 and a terminal of resistor 282.The another terminal of resistor 282 is couple to the lead-out terminal and negative input end of operational amplifier 262.The positive input terminal of operational amplifier 262 is applied in the 5th threshold voltage VR5.The image current of second current mirror can be expressed as (VCOM-VR5)/R282, and wherein R282 is the resistance of resistor 282.
Image current in the 3rd current mirror is produced by transistor 293 and resistor 288.The gate terminal of transistor 293 is couple to the output of operational amplifier 264.The positive input terminal of operational amplifier 264 is applied in the 6th threshold voltage VR6, and negative input end of operational amplifier 264 is couple to the source terminal of transistor 293 and a terminal of resistor 288.The another terminal of resistor 288 is couple to the lead-out terminal and negative input end of operational amplifier 265.The positive input terminal of operational amplifier 265 is applied in from by the voltage that produces behind the VCC of resistor 285 and 286 decay.The image current of the 3rd current mirror can be expressed as (VR6-α VCC)/R288, and wherein R288 is the resistance of resistor 288, α=R286/ (R286+R285), and R286 and R285 are respectively the resistance of resistor 286 and 285.
As shown in Figure 3, can obtain the electric current I d in delayed current source 300 via the right side mapping current Ib that adds up the left side mapping electric current I a that produces from image current and produce from image current by the 3rd electric current of transistor 291 mirror images of comparing with transistor 292 by second electric current of transistor 278 mirror images of comparing with transistor 277.The 5th threshold voltage VR5 is the constant that defines the underload level.The 6th threshold voltage VR6 is the low level deboost that is used to define VCC voltage.In case the voltage VCOM that reduces is lower than the 5th threshold voltage VR5, the shut-in time delay will correspondingly increase.When the VCC voltage of decay is lower than the 6th threshold voltage VR6, can reduces the reduction of shut-in time delay, thereby avoid low VCC voltage with the inhibition switching frequency.Switching frequency reduces according to the minimizing of load.Therefore, handoff loss and power consumption under underload and the no-load condition have been reduced.Formula is described below:
I
d＝I
a+I
b
I
d＝[(V
COM-V
R5/R
282]×K
1+[(V
R6-αV
CC)/R
288]×K
2--------(9)
α＝R
286/(R
286+R
285)
K
1＝N
278/N
277；
K
2＝N
291/N
292；
I
d≤I
T2
I wherein
T2=(V
R7/ R
50) * (N
275/ N
273)
I
T1＝(V
R7/R
50)×(N
274/N
273)----------------------------(10)
Referring to Fig. 4, it illustrates the circuit of the preferred embodiment of signal SAW shown in Fig. 3 and PULSE.Described circuit comprises comparator 217, NAND gate 250, transistor 232, current source 310, capacitor 242 and set-reset flip-floop 229.Illustrate the electric current I T1 of current source 310 among Fig. 5.Switching signal PWM is applied to an input terminal of NAND gate 250.The lead-out terminal of NAND gate 250 is applied to the gate terminal of transistor 232.In case switching signal PWM is high, transistor 232 promptly is disconnected.The electric current I T1 of current source 310 begins capacitor 242 is charged and produce the SAW signal of sawtooth waveform in capacitor 242.The switching signal PWM that closes will connect transistor 232, and then capacitor 242 be discharged.The SAW signal is applied to negative input end of comparator 217, and the 4th threshold voltage VR4 is applied to the positive input terminal of comparator 217, and be the PULSE signal on the lead-out terminal of comparator 217 then, it is applied to set-reset flip-floop 229.The output of set-reset flip-floop 229 is applied to another input terminal of NAND gate 250.As shown in Figure 3, if the output voltage V COM of error amplifier 205 is lower than the SAW voltage of signals, or being higher than the 3rd threshold voltage VR3 from the voltage of current-sense terminal, it can close switching signal PWM so for the overcurrent threshold voltage under the overcurrent condition.If it is high that switching signal PWM keeps, as long as SAW voltage of signals level is higher than the 4th threshold voltage VR4, the sawtooth waveform of SAW signal will be discharged so.
Therefore, the maximum turn-on time of switching signal PWM is by (C242 * VR4)/IT1 decides, and wherein C242 is the electric capacity of capacitor 242.As seen, IT1 equals (VR7/R50) * (N274/N273) from equation 10, and equal the maximum turn-on time of switching signal PWM (R50 * C242 * VR4)/[VR7 * (N274/N273)].
Therefore, as shown in fig. 1, decide according to resistor 50 the maximum turn-on time of switching signal PWM.The description of front can be expressed as:
T
ON-MAX＝(C
242×V
R4)/I
T1 --------------------(11)
T
ON-MAX＝(R
50×C
242×V
R4)/[V
R7×(N
274/N
273)]?----------(12)
Wherein TON-MAX is the maximum turn-on time of switching signal PWM.
Because the maximum turn-on time of switching signal PWM is limited, damage with the overstress of avoiding under the low-voltage condition so the switching device shifter of power factor correction converter is protected.
According to ZCS of the present invention and discontinuous mode power factor correction conversion, next switching cycle starts from the boundary of zero inductance device current status, and wherein shut-in time delay td is almost nil.Energy is given as:
ε＝L×I
2/2 -------------------(13)
Power by the power factor correcting step-up converter supplies can be expressed as:
P
O＝[V
P 2×η×T
ON 2/(4×L×T)] ---------------(14)
Show T=TON+TOFF in the equation 5 and 6.When loading on of power factor correction converter reduced under the light-load conditions, the shut-in time postponed the corresponding increase of td, and before being inserted in next switching cycle and beginning.Therefore, the switching cycle T of switching signal is extended for:
T＝T
ON+T
OFF+t
d ----------------------(15)
Therefore, under underload and no-load condition, the switching frequency of switching signal reduces.Therefore, standby power reduces.In addition, the feature that the shut-in time postpones helps to keep the regulated output voltage VO (VO=PO/IO) of power factor emendation function and holding power factor correcting transducer under light-load conditions.Referring to equation 14,, should produce very little TON pulse duration for extremely light loading condition.Extremely Duan TON has increased the difficulty of power factor correction converter design.The restriction of the short pulse width of TON has been limited the performance of power converter, therefore, must add dummy load at the output of power factor correction converter, to obtain stable output voltage VO.According to equation 14 and 15, it shows that the insertion of shut-in time delay td of the present invention has prolonged switching cycle T and do not needed extremely short TON.Keep stable output voltage VO and do not need dummy load, this has saved the power consumption in the power factor correction converter.
Be understood by those skilled in the art that,, can make various modifications and change structure of the present invention under the situation of scope of the present invention or spirit.In view of aforementioned content,, modification of the present invention and change contain these modifications and change if in the scope of claims and its equivalent, then wishing the present invention.
Claims (12)
1. discontinuous mode power factor correction controller, it is used for a power factor correction converter, wherein said power factor correction converter comprises an electric bridge, an inductor, a rectifier and a main capacitor, a plurality of switching cycles are applied to described power factor correction converter, it is characterized in that wherein said power factor correction controller comprises:
One power supply terminal, it is couple to one first capacitor and thinks described power factor correction controller power supply;
One reference terminal, it is couple to a gate terminal of a first transistor;
One earth terminal, its ground connection;
One compensation terminal;
One feedbacks terminal, and wherein one second capacitor is coupled between described compensation terminal and the described back coupling terminal to be used for frequency compensation, and described back coupling terminal is couple to an output of described power factor correction converter via one second resistor;
One detecting terminal, it is couple to one of described inductor via a detecting resistor and adds winding, is used to detect a zero current condition of described inductor;
One lead-out terminal, it is couple to a gate terminal of a transistor seconds, one drain terminal of wherein said transistor seconds is couple to the node between described inductor and the described rectifier, the one source pole terminal of described transistor seconds is couple to ground via one the 3rd resistor, and wherein one switches signal is applied to described transistor seconds from described lead-out terminal described gate terminal;
One constant current source is used to draw high the voltage level on the described detecting terminal of described controller;
One the 3rd transistor, when the described voltage level of described detecting terminal is detected as low signal, described the 3rd transistor will disconnect;
One delayed current source, it is couple to described the 3rd transistor and one the 3rd capacitor, open described shut-in time delay of beginning via disconnecting described the 3rd transistor, described delayed current source begins described the 3rd capacitor is charged, and in case a voltage level of described the 3rd capacitor is higher than one second threshold voltage, just enable described switching signal, the electric current in wherein said delayed current source produces according to the loading condition of described power factor correction converter; And
One current-sense terminal, it is coupled between the described source terminal and described the 3rd resistor of described transistor seconds, and a drain terminal of wherein said the first transistor is couple to described second resistor via one the 4th resistor and described back coupling terminal, wherein
One shut-in time postponed to be inserted in before each described switching cycle begins, the described shut-in time postpones to be modulated to the function of a feedback voltage and a supply voltage, wherein said supply voltage is the voltage level on the described power supply terminal, when described supply voltage is lower than a deboost, the described shut-in time postpones correspondingly to reduce and prevent low supply voltage, and a switching frequency reduces according to the minimizing of load, and
One first resistor is connected to ground from described reference terminal, and wherein said first resistor determines a maximum turn-on time of described switching signal.
2. discontinuous mode power factor correction controller according to claim 1, it is characterized in that wherein said controller more comprises an error amplifier, be used to receive a described feedback voltage and a reference voltage and export once the voltage that amplifies, wherein said feedback voltage is the voltage on the described back coupling terminal, and when described voltage through amplifying is lower than one the 5th threshold voltage according level, the described shut-in time postpones and will correspondingly increase, and described the 5th threshold voltage is the constant that defines a underload level.
3. discontinuous mode power factor correction controller according to claim 2, it is characterized in that wherein said controller more comprises one the 4th comparator, it has negative input end of a voltage level of the described current-sense terminal that is used to receive described controller, and has a positive input terminal that is used to receive an overcurrent threshold voltage, when the described voltage level of described current-sense terminal is higher than described overcurrent threshold voltage, described switching signal will be stopped using.
4. discontinuous mode power factor correction controller according to claim 1 is characterized in that wherein producing the circuit from an electric current in described delayed current source, comprising:
One first current mirror, it is couple to described first resistor, is used to provide one first image current from described first resistor;
One second current mirror, it is couple to one the 5th resistor, be used to provide one second image current from described the 5th resistor, one end of wherein said the 5th resistor is couple to negative input end of one first operational amplifier, and the other end of described the 5th resistor is couple to one the 5th threshold voltage by one second operational amplifier; And
One the 3rd current mirror, it is couple to one the 6th resistor, be used to provide one the 3rd image current from described the 6th resistor, one end of wherein said the 6th resistor is couple to negative input end of one the 3rd operational amplifier, and the other end of described the 6th resistor is couple to one the 6th threshold voltage by a four-operational amplifier, and the described constant current source that wherein is used to draw high the described voltage level on the described detecting terminal of described controller determines according to described second image current and described the 3rd image current.
5. discontinuous mode power factor correction controller according to claim 4, it is characterized in that wherein said the 5th threshold voltage is a constant that defines a underload level, wherein be lower than described the 5th threshold voltage when reducing to once the voltage that amplifies, the described shut-in time postpones just correspondingly to increase.
6. discontinuous mode power factor correction controller according to claim 4, it is characterized in that wherein said the 6th threshold voltage is a deboost that is used to define the low level voltage on the described power supply terminal of described controller, wherein when the described voltage level in the described power supply terminal of described controller is lower than described deboost, reduce described shut-in time delay to suppress the minimizing of described switching frequency, therefore prevent that the described voltage in the described power supply terminal of described controller is in low voltage level, wherein said switching frequency reduces according to the minimizing of described load, thereby has reduced handoff loss and power consumption under underload and the no-load condition.
7. discontinuous mode power factor correction controller according to claim 1, it is characterized in that wherein decaying to when being lower than described deboost when the described voltage level on the described power supply terminal of described controller, reduce described shut-in time delay to suppress the minimizing of switching frequency, therefore avoid the low voltage level in the described power supply terminal of described controller, wherein said switching frequency reduces according to the minimizing of described load, has therefore reduced handoff loss and power consumption under underload and the no-load condition.
8. discontinuous mode power factor correction controller according to claim 1 is characterized in that it comprises:
One constant current source is used to draw high the voltage level on the described detecting terminal of described controller;
One first comparator, it has a positive input terminal that is used to receive a first threshold voltage, and has negative input end of the described voltage level of the described detecting terminal that is used to receive described controller;
One first NAND gate is used to receive an output of described first comparator and the signal after anti-phase by described switching signal;
One the 3rd transistor, it is couple to described first NAND gate, when the described voltage level of described detecting terminal is detected as low signal, disconnects described the 3rd transistor via the output of described first NAND gate;
One delayed current source, it is couple to described the 3rd transistor and one the 3rd capacitor, opens described shut-in time delay of beginning via disconnecting described the 3rd transistor, and described delayed current source begins described the 3rd capacitor is charged;
One second comparator, it has negative input end that is used to receive one second threshold voltage, and has a positive input terminal of the voltage that is used to receive described the 3rd capacitor; And
One set-reset flip-floop is used to receive an output of described second comparator, and is higher than described second threshold voltage when the voltage level of described the 3rd capacitor, just enables described switching signal.
9. discontinuous mode power factor correction controller according to claim 8 is characterized in that more comprising:
One error amplifier, it has negative input end that is used to receive described feedback voltage, and has and be used to receive a positive input terminal of a reference voltage and export once the voltage that amplifies, and wherein said feedback voltage is the voltage on the described back coupling terminal;
One the 3rd comparator, it has a positive input terminal that is used to receive described voltage through amplifying, and have negative input end that is used to receive a serrated signal, a lead-out terminal of described the 3rd comparator is applied to an input terminal of described first NAND gate;
One second NAND gate, it has an input terminal of the described lead-out terminal that is used to receive described the 3rd comparator, and has another input terminal that is used to receive a pulse wave signal;
One the 4th comparator, it has negative input end of the voltage on the described current-sense terminal that is used to receive described controller, and has a positive input terminal that is used to receive an overcurrent threshold voltage; And
One NOR gate, it has an input terminal of exporting that is used to receive described second NAND gate, and have another input terminal that is used to receive from the inversion signal of a lead-out terminal of described the 4th comparator, the output of described NOR gate is applied to described set-reset flip-floop
Wherein when described voltage through amplifying was lower than one the 5th threshold voltage, the described shut-in time postponed correspondingly to increase, and described the 5th threshold voltage is the constant that defines the underload level,
When the described voltage level on the described power supply terminal of described controller decays to when being lower than a deboost, reduce described shut-in time delay to suppress the minimizing of switching frequency, therefore prevent the low voltage level in the described power supply terminal of described controller, wherein said switching frequency reduces according to the minimizing of described load, thereby has reduced handoff loss and power consumption under underload and the no-load condition.
10. discontinuous mode power factor correction controller according to claim 9, the circuit that it is characterized in that wherein being used to producing described serrated signal and pulse wave signal comprises:
One current source;
One the 4th capacitor, when described switching signal when being high, described current source begins described the 4th capacitor is charged and produces sawtooth waveform SAW, and when described switching signal when low, described the 4th capacitor discharge; And
One the 5th comparator, it has a positive input terminal that is used to receive the 4th threshold voltage and is used to receive negative input end of described serrated signal, and then exports described pulse wave signal.
11. a method of operation that is used for the zero current switching discontinuous mode power factor correction controller of discontinuous mode power factor correction converter is characterized in that described method of operation comprises:
When the line input voltage is applied to described power factor correction converter, start described controller by a feedback resistor and a parasitic diode of described power factor correction controller;
In case described power factor correction controller is enabled, just switch described feedback resistor, make it become the voltage divider of voltage feedback loop; And
One external resistor is provided, it is connected to described power factor correction controller to determine a maximum turn-on time of switching signal, therefore limit peak power output, wherein when stopping using described switching signal, before next switching cycle begins, the inductor current of described power factor correction converter is released to zero, to realize that zero current switches, wherein switch frequency in order to reduce one under the light-load conditions, before shut-in time postpones to be inserted in each switching cycle and begins, a supply voltage of described power factor correction controller with all be regarded as variable from the resulting feedback voltage of described voltage feedback loop.
12. the zero current that is used for the discontinuous mode power factor correction converter according to claim 11 switches the method for operation of discontinuous power factor correction controller, it is characterized in that, the wherein said shut-in time postpones to be modulated to the function of described feedback voltage and described supply voltage, wherein in a single day described feedback voltage reduces and is lower than a threshold voltage, the described shut-in time postpones just correspondingly to increase, wherein said threshold voltage is the constant that defines the underload level, when described supply voltage is lower than a deboost, reduce described shut-in time delay to suppress the minimizing of described switching frequency, therefore prevent low supply voltage, wherein said deboost defines the low supply voltage level, described switching frequency reduces according to the minimizing of described load, thereby has reduced handoff loss and power consumption under underload and the no-load condition.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2004/000361 WO2005101638A1 (en) | 2004-04-16 | 2004-04-16 | Discontinuous mode pfc controller having a power saving modulator and operation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1938932A CN1938932A (en) | 2007-03-28 |
| CN1938932B true CN1938932B (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2004800427478A Expired - Fee Related CN1938932B (en) | 2004-04-16 | 2004-04-16 | Discontinuous mode PFC controller with energy-saving modulator and its operating method |
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| CN (1) | CN1938932B (en) |
| WO (1) | WO2005101638A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1938932A (en) | 2007-03-28 |
| WO2005101638A1 (en) | 2005-10-27 |
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