CN114582742A - 多用途非线性半导体封装体装配线 - Google Patents
多用途非线性半导体封装体装配线 Download PDFInfo
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- CN114582742A CN114582742A CN202111665279.1A CN202111665279A CN114582742A CN 114582742 A CN114582742 A CN 114582742A CN 202111665279 A CN202111665279 A CN 202111665279A CN 114582742 A CN114582742 A CN 114582742A
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Abstract
一种生产封装半导体装置的方法包括提供第一封装衬底面板。提供第二封装衬底面板。第一和第二封装衬底面板使用控制机构移动通过包括多个封装体装配工具的装配线。第一类型封装半导体装置形成在第一封装衬底面板上,第二类型封装半导体装置形成在第二封装衬底面板上。第二类型封装半导体装置与第一类型封装半导体装置不同。控制机构以非线性方式使第一和第二封装衬底面板移动通过装配线。
Description
本申请是申请日为2017年10月09日、申请号为201710929897.X、发明名称为“多用途非线性半导体封装体装配线”的发明专利申请的分案申请。
技术领域
本申请涉及半导体封装,更尤其涉及高容量封装体装配线。
背景技术
半导体封装用于保护集成电路(例如微处理器、微控制器、ASIC装置、传感器、功率晶体管等),并且在集成电路与外部部件、例如印刷电路板之间提供电和热接口。通常,半导体封装体被设计成保护集成电路免受潜在的破坏性环境条件、例如极端温度变化、湿气、灰尘颗粒等。此外,半导体封装体包括在集成电路的端子与外部部件之间提供电接口的外部端子(例如引线、焊盘等)。
随着半导体工业的发展,已经开发出各种不同的封装体类型。开发的第一种封装体类型之一是所谓的TO(晶体管外形:transistor outline)封装体,所述TO封装体包封例如晶体管或二极管的单个半导体裸片,并且包括直接从包封部分延伸出的两个或三个引线。TO封装体之后的一种封装体类型是所谓的DIP(双列直插封装体:dual in-linepackage),它比TO封装体提供了更高的引线数和更多的I/O容量。DIP封装体之后的一种封装体类型是所谓的QFP(四方扁平封装体:quad-flat-package),由于在封装体的四侧都提供“鸥翼”型引线,因此QFP提供了高引线数。从那里,演化了所谓的表面贴装封装体。表面贴装封装体包括用平焊盘代替引线,因此减小了空间。表面贴装封装体的一个例子是BGA(球栅阵列:ball grid array),所述BGA具有位于封装体的底侧的焊料球格栅阵列,所述焊料球格栅阵列用于提供外部电端子。
迄今为止,存在大量可商购并广泛使用的标准封装体类型。这些封装体类型的例子包括DIP(双列直插封装体:dual in-line package)、LGA(接点格栅阵列:land gridarray)、MCM(多芯片模块:multi-chip module)、LCC(带引线的芯片载体:leaded chipcarrier)、PGA(引脚格栅阵列:pin grid array)、CFP(陶瓷扁平封装体:ceramic flatpack)、QFN(四方扁平无引线:quad flat no-leads)、TSOP(薄型小外形封装体:thinsmall-outline package)和WLB(晶片级球栅阵列:Wafer Level Ball Grid Array)。这些封装体的内部结构有很大的差异,并且用于制造这些封装体类型中的任何一种的工艺显著不同。布线技术可以变化(例如引线接合、焊料突起、薄膜附接等)。包封技术可以变化(例如传递模制成型法、压缩成型、层压等)。激励人们优选封装体类型和工艺技术的驱动因素包括成本、电性能、热性能、互连密度、系统集成容量和可靠性。通常,在产品的生命周期中,性能最初是最重要的考虑因素,但随着产品在其生命周期中逐步发展,成本成为主导因素。
降低封装体装配成本的一种方法是利用并行加工技术。并行加工是指在多个封装位点上同时进行相同的封装工艺(例如引线接合、裸片附接、包封等)的技术。该技术的一个例子涉及使用具有大量(例如10、20、50个等)相同的单元细胞的引线框架条,每个单元细胞具有期望封装体类型的引线结构。引线框架条被装载到各种封装工具(例如裸片附接工具、模制成型工具、引线修整工具等)中,并且封装体加工同时应用于引线框架条中的每个单元细胞。最终,单元引线框架被单个化并且产生了许多相同的封装体。
到目前为止,封装体装配线被构建以生产单个封装体类型(例如CFP、QFN、TSOP等)。每个封装体装配线都需要投资、规划、材料建造、流程设计、工具设备和专门仅生产一种类型的封装体的制造位置。这些因素导致每个封装体的成本增加。
发明内容
公开了一种生产封装半导体装置的方法。根据一个实施例,所述方法包括提供第一封装衬底面板。提供第二封装衬底面板。第一和第二封装衬底面板使用控制机构移动通过包括多个封装体装配工具的装配线。第一类型封装半导体装置形成在第一封装衬底面板上,第二类型封装半导体装置形成在第二封装衬底面板上。第二类型封装半导体装置与第一类型封装半导体装置不同。控制机构以非线性方式使第一和第二封装衬底面板移动通过装配线。
根据另一个实施例,所述方法包括提供第一和第二封装衬底面板,每个面板包括多个封装位点。提供包括被配置为对第一和第二面板中的每个封装位点执行封装体加工的多个加工工具的装配线。提供控制机构,其被配置为识别第一和第二封装衬底面板并且以非线性方式将第一和第二面板装载到装配线中的每个加工工具中。使用控制机构使第一面板移动通过装配线,以形成第一封装体类型封装体。使用控制机构使第二面板移动通过装配线,以形成与第一封装体类型不同的第二封装体类型封装体。控制机构将第一面板仅装载到装配线中生产第一封装体类型所需的那些加工工具中、将第二面板仅装载到装配线中生产第二封装体类型所需的那些加工工具中。
根据另一个实施例,所述方法包括提供多个封装衬底面板,每个面板具有相同的尺寸并且为至少24英寸×18英寸。提供具有与24英寸×18英寸面板兼容的多个加工工具的装配线。装配线中的第一组加工工具被配置为执行第一封装体类型的每个封装体加工步骤,并且装配线中的与第一组不同的第二组加工工具被配置为执行与第一封装体类型不同的第二封装体类型的每个封装体加工步骤。提供控制机构,其被配置为能识别装配线中的衬底面板并且将识别出的面板装载到第一组和第二组中的任何一个加工工具中。控制机构用于识别封装衬底面板并且确定识别出的面板包括第一封装体类型封装位点还是第二封装体类型封装位点,在识别出的面板包括第一封装体类型封装位点的情况下将识别出的面板装载到第一组中的一个加工工具中,并且在识别出的面板包括第二封装体类型封装位点的情况下将识别出的面板装载到第二组中的一个加工工具中。
附图说明
附图的元件不一定相对彼此成比例。相同的附图标记表示对应的相同部分。各种示出的实施例的特征可以组合,除非它们彼此排斥。实施例在附图中示出,并且在下面的描述中详细说明。
图1示出了根据一个实施例的线性装配线。
图2示出了根据一个实施例的非线性装配线。
图3示出了根据一个实施例的使用非线性封装体装配线来生产第一封装体类型半导体封装体的工艺流程。
图4示出了根据一个实施例的使用非线性封装体装配线来生产第二封装体类型半导体封装体的工艺流程。
图5包括图5A、5B和5C,示出了根据一个实施例的适配封装衬底面板的方法。图5A示出了适配用于第一封装体类型的封装衬底面板的方法,图5B示出了适配用于第二封装体类型的封装衬底面板的方法,图5C示出了适配用于第三封装体类型的封装衬底面板的方法。
图6示出了根据一个实施例的使用非线性封装体装配线来制造TSLP类型封装体的工艺流程。
图7示出了根据一个实施例的使用非线性封装体装配线来制造SS08类型封装体的工艺流程。
图8示出了根据另一实施例的使用非线性封装体装配线来制造SS08类型封装体的工艺流程。
图9示出了根据一个实施例的使用非线性封装体装配线来制造VQFN类型封装体的工艺流程。
图10示出了根据一个实施例的使用非线性封装体装配线来制造eWLB类型封装体的工艺流程。
图11示出了根据另一实施例的使用非线性封装体装配线来制造eWLB类型封装体的工艺流程。
图12包括图12A、12B和12C,示出了根据一个实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图13包括图13A、13B和13C,示出了根据一个实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图14包括图14A和14B,示出了根据一个实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图15包括图15A和15B,示出了根据一个实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图16包括图16A、16B和16C,示出了根据不同于参考图12-15描述的实施例的另一实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图17包括图17A、17B和17C,示出了根据不同于参考图12-15描述的实施例的另一实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图18示出了根据不同于参考图12-15描述的实施例的另一实施例的使用非线性封装体装配线来形成VQFN类型封装体的选定的工艺步骤。
图19示出了根据不同于参考图12-16描述的实施例和参考图16-18描述的实施例的另一实施例的使用非线性封装体装配线形成的VQFN封装体。
具体实施方式
本文描述的实施例包括同时以各种不同封装体类型(例如CFP、QFN、TSOP等)封装多种半导体装置的方法。这些封装体使用在制造过程中适于所需封装体类型的面板生产。所述面板的尺寸可非常大(例如18英寸×24英寸)。每个面板的封装位点的准确数量将随封装体类型和封装体尺寸而变化。以8平方毫米的封装体占用面积为例,这些非常大的面板中的一个可用于生产大约4,000个封装体。装配线中的每个封装体装配工具都与这些非常大尺寸的面板兼容,并且可以对这些面板上的每个封装位点执行封装体构造步骤。所述封装体装配工具的实例包括模制成型工具、引线接合机、层压机、喷射清洁工具、金属镀覆工具等。通过在装配线中使用非常大的面板尺寸,增加了并行化并且降低了每个封装体的成本。
根据本文描述的有利的实施例,非线性装配线与面板移动控制机构结合使用,以便同时对不同封装体类型执行必需的加工步骤。根据非线性加工技术,封装体批次(即,面板或面板组)不是以线性次序顺序地从一个封装体装配工具传送到下一个封装体装配工具来通过装配线。相反,与第一封装体类型(例如QFN)相关联的特定封装体批次移动通过与第一封装体类型相关联的所选的一组封装体装配工具。同时,与第二不同的封装体类型(例如WLB)相关联的第二封装体批次经过与第二封装体类型相关联的不同组的封装体装配工具,并且可以以不同的次序移动通过公共的加工工具。换句话说,非线性工艺能够基于封装体类型完全地改变加工步骤的次序并且跳过或添加加工步骤。这可以通过能够在每个加工步骤完成之后将一封装体批次移动到装配线中的任何一个加工工具的控制机构实现。控制机构识别每个批次,确定在所识别的批次中包含哪种封装体类型,并将所述批次装载到适当的加工工具(或适当的加工工具队列)中。以这种方式,控制机构控制封装体批次通过装配线的流动,并且确保每个批次仅放置在生产与这些批次相关联的封装体类型所必需的那些加工工具中。此外,控制机构可以通过监测加工工具的可用性和/或延迟时间并且基于负载平衡方案装载所述加工工具来优化系统产量。
参考图1,示出了根据一个实施例的传统的线性封装体装配线100。这种常规的装配线形式适用于各种常见的封装体类型(例如,MCM、LCC、PGA、CFP、QFN、TSOP等)中的任意一种。然而,这种传统的线性封装体装配线100通常只能生产这些封装体类型中的一种。也就是说,所述传统的线性封装体装配线100仅包括那种生产某种封装体类型的加工工具,并且物理上以生产这种封装体类型的方式布置。所述传统的线性封装体装配线100包括总共五个加工工具,即第一加工工具102、第二加工工具104、第三加工工具106、第四加工工具108和第五加工工具110。这些加工工具可以被配置为执行诸如引线接合、蚀刻、层压、注射成型、喷射清洁、电镀、蚀刻、引线修整、切割等封装步骤。对于引线框架式封装体,所述加工工具可以被配置为在每个引线框架中装载和加工具有多个单元引线框架的引线框架条。
传统的线性封装体装配线100是线性的,这意味着在通过所述加工工具之一在封装体批次之一上完成封装体加工步骤之后,所述封装体批次必须前往下游加工工具之一。因此,封装体批次流经加工工具的次序总是相同的。在这点上仅有的灵活性是可以跳过次序中的一个或两个以上步骤,并将所述封装体批次送往更下游的加工工具。这个原理通过图1中为两个不同封装体批次提供的两个工艺流示出。第一封装体批次112线性地流过装配线而直接从第一加工工具102到第二加工工具104,然后直接从第二加工工具104到第三加工工具106,然后直接从第三加工工具106到第四加工工具108,再然后直接从第四加工工具108到第五加工工具110。第二封装体批次114线性地流过装配线而直接从第一加工工具102到第二加工工具104,然后直接从第二加工工具104到第四加工工具108,再然后直接从第四加工工具108到第五加工工具110。因此,第二封装体批次114跳过了第三加工工具106。然而,第一和第二封装体批次112、114都在相同的线性方向上流过传统线性封装体装配线100的加工工具。
通常,在例如参考图1描述的示例性装配线100的线性装配线中,加工工具需要不同的时间量来执行它们相应的封装步骤。这在加工工具之间需要缓冲,并在工艺中产生降低产量的瓶颈。
参考图2,示出了根据一个实施例的非线性封装体装配线200。所述非线性封装体装配线200总共包括十五个加工工具,即第一加工工具202、第二加工工具204、第三加工工具206、第四加工工具208、第五加工工具210、第六加工工具212、第七加工工具214、第八加工工具216、第九加工工具218、第十加工工具220、第十一加工工具222、第十二加工工具224、第十三加工工具226、第十四加工工具228和第十五加工工具230。所述加工工具被分组成多簇,即第一簇250、第二簇260、第三簇270、第四簇280和第五簇290。每簇包括三个加工工具。这只是一个例子,加工工具的总数、簇的总数以及每簇中的加工工具数量可能会有所不同。
所述装配线200是非线性的,这意味着在封装体批次在加工工具中的一个中完成加工之后,所述封装体批次可以前往装配线200中的任何一个加工工具,包括之前已经用于这个封装体批次的任何加工工具。因此,与参考图1描述的线性封装体装配线100相比,可应用于特定封装体批次的潜在的加工步骤要高几个数量级。此外,两个不同的封装体批次可以同时地通过非线性装配线200并接收独有的封装体加工。例如,第一封装体批次可以通过装配线200并接收对于第一封装体类型(例如,VQFN、SON、TON等)来说独有的封装体加工,第二封装体批次可以通过装配线200并接收对于第二种封装体类型(例如,无引线DS、eWLB、WLB等)来说独有的封装体加工。一种封装体类型而不是其它封装体类型所需的多种加工步骤可以同时地在第一和第二封装体批次上执行。这在使用参考图1描述的传统的线性装配线时是不可能的。
所述非线性封装体装配线200包括控制机构232,所述控制机构232便于在制造中使各种封装体批次移动通过装配线200。控制机构232例如负责将封装体批次装载到非线性封装体装配线200中的各种加工工具中,在封装体加工完成之后从各种加工工具移除所述封装体批次,并且将正在制造的封装体批次中的每一个传送到正确的加工工具以用于后续加工。
所述控制机构232被配置为识别正在制造的封装体批次中的每一个。这可以通过在每个封装体批次上提供独有的标识符并且提供被配置为检测独有的标识符的相应机构来完成。例如,每个封装体批次可以包括条形码,并且控制机构232可以包括条形码检测装置。替代性地,多个条形码检测装置可以分布在整个装配线200上并且具有与控制机构232的通信连接(例如,无线或有线连接)。根据另一示例,每个封装体批次可以包括RFID发射器,并且控制机构232可以包括RFID接收器或连接到分布在整个装配线上的多个RFID接收器。
所述控制机构232被配置为使用每个封装体批次的识别信息来确定什么封装体类型与所识别的封装体批次相关联。例如,控制机构232可以确定所识别的封装体批次是否包括TSLP型封装体、SSO8型封装体、VQFN型封装体、扇出晶片级封装(例如eWLB)型封装体等。这可以使用将特定封装体批次的独有标识符与封装体类型相对应的查找表来完成。例如,查找表可以存储在控制机构232的存储器中。替代性地,封装体类型信息可以并入每个封装体批次的标识符中。
所述控制机构232可以在制造中的每个封装体批次的各种加工步骤中的任何一种或所有加工步骤中执行对所述封装体批次的识别。例如,控制机构232可以在非线性装配线200的每个加工工具的出口点处执行封装体识别。替代性地,当封装体批次通过非线性装配线200的中心核时,可以仅在每簇的出口点之后进行封装体识别。
所述控制机构232被配置为确定制造中的每个封装体批次已经完成的加工步骤的序列和仍然需要的加工步骤的序列。这可以使用存储在控制机构232的位于中心的存储器中的目录来完成,所述目录将每个批次与安排好的步骤列表相关联,并且指明这些步骤中的哪些步骤已经完成。替代性地,该信息中的一些或全部可以存储在封装体批次本身上。使用SS08封装体类型作为一个示例,控制机构232可以确定特定批次已经接收到加工步骤,包括层压、芯片附接、等离子体清洁、印刷和裸片附接。控制机构232可以确定这个特定批次仍然需要的加工步骤,包括(按此顺序)压缩成型、研磨、激光打标、松脱、铜蚀刻、层压、电镀、清洁和分离。基于该确定,控制机构232确定所需的下一个加工步骤是压缩成型,因此发送所述特定批次到压缩成型工具。一旦这个过程完成,控制机构232执行更新的识别和确定序列,并发送所述批次到执行研磨的工具(即,工艺中的下一个步骤)。该序列自己重复,直到制作完成。
所述控制机构232被配置为基于多个用户定义的目标优化非线性装配线200的产量。用户定义的目标的示例包括通过非线性装配线的每个封装体批次的平均加工时间、通过非线性装配线的优先封装体批次的子集的平均加工时间、每个加工工具在时间效率或功率效率方面的使用效率等。根据用户定义的目标,控制机制232可以确定最佳资源分配方案。所述最佳资源分配方案可以考虑各种因素,包括非线性装配线的当前状况,例如在制造中的封装体批次的数量、在制造中的封装体类型、装配线中各种加工工具的可用性、每个加工步骤所需的时间等。用户定义的目标和最佳资源分配方案可以由操作者手动输入,可以由存储在控制机构232的存储器中的软件来实现,或者可以由并入控制机构232的一次性可编程硬件来实现。
根据一个实施例,所述非线性封装体装配线200被配置为使用封装衬底面板对制造中的每个封装体批次执行并行加工。根据这项技术,一种标准尺寸的面板可以用作用于封装体形成的衬底。这种标准尺寸的面板通过非线性封装体装配线200。每个标准尺寸的面板包括多个封装位点。所述非线性装配线中的每个加工工具与面板型式兼容,使得加工工具可以装载面板,在所述面板的每个封装位点上执行它们各自的封装体加工步骤(引线接合、注射成型、金属蚀刻等),并在加工完成时使面板可用于传输。面板可以非常大,因此可以容纳大量的封装体。例如,根据一个实施例,面板是24英寸×18英寸。其它尺寸也是可能的,并且非线性封装体装配线200可以被配置为容纳两种或更多种不同尺寸的面板。所述面板可以包括电绝缘材料、导电材料或两者。根据一个实施例,所述面板包括铝层、聚合物层、铜层。这些面板的示例包括标准PCB制作面板。
这里描述的封装体批次是指同时接收相同加工步骤的一组装置。这些封装体批次可以使用由控制机构232控制的匣盒和轨道系统在整个非线性封装体装配线200中传输。一个封装体批次可以是单个面板。替代性地,一个封装体批次可以包括在每个加工工具处按顺序加工并在多个匣盒中的一个中一起传输的多个面板。
参考图3,示出了使用非线性封装体装配线200生产第一封装体类型半导体封装体的第一工艺流程。所述第一封装体类型可以是各种集成电路封装体类型中的任何一种,包括VQFN、SON、TON、无引线分立封装体、扇出WLB、扇入WLB、嵌入式裸片、ATSLP、TSNP、BGA、倒装芯片封装体类型或任何其它封装体类型。根据第一工艺流程,将空面板的第一封装体批次302提供给控制机构232。控制机构232移动第一封装体批次302通过非线性装配线200,使得第一封装体批次302由选定的一组加工工具以特定的顺序加工。更具体地,控制机构232移动第一封装体批次302通过非线性装配线200,使得第一封装体批次302由第一加工工具202、第二加工工具204、第三加工工具206、第四加工工具208、第五加工工具210、第八加工工具216、第九加工工具218、第十二加工工具224、第十三加工工具226和第十五加工工具230顺序地加工。这个选定的组和顺序对应于形成第一封装体类型封装体所需的工艺流程。
参考图4,示出了使用非线性封装体装配线200生产第二封装体类型半导体封装体的第二工艺流程。所述第二封装体类型不同于第一封装体类型,且可以是各种集成电路封装体类型中的任何一种,包括VQFN、SON、TON、无引线分立封装体、扇出WLB、扇入WLB、嵌入式裸片、ATSLP、TSNP、BGA、倒装芯片封装体类型或任何其它封装体类型。根据第二工艺流程,将空面板的第二封装体批次304提供给控制机构232。控制机构232移动第二封装体批次304通过非线性封装体装配线200,使得第二封装体批次304由选定的一组加工工具以特定顺序加工。更具体地,控制机构232移动第二封装体批次304通过非线性装配线,使得第二封装体批次304由第一加工工具202、第二加工工具204、第三加工工具206、第七加工工具214、第八加工工具216、第四加工工具208、第六加工工具212、第十加工工具220、第十一加工工具222、第十四加工工具228和第十五加工工具230顺序地加工。这个选定的组和顺序对应于形成第二封装体类型封装体所需的工艺流程。图4的第二工艺流程可以与图3的第一工艺流程同时进行。
一般来说,非线性封装体装配线200的加工工具可以是被配置为执行上面列出的加工步骤中的一个或多个的各种加工工具中的任何一种。加工工具的实例包括模制成型工具、激光打孔工具、机械打孔工具、溅射工具、引线接合机、层压机、喷射清洁工具、金属镀覆工具和化学蚀刻工具。
根据一个实施例,非线性封装体装配线200被组织成使得簇对应于封装体加工步骤的类或子类。例如,第一簇250可以被配置为执行面板适配。为此,第一簇250可以包括粘合剂施加工具、金属蚀刻工具和电镀工具。第二簇260可以被配置为执行第一级互连(即,裸片和封装体之间的连接)或第二级互连(形成封装体级端子)。为此,第二簇260可以包括引线接合工具、焊料球形成工具、焊料回流工具和夹附接工具。第三簇270可以被配置为执行裸片包封。为此,第三簇270可以包括压缩成型工具、传递成型工具、注塑成型工具和层压工具。第四簇280可以被配置为执行湿法化学法。为此,第四簇280可以包括电镀工具、金属蚀刻工具、光刻胶工具和等离子体清洁工具。第五簇290可以被配置为执行封装体分离。为此,第五簇290可以包括切割工具和引线修整工具。
参考图5,示出了适配封装衬底面板500的方法。可以使用非线性封装体装配线200以前述方式执行该面板适配。图5A描绘了用于第一封装体类型的适配封装衬底面板500的方法,图5B描绘了用于第二封装体类型的适配封装衬底面板500方法,图5C描绘了用于第三封装体类型的适配封装衬底面板500的方法,其中,第一、第二和第三封装体类型各自彼此不同。根据一个实施例,第一封装体类型是扇出晶片级封装体(FO-WLB,例如eWLB)封装体类型,第二封装体类型是TSLP封装体类型,第三封装体类型是VQFN封装体类型。对于第一封装体类型,粘合剂层502被施加到面板500的顶表面。裸片可以直接附接到粘合剂层502,并且随后可以执行后续加工。对于第二封装体类型,电绝缘体504被形成在面板500的顶表面上。随后,引线框架506设置在电绝缘体504上。引线框架506可以单独制造。对于第三封装体类型,金属层508形成在面板500的顶表面上。金属层508可以预先形成在面板500上而具有一定厚度,例如12μm、17.5μm、35μm等。可以使用添加或消减工艺来实现期望的最终局部不同的厚度(例如半蚀刻)。随后,可以结构化金属层508,以提供具有多个裸片焊盘的期望的引线框架结构。
参考图6-11,示出了使用非线性封装体装配线200形成各种封装体类型的工艺流程。每个工艺流程在至少一个加工步骤和/或加工步骤的顺序方面彼此不同。然而,每个封装体类型的工艺流程遵循相同的基本顺序:(1)衬底/载体适配;(2)裸片附接;(3)互连/分离。根据一个实施例,根据这些类别之一对非线性封装体装配线200的簇进行分组。例如,一个或两个以上的簇可以包括用于衬底/载体适配的所有必需的工具,一个或两个以上的簇可以包括用于裸片附接的所有必需的工具,一个或两个以上的簇可以包括用于互连的所有必需的工具。可以在装配线200中提供具有相同加工工具的两个或更多个簇,以便增加产量和能够同时进行共同的加工步骤。
参考图6,示出了根据一个实施例的使用非线性封装体装配线200制造TSLP类型封装体的工艺流程。根据所述工艺流程,衬底/载体适配包括两个层压步骤602、604,接着是光刻步骤606,接着是化学清洁步骤608,接着是Sn/Tn镀覆步骤610,接着是化学抗蚀剂去除步骤612,然后是粘合剂施加步骤。裸片附接包括拾取并将半导体裸片放置在封装位点上616,接着是烘箱烘烤618。互连/分离包括引线接合620,接着是压缩成型622,接着是批号激光标记624,接着是金属蚀刻626,接着是非电式Ni/Au镀覆628,然后对封装体进行切割630。
参考图7,示出了根据一个实施例的使用非线性封装体装配线200制造SSO8类型封装体的工艺流程。在这个实施例中,例如以参照图5B描述的方式使用外部提供的引线框架。根据所述工艺流程,衬底/载体适配包括层压步骤702,接着将引线框架附接/放置在封装衬底面板上704,接着是等离子体清洁步骤706。裸片附接包括在引线框架上印刷焊料球708,接着拾取并将半导体裸片放置在引线框架的封装位点上710。互连/分离包括拾取和放置封装体引线712,接着是焊料回流714,接着压缩成型716,接着是研磨718,接着是批号激光标记720,接着是剥离翘曲调整722,接着是铜蚀刻724,接着是层压726,接着是非电式Sn镀覆728,接着是化学清洁730,然后是对封装体进行切割732。
参考图8,示出了使用非线性封装体装配线200制造SSO8类型封装体的工艺流程。在这个实施例中,作为封装体适配步骤的一部分,引线框架例如以参照图5C描述的方式直接形成在封装面板的导电层上。根据所述工艺流程,衬底/载体适配包括层压步骤802,然后对封装面板的导电层应用光刻804,接着是封装面板的导电层的化学显影/蚀刻和光刻胶剥除806,接着是等离子体清洁步骤808。裸片附接包括在引线框架上印刷焊料球810,接着是拾取并将半导体裸片放置在引线框架的封装位点上812。互连/分离包括拾取和放置封装体引线814,接着是焊料回流816,接着是压缩成型818,接着进行研磨820,接着是批号激光标记822,接着是剥离翘曲调整824,接着是铜蚀刻826,接着是层压828,接着是非电式Sn镀覆830,接着是化学清洁832,然后是对封装体进行切割834。
参考图9,示出了根据一个实施例的使用非线性封装体装配线200制造VQFN类型封装体的工艺流程。在这个实施例中,作为封装体适配步骤的一部分,引线框架例如以参照图5C描述的方式直接形成在封装面板的导电层上。根据所述工艺流程,衬底/载体适配包括层压步骤902,然后对封装面板的导电层应用光刻904,接着进行封装面板的导电层的化学显影/蚀刻和光刻胶剥除906,接着进行等离子体清洁步骤908,接着进行印刷步骤910。裸片附接包括拾取并将半导体裸片放置在引线框架的封装位点上912,接着是烘箱烘烤914。互连/分离包括引线接合或第一级互连916,接着是压缩成型918,接着是批号激光标记920,接着进行金属蚀刻922,接着进行等离子体清洁924,接着进行部分封装体分离926,接着进行进一步金属蚀刻928,接着是非电式SN镀覆930,接着进行水清洁932,然后完成封装体分离934。
参考图10,示出了根据一个实施例的使用非线性封装体装配线200制造扇出晶片级封装体类型封装体(基于eWLB封装体)的工艺流程。根据所述工艺流程,衬底/载体适配包括层压步骤1002。裸片附接包括拾取和放置半导体裸片1004,接着是箔退火步骤1006。互连/分离包括压缩成型1008,接着是批号激光标记1010,接着进行剥离翘曲调整1012,接着是边缘圆滑1014,接着进行等离子体清洁1016,接着是烘箱烘烤1018,接着进行裸片检查1020,接着进行层压1024,接着进行激光打孔1026,接着进行激光打孔1028,接着是剥离1030,接着进行等离子体清洁1032,接着进行聚合物种子浸渍1034,接着进行层压1036,接着进行光刻曝光1038,接着是显影1040,接着进行铜镀覆1042,接着进行化学加工(包括光刻胶剥除、种子层蚀刻和铜粗糙化1044),接着进行层压1048,接着进行激光打孔1050,接着进行化学加工(包括清洁和种子层蚀刻1052),接着进行焊料球印刷1054,接着是焊料回流1056,然后进行封装体分离1058。
参考图11,示出了根据另一实施例的使用非线性封装体装配线200制造扇出晶片级封装体类型封装体(基于eWLB封装体)的工艺流程。根据所述工艺流程,衬底/载体适配包括层压步骤1102。裸片附接包括拾取和放置半导体裸片1104,接着是箔退火步骤1106。互连/分离包括压缩成型1108,接着是批号激光标记1110,接着进行剥离翘曲调整1112,接着进行边缘圆滑1114,接着进行等离子体清洁1116,接着进行烘箱烘烤1118,接着进行裸片检查1120,接着进行层压1112,接着进行激光打孔1124,接着进行等离子体清洁1126,接着进行TiW和Cu溅射1128,接着进行层压1130,接着进行光刻1132,接着进行显影1134,接着进行铜镀覆1136,接着进行化学加工(包括光刻胶剥除、种子层蚀刻和铜粗糙化1138),接着进行层压1140,接着进行激光打孔1142,接着进行化学加工(包括清洁和种子层蚀刻1144),接着进行焊料球印刷1146,接着进行焊料回流1148,接着进行封装体分离1150。
参考图12-15,示出了根据一个实施例的VQFN类型封装体形成工艺的剖视视图。所述VQFN类型封装体使用本文所述的非线性封装体装配线200形成。
参考图12A,提供了封装衬底面板1200。封装衬底面板1200包括铝板1202、聚合物层1204和薄铜层1206。聚合物层1204可以是模制化合物或多层材料。薄铜层1206可以具有诸如12μm、17.5μm、35μm等的不同的厚度。
参考图12B,结构化铜层1208在所述薄铜层之上形成在封装衬底面板上。结构化铜层1028可以通过掩模、电镀和蚀刻步骤形成。铜层被结构化成包括裸片焊盘1210和接合焊盘1212。根据一个实施例,结构化铜层的裸片焊盘1210比邻近的接合焊盘1212厚。
参考图12C,裸片1214附接到裸片焊盘1210。这可以根据各种技术(包括焊接、烧结、胶合、压力接合等)中的任何一种来完成。
参考图13A,在裸片1214和接合焊盘1212之间形成电连接1216(即第一级互连)。这可以根据各种技术(包括引线接合、夹附接或两者的混合)中的任何一种来完成。在非常大尺寸的面板、例如18英寸×24英寸或更大的情况下,引线接合机可能没有足够大的工作区域来完成面板上每个封装体的引线接合。在这种情况下,引线接合可以通过对面板上的一半的封装位点执行引线接合、旋转面板、然后对面板上的另一半的封装位点执行引线接合来完成。
参考图13B,执行包覆成型工艺。根据这个工艺,裸片1214和电连接1216被电绝缘的模制化合物1218、例如热固性塑料包封。可以使用压缩成型或注射成型技术。
参考图13C,去除了封装衬底面板1200的多个部分。具体地,去除了铝板1202和聚合物层1204。例如,这可以通过湿化学蚀刻来完成。
参考图14A,去除了薄铜层1206。例如,这可以使用各向同性蚀刻技术来完成。
参考图14B,将局部切割/分离工艺应用于装置的下侧。具体地,凹槽1220形成在装置的下侧。例如,这可以通过刀片切割或激光打孔来完成。凹槽1220至少延伸穿过结构化铜层1210,以到达模制化合物1218。
参考图15A,可焊接的贵金属层1222形成在结构化铜层上。根据一个实施例,可焊接的贵金属层1222通过非电式镀覆形成。非电式镀覆可以是诸如Sn或SnAG的锡基镀覆。所述镀覆形成在金属层1208的暴露的铜部分上、具体地是形成在裸片焊盘1210和接合焊盘1212的下侧以及接合焊盘1212的设置在凹槽1120内的内侧上。
参考图15B,执行完全的封装体分离工艺。所述封装体沿着凹槽分离。例如,这可以通过刀片切割来完成。
上述实施例中的部分切割/分离工艺和非电式镀覆工艺使得能够使用非线性封装体装配线200生产VQFN类型封装体。在封装衬底面板1200已经通过图14A的步骤去除之后,裸片焊盘1210和接合焊盘1212完全或部分地嵌入在模制化合物1218内。需要进一步加工,以使这些第二级互连点可焊接并且符合VQFN类型封装体的引线设计。通过形成延伸穿过接合焊盘1212的凹槽1220,暴露出接合焊盘1212的垂直于封装体的下侧的侧面。这些侧面被电镀,以在封装体的角部处形成封装体级端子。此外,裸片焊盘1210的下侧被电镀,以形成与裸片1214的下侧连接的连接端子。
参考图16-18,示出了根据另一个实施例的VQFN类型封装体形成工艺的剖视图。VQFN类型封装体可以使用非线性封装体装配线200形成。
参考图16A,提供了封装衬底面板1600。封装衬底面板1600包括铝板1602、聚合物层1604和薄铜层1606。聚合物层1604可以是模制化合物或多层材料。薄铜层1606可以具有不同的厚度,包括12μm,17.5μm,35μm等。
参考图16B,第二级金属化层1608形成在铜层1606上。例如,第二级金属化层1608可以通过溅射、电镀和蚀刻步骤形成。第二级金属化层1608和铜层1606都被结构化,以形成裸片焊盘1610和多个接合焊盘1612。根据一个实施例,裸片焊盘1610比相邻的接合焊盘1612厚。例如,铜层1606和第二级金属化层1608可以通过掩模、电镀和蚀刻步骤被结构化。
参考图16C,裸片1614附接到裸片焊盘1610。这可以根据各种技术(包括焊接、烧结、胶合、压力接合等)中的任何一种来完成。
参考图17A,在裸片1614与接合焊盘1612之间形成电连接1616、即第一级互连。这可以根据各种技术(包括引线接合、夹附接或两者的混合)中的任何一种来完成。在非常大尺寸的面板、例如18英寸×24英寸或更大的情况下,所述引线接合机可能没有足够大的工作区域来完成面板上的每个封装体的引线接合。在这种情况下,引线接合可以通过对面板上的一半的封装位点执行引线接合、旋转面板、然后对面板上的另一半的封装位点执行引线接合来完成。
参考图17B,执行包覆成型工艺。根据该工艺,裸片1614和电连接1616被电绝缘的模制化合物1618包封。可以使用压缩成型或注射成型技术。
参考图17C,去除铝板1602。例如,这可以通过湿化学蚀刻来完成。
参考图18,去除聚合物层1604。例如,这可以通过湿化学蚀刻来完成。这样,裸片焊盘1610和接合焊盘1612嵌入在模制化合物1618中,但是在装置的下侧可以接近。可以例如通过非电式镀覆或印刷将最终涂层施加到裸片焊盘1610和接合焊盘1612。这样,可以获得一个完成的封装装置。
参考图19,示出了根据另一实施例的VQFN类型封装体。在该实施例中,除了以下之外,执行与参照图16-18所述相同的加工步骤。铜层1606选择得更厚些,例如35μm或更大。此外,铜层1606和第二级金属化层1608在图16和17中描述的裸片附接、引线接合和成型步骤之前未被结构化。相反,铜层1606和第二级金属化层1608在去除铝板1602和聚合物层1604之后被结构化。以这种方式,所述装置可以被配置成使得结构化金属层(即,裸片焊盘1610和接合焊盘1612)从模制化合物露出,如图19所示。
本文所使用的诸如“相同”、“相配”和“匹配”的术语意指相同、几乎相同或近似,所以,在不脱离本发明的精神的情况下可以想到一些合理的变化量。术语“恒定”表示不改变或变化,或者稍微改变或稍微变化,从而在不脱离本发明的精神的情况下可以想到一些合理的变化量。此外,诸如“第一”、“第二”等术语用于描述各种元件、区域、部分等,也不旨在限制。在整个说明书中,相同术语指代相同的元件。
诸如“之下”、“下方”、“下”、“之上”、“上”等之类的空间相对术语用于方便解释一个元件相对于第二元件的定位。这些术语旨在除图中示出的那些取向外还包括装置的不同取向。此外,诸如“第一”、“第二”等的术语也用于描述各种元件、区域、部分等,也不旨在限制。在整个说明书中,相同术语指代相同的元件。
本文所使用的术语“具有”、“含有”、“包含”、“包括”等是表示所述元件或特征存在的开放式术语,但是不排除附加元件或特征。冠词“一个”、“一种”和“所述”旨在包括复数和单数,除非上下文另有明确指出。
考虑到上述变化和应用的范围,应当理解,本发明不受前面描述的限制,也不受附图的限制。相反,本发明仅由所附权利要求及其法律意义上的等同替换限制。
Claims (14)
1.一种形成半导体封装体的方法,所述方法包括:
提供面板;
在所述面板的上表面上提供一个或多个金属层;
由所述一个或多个金属层形成裸片焊盘和接合焊盘,所述裸片焊盘与所述接合焊盘相邻并间隔开;
将裸片附接到裸片焊盘;
在所述裸片与所述接合焊盘之间形成电连接;
使用电绝缘的模制化合物包封所述裸片和所述电连接;
去除所述面板的多个部分;和
在包封所述裸片之后,使所述裸片焊盘和所述接合焊盘暴露。
2.根据权利要求1所述的方法,其中,所提供的面板包括金属板和设置在所述金属板上的聚合物层。
3.根据权利要求2所述的方法,其中,所提供的面板包括位于所述聚合物层上的第一金属化层和位于所述第一金属化层上的铜层,其中,形成所述裸片焊盘和所述接合焊盘包括结构化所述铜层,以在所述铜层中形成所述裸片焊盘和所述接合焊盘。
4.根据权利要求3所述的方法,其中,去除所述面板的多个部分包括去除所述金属板和所述聚合物层,使所述裸片焊盘和所述接合焊盘暴露包括在去除所述金属板和所述聚合物层之后去除所述第一金属化层,在去除所述第一金属化层之后,所述裸片焊盘的下侧和所述接合焊盘的下侧被暴露。
5.根据权利要求4所述的方法,其中,所述方法还包括:在使所述裸片焊盘和所述接合焊盘暴露之后,在所述裸片焊盘的下侧和所述接合焊盘的下侧上形成可焊接的贵金属层。
6.根据权利要求5所述的方法,其中,形成可焊接的贵金属层包括在所述裸片焊盘的下侧和所述接合焊盘的下侧上镀覆锡基的可焊接的贵金属层。
7.根据权利要求5所述的方法,其中,所述方法还包括:在使所述裸片焊盘和所述接合焊盘暴露之后,形成延伸穿过所述接合焊盘进入所述电绝缘的模制化合物中的凹槽,其中,形成在所述接合焊盘上的所述可焊接的贵金属层延伸到所述凹槽中。
8.根据权利要求7所述的方法,其中,沿着所述凹槽切割包封体,使得形成在所述接合焊盘上的可焊接的贵金属层沿着包封体的侧壁延伸。
9.根据权利要求2所述的方法,其中,提供所述一个或多个金属层包括:提供位于聚合物层上的第一金属化层和位于第一金属化层上的第二金属化层,形成所述裸片焊盘和所述接合焊盘包括结构化第一金属化层和第二金属化层中的每一个,使得裸片焊盘和接合焊盘均对应于第一金属化层和第二金属化层的结构化出的堆叠体。
10.根据权利要求9所述的方法,其中,所述第一金属化层和第二金属化层在包封所述裸片和所述电连接之前被结构化为形成所述裸片焊盘和所述接合焊盘。
11.根据权利要求10所述的方法,其中,包封所述裸片和所述电连接包括绕着所述裸片焊盘和所述接合焊盘包覆成型电绝缘的模制化合物,使得电绝缘的模制化合物达到聚合物层,其中,在使所述裸片焊盘和所述接合焊盘暴露之后,裸片焊盘的下侧和接合焊盘的下侧与电绝缘的模制化合物的外表面共面。
12.根据权利要求2所述的方法,其中,第一金属化层和第二金属层在包封所述裸片和所述电连接之后被结构化为形成所述裸片焊盘和所述接合焊盘。
13.根据权利要求12所述的方法,其中,去除面板的多个部分包括在包封所述裸片和所述电连接之后去除所述金属板和所述聚合物层,其中,所述第一金属化层和第二金属化层在去除所述金属板和聚合物层之后被结构化。
14.根据权利要求1所述的方法,其中,半导体封装体被形成为具有四方扁平无引线结构形式。
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