CN114550606A

CN114550606A - Display panel and display device

Info

Publication number: CN114550606A
Application number: CN202210186600.6A
Authority: CN
Inventors: 蔡敏; 夏志强; 马扬昭
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2022-05-27
Also published as: CN114937410B; CN114550608A; CN114944113A; CN114550604A; CN110874990B; CN110874990A; CN114550607A; CN114550605A; CN114937410A

Abstract

The embodiment of the application provides a display panel and a display device. The display panel comprises a display area, wherein the display area comprises a first display area, a transition area and a second display area, and the sub-pixel density of the first display area, the transition area and the second display area is gradually increased. The first display area comprises a plurality of first sub-pixels, and the first pixel circuits for driving the first sub-pixels are located in the transition area, so that the light transmission area of the first display area is increased. The first sub-pixel is electrically connected with the first pixel circuit through a connecting line. The first line segment, the second line segment and the third line segment belong to different connecting lines respectively, extend along a first direction and are arranged in sequence in a second direction. There is not the clearance between the first line segment that arranges in proper order and the second line segment and between second line segment and the third line segment, can promote the luminousness of first display area, improves the diffraction phenomenon when light pierces through first display area simultaneously, promotes optical property of optical device under the screen.

Description

Display panel and display device

The application is a divisional application with application date of 2019, 12 and 02, application number of 201911216232.X and invention creation name of 'a display panel and a display device'.

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of display technology, people not only require smooth use experience for electronic products, but also increasingly require visual experience, and the high screen ratio becomes the direction of current research. For electronic products, the arrangement of optical devices such as a front camera inevitably occupies a certain space, thereby affecting the screen ratio. In order to improve the screen occupation ratio and realize a full screen, researchers consider the implementation scheme of the optical device under the screen.

The optical device is arranged below the film layer of the display panel where the light-emitting device is located, namely the optical device is arranged in the display area. When the display is needed, the position of the optical device can be displayed normally; when the optical device is used, light penetrates through the display panel to the optical device and is finally utilized by the optical device. The optical device is arranged under the screen, light rays can be utilized by the optical device only by penetrating through a film layer structure of the display panel, and the imaging quality of the optical device under the screen is poor and the requirements of users are difficult to meet when the current scheme for arranging the optical device under the screen is evaluated and found.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which are used for solving the technical problems that the imaging quality of an optical device under a screen is poor and the user requirement is difficult to meet in the prior art.

In order to solve the above technical problem, in a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a display area, the display area includes a first display area, a transition area and a second display area, the transition area at least semi-surrounds the first display area, the second display area at least semi-surrounds the transition area, the first display area includes a plurality of first sub-pixels, the transition area includes a plurality of transition sub-pixels, the second display area includes a plurality of second sub-pixels, a density of the plurality of first sub-pixels is less than a density of the plurality of transition sub-pixels, and a density of the plurality of transition sub-pixels is less than a density of the plurality of second sub-pixels;

the display area further comprises a plurality of pixel circuits and a plurality of connecting lines, the plurality of pixel circuits comprise a plurality of first pixel circuits located in the transition area, the first sub-pixels are electrically connected with the first pixels through the connecting lines, and the plurality of connecting lines comprise first connecting lines, second connecting lines and third connecting lines;

the plurality of first sub-pixels comprise a first sub-pixel, a second first sub-pixel and a third first sub-pixel, the first sub-pixel is electrically connected with the first pixel circuit through a first connecting line, the second first sub-pixel is electrically connected with the first pixel circuit through a second connecting line, and the third first sub-pixel is electrically connected with the first pixel circuit through a third connecting line; wherein,

the first connecting line comprises a first line segment, the second connecting line comprises a second line segment, the third connecting line comprises a third line segment, the first line segment, the second line segment and the third line segment extend along the first direction and are sequentially arranged in the second direction, and the second direction is perpendicular to the first direction;

the display panel comprises a substrate base plate, a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are positioned on the substrate base plate, a first connecting line and a third connecting line are positioned on the first metal layer, the second connecting line is positioned on the second metal layer, orthographic projections of the first line segment, the second line segment and the third line segment on the substrate base plate are respectively a first projection, a second projection and a third projection, the first projection and the second projection are overlapped or have a common boundary, and the second projection and the third projection are overlapped or have a common boundary.

Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a display device, including the display panel provided in any embodiment of the present application.

The display panel and the display device provided by the embodiment of the application have the following beneficial effects:

in the display panel provided in the embodiment of the present application, the display area includes a first display area, a transition area and a second display area, the sub-pixel density of the first display area is less than the sub-pixel density of the second display area, and the sub-pixel density of the transition area is between the sub-pixel density of the first display area and the sub-pixel density of the second display area. When displaying, the transition area can play a transition role, and the visual difference caused by the different sub-pixel densities of the first display area and the second display area is reduced. Meanwhile, after the density of the sub-pixels in the transition area is set to be smaller than that of the sub-pixels in the second display area, a space is reserved in the transition area, and at least part of first pixel circuits for driving the first sub-pixels can be arranged in the transition area, so that the area of a light-transmitting area of the first display area can be further improved. The application in the scheme of the optical device under the screen can increase the light quantity received by the optical device. In addition, when the connecting line electrically connected with the first sub-pixel and the first pixel is designed, three line segments extending along the same direction in at least three connecting lines are sequentially arranged, no gap exists between any two adjacent line segments in the arrangement direction, when light penetrates through the line segment arrangement region, a diffraction phenomenon cannot be generated due to the gap, the influence of the diffraction phenomenon on the optical performance of the optical device under the screen can be reduced, and the imaging effect of the optical device under the screen is improved. And the three line segments which are sequentially arranged are positioned on the two metal layers, namely the three line segments which are staggered are manufactured by adopting the two metal film layers, and the number of the film layers occupied by the three line segments in the display panel is small, so that the display panel is favorably thinned.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure;

FIG. 2 is an enlarged view of FIG. 1 at the location of region Q;

FIG. 3 is a schematic cross-sectional view taken at line A-A' of FIG. 2;

fig. 4 is a first schematic projection diagram of three line segments arranged in sequence on a substrate in the embodiment of the present application;

fig. 5 is a second schematic projection diagram of three line segments arranged in sequence on a substrate in the embodiment of the present application;

FIG. 6 is a partial schematic view of an alternative embodiment of a display panel provided in an embodiment of the present application;

FIG. 7 is a partial schematic view of another alternative embodiment of a display panel provided in an embodiment of the present application;

FIG. 8 is an enlarged view of an alternate embodiment at the location of area Q in FIG. 1;

FIG. 9 is an enlarged view of an alternate embodiment taken at the location of area Q in FIG. 1;

FIG. 10 is a schematic cross-sectional view taken at the location of line B-B' of FIG. 9;

FIG. 11 is an enlarged view of an alternate embodiment taken at the location of area Q in FIG. 1;

FIG. 12 is a schematic cross-sectional view taken at the location of line C-C' of FIG. 11;

FIG. 13 is an enlarged view of an alternate embodiment taken at the location of area Q in FIG. 1;

FIG. 14 is a partial schematic view of another alternative embodiment of a display panel provided in an embodiment of the present application;

FIG. 15 is an enlarged view of an alternate embodiment taken at the location of area Q in FIG. 1;

FIG. 16 is a diagram illustrating a structure of a film layer of an alternative embodiment of a display panel according to an embodiment of the present disclosure;

FIG. 17 is an enlarged view of an alternate embodiment at the location of area Q in FIG. 1;

FIG. 18 is a diagram illustrating a film structure of an alternative embodiment of a display panel according to an embodiment of the present disclosure;

FIG. 19 is an enlarged view of an alternate embodiment taken at the location of area Q in FIG. 1;

FIG. 20 is a partial schematic view of another alternative embodiment of a display panel provided in an embodiment of the present application;

FIG. 21 is a schematic diagram of another alternative embodiment of a display panel provided in an embodiment of the present application;

fig. 22 is a schematic view of a display device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure, and fig. 2 is an enlarged view of a region Q in fig. 1. Fig. 3 is a schematic cross-sectional view at the position of line a-a' in fig. 2. As shown in fig. 1, the display panel includes a display area AA, and the display area AA includes a first display area AA1, a transition area AAG and a second display area AA2, the transition area AAG at least half-surrounds the first display area AA1, and the second display area AA2 at least half-surrounds the transition area AAG. The shape of the first display area AA1 is shown schematically, and is not intended to limit the embodiments of the present application. Only the transition area AAG surrounds the first display area AA1, and the second display area AA2 surrounds the transition area AAG.

As shown in fig. 2, the first display area AA1 includes a plurality of first sub-pixels sp1, the transition area includes a plurality of transition sub-pixels spg, the second display area AA2 includes a plurality of second sub-pixels sp2, a density of the plurality of first sub-pixels sp1 is less than a density of the plurality of transition sub-pixels spg, and a density of the plurality of transition sub-pixels spg is less than a density of the plurality of second sub-pixels sp 2. The display panel provided by the embodiment of the application can be applied to an optical device scheme under a screen, the optical device is arranged below the first display area AA1, the position of the first display area can be normally displayed during displaying, and when the optical device is used, light can penetrate through the first display area and then is utilized by the optical device. Meanwhile, by setting the transition area AAG, the density of the sub-pixels in the transition area AAG is between the density of the sub-pixels in the first display area AA1 and the density of the sub-pixels in the second display area AA2, that is, the density of the sub-pixels gradually decreases in the direction from the second display area AA2 to the first display area AA 1. The transition region AAG can play a role of transition when displayed, and reduce the visual difference between the first display region AA1 and the second display region AA2 due to the difference in sub-pixel density. In addition, in the embodiment of the present application, the density of the transition sub-pixel spg is less than the density sp2 of the plurality of second sub-pixels, and a space can be reserved in the transition area AAG to set the first pixel circuit DL.

The display area further includes a plurality of pixel circuits including a plurality of first pixel circuits DL1 located in the transition area AAG, the first sub-pixels sp1 being electrically connected to the first pixel circuits DL1 through connection lines, and a plurality of connection lines including a first connection line L1, a second connection line L2, and a third connection line L3, as illustrated with continued reference to fig. 2; according to the embodiment of the application, at least part of the first pixel circuit DL1 electrically connected with the first sub-pixel sp1 is arranged in the transition area AAG, so that the area of the light-transmitting area of the first display area AA1 can be increased, and the light receiving amount of the optical device under the screen can be increased when the scheme is applied to the optical device under the screen. The first sub-pixel comprises an anode, a light emitting layer and a cathode which are sequentially stacked, the anode is electrically connected with one end of a connecting wire, and the other end of the connecting wire is electrically connected with the first pixel circuit, so that the first sub-pixel is electrically connected with the first pixel circuit.

The plurality of first sub-pixels includes a first sub-pixel 1sp1, a second first sub-pixel 2sp1, and a third first sub-pixel 3sp1, the first sub-pixel 1sp1 is electrically connected to the first pixel circuit DL1 through a first connection line L1, the second first sub-pixel 2sp1 is electrically connected to the first pixel circuit DL1 through a second connection line L2, and the third first sub-pixel 3sp1 is electrically connected to the first pixel circuit DL1 through a third connection line L3; wherein,

the first connecting line L1 includes a first line segment D1, the second connecting line L2 includes a second line segment D2, the third connecting line L3 includes a third line segment D3, the first line segment D1, the second line segment D2 and the third line segment D3 all extend along the first direction x and are sequentially arranged in the second direction y, and the second direction y is perpendicular to the first direction x; the first line segment D1 and the second connection line L2 including the second line segment D2 may be straight lines or curved lines, which is not limited in the present application. For clarity of illustrating the invention of the embodiment of the present application, only a part of the first pixel circuit DL1 is illustrated in fig. 2.

As shown in fig. 3, for a simplified illustration only, the display panel includes a substrate 101, and a first metal layer 102 and a second metal layer 103 located on the substrate 101, wherein a first connection line L1 and a third connection line L3 are located on the first metal layer 102, a second connection line L2 is located on the second metal layer 103, that is, a first segment D1 and a third segment D3 are located on the first metal layer 102, and a second segment D2 is located on the second metal layer 103. The display panel comprises a first line segment, a second line segment and a third line segment, wherein the three line segments are equivalently staggered in the direction vertical to the display panel and are positioned on two film layers of the display panel. Fig. 3 is only illustrated with the second metal layer 103 on the side of the first metal layer 102 close to the base substrate 101. In fact, other film structures are still present between the substrate 101 and the second metal layer 103, which are only schematically illustrated, and the complete film structure of the display panel is not shown. In another embodiment, the second metal layer may also be located on a side of the first metal layer remote from the substrate base plate.

Orthographic projections of the first line segment D1, the second line segment D2 and the third line segment D3 on the substrate are a first projection Y1, a second projection Y2 and a third projection Y3 respectively, wherein the first projection Y1 and the second projection Y2 overlap or have a common boundary, and the second projection Y2 and the third projection Y3 overlap or have a common boundary.

Fig. 4 is a first schematic view of projections of three line segments arranged in sequence on a substrate in this embodiment, and fig. 5 is a second schematic view of projections of three line segments arranged in sequence on a substrate in this embodiment. As shown in fig. 4, the first projection Y1 overlaps the second projection Y2, and the second projection Y2 overlaps the third projection Y3. As shown in fig. 5, the first projection Y1 has a common boundary with the second projection Y2, and the second projection Y2 and the third projection Y3 have a common boundary. Optionally, the first projection and the second projection may overlap, and the second projection and the third projection have a common boundary. Or the first projection and the second projection have a common boundary, and the second projection and the third projection overlap. Which are not illustrated in the drawings.

As can be seen from the projection diagrams illustrated in fig. 4 and 5, there is no gap between the first projection Y1 and the second projection Y2, and between the second projection Y2 and the third projection Y3. That is, as illustrated in fig. 3, there is no gap between two adjacent line segments in the second direction y in which the line segments are arranged. When the scheme is applied to the optical device under the screen, when light penetrates through the areas where the three line segments are located, the diffraction phenomenon cannot be generated due to gaps among the line segments. And among the three line segments arranged in sequence, two line segments which are not adjacent in the arrangement direction are positioned on the same film layer, namely, two layers of metal are adopted to realize the manufacture of the three connecting lines, and the parts (namely, a first line segment, a second line segment and a third line segment) which extend along the same direction and are arranged in sequence along the other direction in the three connecting lines can be ensured to be insulated from each other.

The first metal layer and the second metal layer for disposing the connection line in the embodiment of the present application may be original film layers in the display panel, or may also be newly added film layers in the panel, and the position of the film layer where the connection line is located will be described in the following specific embodiments.

In an embodiment, fig. 6 is a partial schematic view of an alternative implementation manner of a display panel provided in an embodiment of the present application. As shown in fig. 6, the first display area AA1 and the transition area AAG have a virtual boundary BJ therebetween, and the first pixel circuits DL1 are arranged along the virtual boundary. In this embodiment, the first pixel circuits DL1 are arranged along the virtual boundary BJ, and the first pixel circuit DL1 is closer to the first display area AA1, so that the length of the connection line (shown schematically) can be correspondingly shortened, and the connection between the first sub-pixel sp1 and the first pixel circuit DL1 can be realized without manufacturing a complicated pull-out wire during manufacturing. And as illustrated in fig. 6, one circle of the first pixel circuits DL1 may be disposed along the virtual boundary BJ, or two circles of the first pixel circuits may be disposed, so that the first pixel circuits may be uniformly dispersed outside the first display area, and when the connecting lines are formed, the connecting lines may be formed to be uniform, which radiate from the first display area, and is beneficial to achieving uniformity of light transmission in the first display area. The shape of the virtual boundary BJ in fig. 6 is only schematically illustrated, and the number of the first sub-pixels sp1 in the actual first display area AA1 is very large, which is only schematically illustrated in the figure.

Further, in an embodiment, as shown in fig. 7, fig. 7 is a partial schematic view of another alternative implementation of the display panel provided in the embodiment of the present application. A virtual boundary BJ is provided between the first display area AA1 and a transition area (an area surrounding the first display area AA1, not shown); the plurality of first sub-pixels sp1 includes an edge first sub-pixel sp1B adjacent to the virtual boundary BJ, and the plurality of first pixel circuits DL1 includes an edge first pixel circuit DL1B adjacent to the virtual boundary BJ; the edge first sub-pixel sp1B is electrically connected to the edge first pixel circuit sp1B via a connection line L. The first edge sub-pixel is close to the first edge pixel circuit, the first edge sub-pixel is electrically connected with the first edge pixel circuit, and the connecting line is short in length. When the first pixel circuit for driving the first sub-pixel is arranged in the transition area, the length and the position of the connecting line can be reasonably designed according to the shape of the first display area and the specific position of the first sub-pixel in the first display area, so as to ensure that the area occupied by the connecting line is minimum.

With continued reference to FIG. 7, the first display area AA1 has a virtual boundary BJ between it and the transition area; the plurality of first sub-pixels includes an eighth first sub-pixel 8sp1 and a ninth first sub-pixel 9sp1, the eighth first sub-pixel 8sp1 being located on a side of the ninth first sub-pixel 9sp1 away from the virtual boundary BJ; the plurality of connection lines include an eighth connection line L8 and a ninth connection line L9; the eighth first sub-pixel 8sp1 is electrically connected to the first pixel circuit DL1 through an eighth connection line L8, and the ninth first sub-pixel 9sp1 is electrically connected to the first pixel circuit DL1 through a ninth connection line L9; the eighth connecting line L8 includes an eighth line segment D8 extending along the first direction x, the ninth connecting line L9 includes a ninth line segment D9 extending along the first direction x, and in the direction perpendicular to the display panel, the eighth line segment D8 and the ninth line segment D9 overlap, fig. 7 is a schematic top view diagram, the direction of the top view is the same as the direction perpendicular to the display panel, and it can be seen from fig. 7 that the eighth line segment D8 and the ninth line segment D9 overlap, that is, there is no gap between the eighth line segment D8 and the ninth line segment D9. The ninth connecting line L9 is located on a side of the eighth connecting line L8 away from the substrate base board, that is, the ninth connecting line L9 is disposed above the eighth connecting line L8. The film structure of the panel is not illustrated in this embodiment, but it can be seen that the eighth connecting line L8 passes through the area where the ninth first sub-pixel 9sp1 is located when the eighth connecting line L8 is connected to the first pixel circuit located in the transition region by being pulled out from the first display region AA 1. The ninth connecting line is disposed above the eighth connecting line. It is ensured that the eighth connecting line is not cross-shorted with the ninth connecting line when it is pulled out from the first display area while passing through the position where the ninth first sub-pixel 9sp1 is located.

In one example, FIG. 8 is an enlarged view of an alternative embodiment at the location of region Q in FIG. 1. As shown in fig. 8, the plurality of pixel circuits further includes a plurality of transition pixel circuits DLg and a plurality of second pixel circuits DL2, the plurality of second pixel circuits DL2 are located in the second display area AA2, and the second pixel circuits DL2 are electrically connected to the second sub-pixels sp2, the plurality of transition pixel circuits DLg are located in the transition area AAG, and the transition pixel circuits DLg are electrically connected to the transition sub-pixels spg. The second display area AA2 is a conventional display area, and the second pixel circuit DL2 electrically connected to the second sub-pixel sp2 in a normal case as illustrated in the drawing is disposed below the second sub-pixel sp 2. In the same transition region AAG, the transition pixel circuit DLg electrically connected to the transition subpixel spg is correspondingly disposed below the transition subpixel spg. After the sub-pixel density of the transition area is reduced, the sub-pixel density of the transition area is reasonably designed, a space can be reserved in an interval area between adjacent transition pixel circuits to set the first pixel circuit, and at least part of the first pixel circuit driving the first sub-pixel is arranged in the transition area to increase the area of a light-transmitting area of the first display area. The optical device is applied to the scheme of the optical device under the screen, so that the light quantity received by the optical device can be increased, and the imaging quality of the optical device is improved.

In some alternative embodiments, FIG. 9 is an enlarged view of an alternative embodiment at the location of region Q in FIG. 1. Fig. 10 is a schematic cross-sectional view at the position of line B-B' in fig. 9. Referring to fig. 9 and 10, the plurality of first sub-pixels includes a fourth first sub-pixel 4sp1, the plurality of connection lines further includes a fourth connection line L4, the fourth connection line is located on the second metal layer 103, and the fourth first sub-pixel 4sp1 is electrically connected to the first pixel circuit DL1 through the fourth connection line L4.

The fourth connection line L4 includes a fourth line segment D4, the fourth line segment D4 extending in the first direction x, and the fourth line segment D4 located on the second metal layer 103. The orthographic projection of the fourth line segment D4 on the substrate base plate is a fourth projection, wherein the fourth projection and the third projection overlap or have a common boundary. For the understanding that the projections overlap or have a common boundary, reference is made to the corresponding description of fig. 4 and 5 above, which are not illustrated in the drawings. In fig. 10, the second metal layer 103 is only schematically shown on the side of the first metal layer 102 away from the base substrate 101. In practice, there are other film structures between the first metal layer 102 and the substrate 101, which are only schematically illustrated.

In this embodiment, of the first segment D1, the second segment D2, the third segment D3, and the fourth segment D4 that are sequentially arranged in the second direction y, two non-adjacent segments are located in the same film layer, and four staggered segments are formed by two metal film layers. No gap is reserved between any two adjacent line segments in the arrangement direction, and the space occupied by the arrangement of the four line segments is small, so that the transmittance of the first display area is improved. Meanwhile, when light passes through the area where the line segments are arranged, the diffraction phenomenon cannot be generated due to line segment gaps, the influence of the diffraction phenomenon on the performance of the optical device is favorably improved, and the imaging quality of the optical device under the screen is improved.

In some alternative embodiments, FIG. 11 is an enlarged view of an alternative embodiment at the location of area Q in FIG. 1. Fig. 12 is a schematic cross-sectional view at the position of line C-C' of fig. 11. As shown in fig. 11, the plurality of first sub-pixels includes a fourth first sub-pixel 4sp1, the plurality of connection lines further includes a fourth connection line L4, and the fourth first sub-pixel 4sp1 is electrically connected to the first pixel circuit DL1 through the fourth connection line L4. The fourth connecting line L4 includes a fourth line segment D4, the fourth line segment D4 extends along the first direction x, an orthogonal projection of the fourth line segment D4 on the substrate base plate 101 is a fourth projection, the fourth projection overlaps with the first projection, and the fourth projection overlaps with the second projection; as shown in fig. 12, the display panel further includes a third metal layer 104 on the substrate base plate 101, the fourth connection line L4 is located on the third metal layer 104, and the fourth line segment D4 is located on the third metal layer 104. It can be understood that the line segment is orthographically projected onto the substrate base plate, and the projection direction is perpendicular to the display panel, that is, the projection direction is the direction e illustrated in the figure. In the figure, it can be seen that in the direction e, the fourth line segment D4 overlaps the first line segment D1, i.e. the fourth projection of the fourth line segment on the substrate base 101 overlaps the first projection of the first line segment D1 on the substrate base 101; the fourth line segment D4 overlaps the second line segment D2, i.e. the fourth projection of the fourth line segment on the substrate base 101 overlaps the second projection of the second line segment D2 on the substrate base 101. The relative positions of the metal layers in the figures are only schematically indicated. In the second direction y in which the line segments are arranged, there is no gap between the fourth line segment and the line segment adjacent to the fourth line segment, and as illustrated in the figure, the fourth line segment D4 can block light in an oblique direction, where the light in the oblique direction is also the light with a certain included angle between the propagation direction and the direction e, and can also be understood as the light with the propagation direction not perpendicular to the display panel. The fourth line segment can further shield the light which enters the first display area in the oblique direction, and the diffraction phenomenon that the light penetrates through the first display area can be further improved.

Further, FIG. 13 is an enlarged view of an alternative embodiment at the location of area Q in FIG. 1. As shown in fig. 13, the first sub-pixel 1sp1, the second first sub-pixel 2sp1, and the third first sub-pixel 3sp1 are arranged in this order in the first direction x. By providing a plurality of first sub-pixels arranged in the same direction, connection lines are formed to the transition regions in the arrangement direction thereof to be connected to the first pixel circuits. At least three line segments can be arranged, so that no gap is formed between two adjacent line segments, and the diffraction phenomenon that light penetrates through the first display area is improved. Simultaneously, can reduce the connecting wire and coil in first display area, reduce the space that the connecting wire occupied in first display area, promote the light-transmitting area of first demonstration, and then promote the luminousness of first display area.

Further, fig. 14 is a partial schematic view of another alternative implementation of a display panel provided in an embodiment of the present application. As shown in fig. 14, the plurality of first sub-pixels further includes a fifth first sub-pixel 5sp1, a sixth first sub-pixel 6sp1, and a seventh first sub-pixel 7sp1 arranged in the second direction y; the plurality of connecting lines comprise a fifth connecting line L5, a sixth connecting line L6 and a seventh connecting line L7, the fifth connecting line L5 and the seventh connecting line L7 are positioned on the first metal layer, and the sixth connecting line L6 is positioned on the second metal layer;

the fifth first sub-pixel 5sp1 is electrically connected to the first pixel circuit DL1 through a fifth connection line L5, the sixth first sub-pixel 6sp1 is electrically connected to the first pixel circuit DL1 through a sixth connection line L6, and the seventh first sub-pixel 7sp1 is electrically connected to the first pixel circuit DL1 through a seventh connection line L7; wherein,

the fifth connecting line comprises a fifth line segment, the fifth connecting line comprises a sixth line segment, the seventh connecting line comprises a seventh line segment, and the fifth line segment, the sixth line segment and the seventh line segment extend along the second direction and are sequentially arranged in the first direction; orthographic projections of the fifth line segment, the sixth line segment and the seventh line segment on the substrate base plate are respectively a fifth projection, a sixth projection and a seventh projection, wherein the fifth projection and the sixth projection are overlapped or have a common boundary,

and the sixth projection and the seventh projection overlap or have a common boundary. The arrangement of the fifth line segment, the sixth line segment and the seventh line segment may be understood by referring to the arrangement of the first line segment, the second line segment and the third line segment in fig. 2 and fig. 3, and details are not described herein again. The fifth line segment, the sixth line segment and the seventh line segment are arranged in an overlapping mode, no gap exists between every two adjacent line segments, the phenomenon that light penetrates through the area where the line segments are located cannot be caused by diffraction due to the gaps when the light penetrates through the area where the line segments are located is avoided, and the phenomenon that the light penetrates through the first display area is avoided.

This embodiment makes the connection line to be connected to not only the first pixel circuit in the transition region in the first direction but also the first pixel circuit in the transition region in the second direction within the first display region. Can be through the outside back with the even dispersion of first pixel circuit in first display area, can make by the even connecting wire of first display area external radiation when refabricating the connecting wire, be favorable to realizing the printing opacity's in the first display area homogeneity.

In the embodiment of the present invention, the connection line may be made by using a metal layer newly added in the panel, the array layer is made on the substrate, after the array layer is made, the first metal layer and the second metal layer are correspondingly made, and the connection line is made on the first metal layer and the second metal layer, so as to realize the electrical connection between the first sub-pixel and the first pixel circuit located in the transition region.

In some alternative embodiments, the connection lines may also be formed by multiplexing existing film layers of the display panel, and when the extending direction of the connection lines is the same as the extending direction of the scan lines or the extending direction of the data lines, different arrangement modes are required.

In an embodiment, the display area further includes a plurality of scan lines extending along the first direction and a plurality of data lines extending along the second direction, as shown in fig. 15, and fig. 15 is an enlarged view of an alternative embodiment at a position of a region Q in fig. 1. Only one scan line S and one data line D within the transition area AAG are illustrated in the drawing, and when the connection line L is led from within the first display area AA1 to be connected to the first pixel circuit DL1 within the transition area AAG, the connection line L may overlap the data line D. The connection line L and the data line D are disposed at different layers in this embodiment.

Fig. 16 is a film structure diagram of an alternative implementation manner of the display panel provided in the embodiment of the present application, in which only one transistor T and a pixel capacitor of a pixel circuit are illustrated. The transistor includes an active layer w, a gate electrode g, a source electrode s, and a drain electrode d. The pixel capacitor comprises a first polar plate B1 and a second polar plate B2;

a first metal layer 102, a second metal layer 103 and a source-drain metal layer 105 are sequentially arranged on a substrate base plate 101, wherein a scanning line S, a first polar plate B1, a gate g are positioned on the first metal layer 102, a second polar plate B2 is positioned on the second metal layer 103, and a data line D, a source S and a drain D are positioned on the source-drain metal layer 105; that is, the first metal layer 102 is a gate metal layer, and the second metal layer 103 is a capacitor metal layer. When the connecting line is manufactured along the first direction x, the first line segment, the second line segment and the third line segment are manufactured respectively by adopting the grid metal layer and the capacitor metal layer, so that the insulating intersection of the connecting line and the data line D can be ensured, and the short circuit of the connecting line and the data line is avoided. Meanwhile, three line segments are made of two layers of metal, the first line segment, the second line segment and the third line segment can be arranged in a staggered mode in the second direction, no gap exists between every two adjacent line segments in the arrangement direction, the influence of diffraction phenomena on the optical performance of the optical device under the screen can be reduced, and the imaging effect of the optical device under the screen is improved.

In another embodiment, the second metal layer, the first metal layer and the source drain metal layer are sequentially arranged on the substrate, the scan line and the first plate are located on the second metal layer, and the second plate is located on the first metal layer. The above-mentioned fig. 16 can be referred to for understanding, and the details are not repeated herein.

In one embodiment, the display area further includes a plurality of data lines extending in a first direction and a plurality of scan lines extending in a second direction; fig. 17 is an enlarged view of an alternate embodiment at the location of region Q in fig. 1, as shown in fig. 17. Only one scan line S and one data line D within the transition area AAG are illustrated in the drawing, and when the connection line L is led from within the first display area AA1 to be connected to the first pixel circuit DL1 within the transition area AAG, the connection line L may overlap the scan line S. The connecting lines L are disposed at different layers from the scanning lines S in this embodiment.

Fig. 18 is a film structure diagram of an alternative implementation manner of the display panel provided in the embodiment of the present application, and only one transistor T and a pixel capacitor of a pixel circuit are illustrated in the diagram. The transistor includes an active layer w, a gate electrode g, a source electrode s, and a drain electrode d. The pixel capacitor comprises a first polar plate B1 and a second polar plate B2;

the gate metal layer 106, the first metal layer 102 and the second metal layer 103 are sequentially arranged on the substrate base plate 101, wherein the scan line S and the first plate B1, and the gate g are located on the gate metal layer 106, the second plate B2 is located on the first metal layer 102, and the data line D, and the source S and the drain D are located on the second metal layer 103; that is, the first metal layer 102 is a capacitor metal layer, and the second metal layer 103 is a source/drain metal layer. When the connecting line is manufactured along the first direction x, the capacitance metal layer and the source drain metal layer are respectively used for manufacturing the first line segment, the second line segment and the third line segment as illustrated in the figures 2 and 3, so that the insulating intersection of the connecting line and the scanning line S can be ensured, and the short circuit of the connecting line and the scanning line is avoided. Meanwhile, three line segments are made of two layers of metal, the first line segment, the second line segment and the third line segment can be arranged in a staggered mode in the second direction, no gap exists between every two adjacent line segments in the arrangement direction, the influence of diffraction phenomena on the optical performance of the optical device under the screen can be reduced, and the imaging effect of the optical device under the screen is improved.

In another embodiment, the gate metal layer, the second metal layer and the first metal layer are sequentially arranged on the substrate, the second plate is located on the second metal layer, and the data line is located on the first metal layer. The above-mentioned fig. 17 can be referred to for understanding, and the details are not repeated herein.

Further, in the display panel provided in the embodiment of the present application, the line width of the connection line is positively correlated to the line length of the connection line. According to the law of resistance, R ═ ρ L/S. Wherein R is a resistance value. ρ is the resistivity of the material making up the resistor, L is the wire length, and S is the wire cross-sectional area. The line width through setting up the connecting wire is positive correlation with the line length of connecting wire, comes the resistance grow problem that the length of balanced line lengthens and lead to through the increase linewidth to reduce the resistance difference between each connecting wire, and then reduce the pressure drop difference that the resistance difference leads to on each connecting wire. So as to reduce the influence of different voltage drops on the brightness of the sub-pixel.

In one example, FIG. 19 is an enlarged view of an alternative embodiment at the location of region Q in FIG. 1. As shown in FIG. 19, the first display area AA1 and the transition area AAG have a virtual boundary BJ therebetween; in two adjacent first sub-pixels sp 1: the farther the first sub-pixel is from the virtual boundary BJ, the closer the first pixel circuit DL1 electrically connected thereto is to the virtual boundary BJ. The embodiment can reduce the difference of the line length between the connecting lines and avoid the larger difference of the resistance between the connecting lines. And further, the voltage drop difference caused by the resistance difference of each connecting line is reduced. So as to reduce the influence of different voltage drops on the brightness of the sub-pixel.

In an embodiment, fig. 20 is a partial schematic view of another alternative implementation of a display panel provided in an embodiment of the present application. As shown in fig. 20, only the first display area AA1 and a portion of the transition area AAG surrounding the first display area AA1 are illustrated. The display region further includes a plurality of first signal lines extending in the third direction a, the plurality of first signal lines including a plurality of first a signal lines 1X1 and a plurality of first b signal lines 2X 1; the first signal line 1X1 passes through the display region in the third direction a; a virtual boundary BJ is provided between the first display area AA1 and the transition area AAG, the first second signal line 2X1 is cut off at a side of the virtual boundary adjacent to the transition area AAG, the transition area AAG includes a plurality of first winding lines R1, and two first second signal lines 2X1 positioned at both sides of the first display area AA1 in the third direction are electrically connected through the first winding lines R1. Optionally, the first signal line may be a data line or a positive power line. Or may be a scan line, a reset signal line, or the like. In this embodiment, two first second signal lines that will be located first display area both sides are connected through the first wire winding in the transition district for first second signal line that extends in the third direction need not run through first display area, has reduced the line number of walking in the first display area, can be favorable to promoting the area in the printing opacity district in first display area, and then uses in the optical device scheme under the screen, can increase the light volume that optical device received.

Further, as shown in fig. 20, the display region further includes a plurality of second signal lines extending along a fourth direction b, the fourth direction b intersecting the third direction a, the plurality of second signal lines including a plurality of second signal lines 1X2 and a plurality of second signal lines 2X 2; the second signal line 1X2 passes through the display region in the fourth direction; the second signal lines 2X2 are cut off at a virtual boundary on a side close to the transition area AAG including a plurality of second winding lines R2, and two second signal lines 2X2 positioned at both sides of the first display area AA1 in the fourth direction b are electrically connected through the second winding lines R2. Only a portion of the second signal line is shown. The two second signal lines of being located first display area both sides are further set up and are connected through the second wire winding in the transition district for the second signal line of being right in the fourth direction extension need not run through first display area, has reduced the line figure of walking in the first display area, can be favorable to promoting the area in the printing opacity district of first display area, and then uses in the optical device scheme under the screen, can increase the light volume that optical device received.

In an embodiment, fig. 21 is a schematic view of another alternative implementation of the display panel provided in the embodiment of the present application. As shown in fig. 21, the transition area AAG includes at least one alignment mark ZZ, the transition area AAG includes a plurality of pixel areas P1 and a plurality of circuit areas P2, the transition sub-pixel spg is located in the pixel area P1, and the first pixel circuit DL1 is located in the circuit area P2, where the alignment mark ZZ is located between two adjacent pixel areas P1 and does not overlap with the circuit area P2. The embodiment of the present invention does not limit the number of the alignment marks. The alignment mark can be made of a metal material, and the alignment mark made of the metal material can reflect light, so that the alignment mark is applied to the scheme of the optical device under the screen, and when the optical device and the display panel are assembled and aligned, whether alignment is accurate can be judged through the alignment mark. The sub-pixel density of the first display area and the transition area is smaller than that of the second display area, and the position of the optical device can be roughly judged through the light transmission areas of the first display area and the transition area during alignment, so that alignment is realized. After the design of this application embodiment is adopted, increased the counterpoint mark, counterpoint mark and pixel district and circuit region all do not overlap, can promote the counterpoint degree of accuracy through the accurate position of judging optical device place of counterpoint mark in the assembling process.

Based on the same inventive concept, an embodiment of the present application further provides a display device, and fig. 22 is a schematic view of the display device provided in the embodiment of the present application, and as shown in fig. 22, the display device includes the display panel 100 provided in any embodiment of the present application. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 22 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel comprising a display region, said display region comprising a first display region, a transition region and a second display region, said transition region at least half-surrounding said first display region, said second display region at least half-surrounding said transition region, said first display region comprising a plurality of first sub-pixels, said transition region comprising a plurality of transition sub-pixels, said display region further comprising a plurality of pixel circuits, said plurality of pixel circuits comprising a plurality of first pixel circuits and a plurality of transition pixel circuits located in said transition region, said first sub-pixels being electrically connected to said first pixel circuits, said transition sub-pixels being electrically connected to said transition pixel circuits;

the first sub-pixels comprise first sub-pixels of a first type and second sub-pixels of a second type, and the farther the first sub-pixels of the first type are from the transition region, the farther the first pixel circuits electrically connected with the first sub-pixels are from the first display region; the closer the second type of first sub-pixel is to the transition region, the closer the first pixel circuit electrically connected thereto is to the first display region.

2. The display panel according to claim 1, wherein the display panel further comprises a substrate base plate, and an overlapping region exists between an orthographic projection of the first pixel circuit on the substrate base plate and an orthographic projection of the transition pixel circuit on the substrate base plate along a first direction or a second direction, and the first direction and the second direction are mutually crossed.

3. The display panel according to claim 1, wherein the display region further comprises a plurality of connection lines, the first sub-pixel and the first pixel circuit are electrically connected through the connection lines, the connection lines comprise a first type of connection line and a second type of connection line electrically connected to the first type of connection line, the first type of connection line extends in a first direction, the second type of connection line extends in a second direction, and the first direction crosses the second direction.

4. The display panel according to claim 1, wherein the second display region includes a plurality of second sub-pixels;

the display area further comprises a plurality of pixel circuits and a plurality of connecting lines, the plurality of pixel circuits comprise a plurality of first pixel circuits located in the transition area, the first sub-pixels are electrically connected with the first pixel circuits through the connecting lines, and the plurality of connecting lines comprise first connecting lines, second connecting lines and third connecting lines;

the plurality of first sub-pixels include a first sub-pixel electrically connected to the first pixel circuit through the first connection line, a second first sub-pixel electrically connected to the first pixel circuit through the second connection line, and a third first sub-pixel electrically connected to the first pixel circuit through the third connection line; wherein,

the first connecting line comprises a first line segment, the second connecting line comprises a second line segment, the third connecting line comprises a third line segment, the first line segment, the second line segment and the third line segment extend along a first direction and are sequentially arranged in a second direction, and the second direction is perpendicular to the first direction;

the display panel comprises a substrate base plate, a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are positioned on the substrate base plate, the first connecting line and the third connecting line are positioned on the first metal layer, the second connecting line is positioned on the second metal layer, orthographic projections of the first line segment, the second line segment and the third line segment on the substrate base plate are respectively a first projection, a second projection and a third projection, the first projection and the second projection are overlapped or have a common boundary, and the second projection and the third projection are overlapped or have a common boundary.

5. The display panel according to claim 4,

the plurality of first sub-pixels comprise a fourth first sub-pixel, the plurality of connecting lines further comprise a fourth connecting line, the fourth connecting line is located on the second metal layer, and the fourth first sub-pixel is electrically connected with the first pixel circuit through the fourth connecting line;

the fourth connecting line includes a fourth line segment extending along the first direction, and an orthogonal projection of the fourth line segment on the substrate base plate is a fourth projection, where the fourth projection and the third projection overlap or have a common boundary.

6. The display panel according to claim 4,

the plurality of first sub-pixels comprise a fourth first sub-pixel, the plurality of connecting lines further comprise a fourth connecting line, and the fourth first sub-pixel is electrically connected with the first pixel circuit through the fourth connecting line;

the fourth connecting line comprises a fourth line segment extending along the first direction, an orthographic projection of the fourth line segment on the substrate base plate is a fourth projection, the fourth projection overlaps with the first projection, and the fourth projection overlaps with the second projection;

the display panel further comprises a third metal layer located on the substrate base plate, and the fourth connecting line is located on the third metal layer.

7. The display panel according to claim 4,

the first sub-pixel, the second first sub-pixel, and the third first sub-pixel are sequentially arranged in the first direction.

8. The display panel according to claim 4,

the plurality of first subpixels further includes a fifth first subpixel, a sixth first subpixel, and a seventh first subpixel arranged in the second direction; the plurality of connecting lines comprise a fifth connecting line, a sixth connecting line and a seventh connecting line, the fifth connecting line and the seventh connecting line are positioned on the first metal layer, and the sixth connecting line is positioned on the second metal layer;

the fifth first sub-pixel is electrically connected to the first pixel circuit through the fifth connection line, the sixth first sub-pixel is electrically connected to the first pixel circuit through the sixth connection line, and the seventh first sub-pixel is electrically connected to the first pixel circuit through the seventh connection line; wherein,

the fifth connecting line comprises a fifth line segment, the fifth connecting line comprises a sixth line segment, the seventh connecting line comprises a seventh line segment, and the fifth line segment, the sixth line segment and the seventh line segment extend along the second direction and are sequentially arranged in the first direction;

orthographic projections of the fifth line segment, the sixth line segment and the seventh line segment on the substrate base plate are respectively a fifth projection, a sixth projection and a seventh projection, wherein the fifth projection and the sixth projection overlap or have a common boundary, and the sixth projection and the seventh projection overlap or have a common boundary.

9. The display panel according to claim 4,

the display area further comprises a plurality of scanning lines extending along the first direction and a plurality of data lines extending along the second direction;

the pixel circuit comprises a pixel capacitor, and the pixel capacitor comprises a first polar plate and a second polar plate;

the display panel further comprises a source drain metal layer positioned on the substrate, and the data line is positioned on the source drain metal layer; wherein,

the first metal layer, the second metal layer and the source drain metal layer are sequentially arranged on the substrate, the scanning line and the first polar plate are positioned on the first metal layer, and the second polar plate is positioned on the second metal layer; or the second metal layer, the first metal layer and the source drain metal layer are sequentially arranged on the substrate, the scanning line and the first polar plate are positioned on the second metal layer, and the second polar plate is positioned on the first metal layer.

10. The display panel according to claim 4,

the display area further comprises a plurality of data lines extending along the first direction and a plurality of scanning lines extending along the second direction;

the display panel further comprises a grid metal layer positioned on the substrate base plate, and the scanning line and the first polar plate are positioned on the grid metal layer; wherein,

the gate metal layer, the first metal layer and the second metal layer are sequentially arranged on the substrate, the second plate is located on the first metal layer, and the data line is located on the second metal layer; or, the gate metal layer, the second metal layer, and the first metal layer are sequentially arranged on the substrate, the second plate is located on the second metal layer, and the data line is located on the first metal layer.

11. The display panel according to claim 4,

a virtual boundary is arranged between the first display area and the transition area;

the plurality of first sub-pixels comprise an eighth first sub-pixel and a ninth first sub-pixel, and the eighth first sub-pixel is positioned on one side of the ninth first sub-pixel away from the virtual boundary; the plurality of connecting lines comprise an eighth connecting line and a ninth connecting line; the eighth first sub-pixel is electrically connected with the first pixel circuit through the eighth connecting line, and the ninth first sub-pixel is electrically connected with the first pixel circuit through the ninth connecting line;

the eighth connecting line comprises an eighth line segment extending along the first direction, the ninth connecting line comprises a ninth line segment extending along the first direction, and the eighth line segment and the ninth line segment are overlapped in the direction perpendicular to the display panel; wherein,

the ninth connecting line is positioned on one side of the eighth connecting line far away from the substrate base plate.

12. The display panel according to claim 1, wherein the display area further comprises a plurality of connecting lines, and the line width of the connecting lines is positively correlated with the line length of the connecting lines.

13. The display panel according to claim 1,

the display area further comprises a plurality of first signal lines extending along a third direction, and the plurality of first signal lines comprise a plurality of first A signal lines and a plurality of first B signal lines;

the first signal line penetrates through the display area in the third direction;

a virtual boundary is arranged between the first display area and the transition area, the first second signal line is cut off at one side of the virtual boundary close to the transition area, the transition area comprises a plurality of first winding lines, and two first second signal lines positioned at two sides of the first display area in the third direction are electrically connected through the first winding lines.

14. The display panel according to claim 13,

the display area further comprises a plurality of second signal lines extending along a fourth direction, the fourth direction is crossed with the third direction, and the plurality of second signal lines comprise a plurality of second signal lines and a plurality of second signal lines;

the second signal line penetrates the display area in the fourth direction;

the second signal lines are cut off at one side of the virtual boundary close to the transition area, the transition area comprises a plurality of second winding lines, and two second signal lines positioned at two sides of the first display area in the fourth direction are electrically connected through the second winding lines.

15. The display panel according to claim 1,

the transition area comprises at least one alignment mark, the transition area comprises a plurality of pixel areas and a plurality of circuit areas, the transition sub-pixels are located in the pixel areas, the first pixel circuits are located in the circuit areas, and the alignment mark is located between every two adjacent pixel areas and does not overlap with the circuit areas.

16. The display panel according to claim 1,

a virtual boundary is arranged between the first display area and the transition area, and the first pixel circuits are arranged along the virtual boundary.

17. The display panel according to claim 1,

the plurality of pixel circuits further comprise a plurality of second pixel circuits, the plurality of second pixel circuits are located in the second display area, and the second pixel circuits are electrically connected with the second sub-pixels.

18. A display device characterized by comprising the display panel according to any one of claims 1 to 17.