CN109524445B - Display panel and display device - Google Patents
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- CN109524445B CN109524445B CN201811561173.5A CN201811561173A CN109524445B CN 109524445 B CN109524445 B CN 109524445B CN 201811561173 A CN201811561173 A CN 201811561173A CN 109524445 B CN109524445 B CN 109524445B
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Abstract
The invention describes a display panel and a display device, relating to the technical field of display, wherein the display panel comprises: the first connecting wires are connected with the same row of pixel units of the first sub-display area and the second sub-display area, and the first connecting wires are arranged above the grid driving circuit area through anode metal layer routing and are overlapped with the grid driving circuit on the orthographic projection of the display panel. Therefore, the first connecting wires do not occupy space, the occupied proportion of a non-display area is reduced, and a narrow frame is further realized. Meanwhile, through resistance compensation, the load difference between the first display area and the second display area is reduced, the display brightness uniformity of the display panel is improved, and the display effect is enhanced.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
Along with the development of display technology, the diversified demand of people has been satisfied in different sex display panel's structure and appearance design, and people also more and more high to display panel's narrow frame requirement down, through setting up equipment such as camera and earphone on the mobile terminal at display panel's open region, compare with traditional rectangle display panel, can improve display panel's screen greatly and account for than.
As shown in fig. 1, for a display panel with an opening region in the prior art, due to the existence of the opening region K ', the first display region a1 ' and the second display region a2 ' bypass the opening region K ' through the data signal lines D ', so that a large number of data signal lines D ' are densely packed in the opening region K ', not only is the frame region of the special-shaped display panel increased, but also the signal lines densely arranged in the opening region are prone to generate coupling capacitance, and simultaneously, due to the winding of the opening region, the resistance loads of the data signal lines corresponding to the first display region and the second display region are different, thereby affecting the display luminance uniformity of the display panel.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device, which are used to improve the screen ratio of the display panel, reduce the narrow frame, balance the resistance load of the signal lines, and improve the uniformity of the display brightness.
The present invention provides a display panel, comprising:
the display device comprises a display area, a driving circuit and a control circuit, wherein the display area comprises a plurality of data signal lines and a plurality of grid signal lines which are arranged in a crossed manner, and pixel units defined by the crossed data signal lines and the grid signal lines;
the first display area and the second display area are arranged along the extending direction of the grid signal line, and the number of any column of pixel units in the first display area is less than that of any column of pixel units in the second display area;
the first display area comprises a first sub display area and a second sub display area which are arranged along the extending direction of the data signal line, an opening area is arranged between the first sub display area and the second sub display area at intervals, and a first frame area is arranged between the opening area and the second display area;
the first display area comprises first data lines, and the pixel units in the same column in the first display area are connected by the first data lines;
the first data line comprises a first sub data line, a second sub data line and a first connecting lead, the first sub data line is located in the first sub display area, the second sub data line is located in the second sub display area, the first connecting lead comprises a first sub connecting lead, and the first sub connecting lead is arranged in the first frame area;
the first connecting wire is connected with the first sub data line and the second sub data line.
The driving circuit surrounds the first display area and the second display area, the driving circuit comprises a first driving circuit positioned in the first frame area, and the first driving circuit is electrically connected with at least one grid driving signal line;
the display panel further includes a substrate base plate, and an orthogonal projection of the first sub-connection wire on the substrate base plate overlaps an orthogonal projection of the first driving circuit on the substrate base plate.
The invention further comprises a display device and the display panel.
Compared with the prior art, the invention at least realizes the following beneficial effects:
according to the display panel and the display device provided by the invention, the first connecting lead is connected with the first sub-data line and the second sub-data line, the first connecting lead comprises the first sub-connecting lead positioned in the first frame area, and the first sub-connecting lead is at least partially overlapped with the orthographic projection of the first driving circuit on the substrate, so that the first sub-connecting lead does not occupy the width of the first frame area, the width of the first frame area is reduced, and the narrow frame is further realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a prior art display panel;
fig. 2 is a schematic plan view of a display panel according to an embodiment of the present invention;
FIG. 3 is an enlarged view of the position A in FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view taken along section line XX' in FIG. 2 according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view taken along section line XX' in FIG. 2 according to an embodiment of the present invention;
FIG. 6 is another enlarged schematic view of the position A in FIG. 2 according to the present invention;
FIG. 7 is a schematic view of an enlarged view of the position A in FIG. 2 according to an embodiment of the present invention;
FIG. 8 is an enlarged view of the position B in FIG. 5 according to the present invention;
FIG. 9 is a further enlarged schematic view of the position A in FIG. 2 according to the present invention;
FIG. 10 is a further enlarged schematic view of the position A in FIG. 2 according to the present invention;
FIG. 11 is a schematic view of an enlarged view of the position A in FIG. 2 according to an embodiment of the present invention;
FIG. 12 is a cross-sectional view taken along line YY' of FIG. 3 according to one embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view taken along line YY' in FIG. 3 according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In order to reduce the width of the frame area, reduce the coupling capacitance generated by dense arrangement of the signal lines in the frame area and improve the display effect of the display screen, the invention designs the following technical scheme:
the present embodiment provides a display panel, please refer to fig. 2, fig. 3 and fig. 4.
Specifically, as shown in fig. 2, fig. 2 is a schematic plan view of a display panel according to an embodiment of the present invention, where the display panel 100 includes: the display device comprises a display area AA, a display area B and a display area C, wherein the display area AA comprises a plurality of data signal lines D and a plurality of grid signal lines G which are arranged in a crossed mode; a pixel unit P defined by the intersection of the data signal line D and the gate signal line G; a first display area a1 and a second display area a2 arranged along a direction in which the gate signal line G extends, wherein the number of pixel cells in any column in the first display area a1 is less than the number of pixel cells in any column in the second display area a 2;
it should be noted that, in general, the extending direction of the data signal line D is a column direction of a plane where the display panel 100 is located, and the extending direction of the gate signal line G is a row direction of the plane where the display panel 100 is located, which is only an exemplary illustration in this embodiment, and specific details need to be referred to in this embodiment.
With continued reference to fig. 2, the first display region a1 includes a first sub-display region a11 and a second sub-display region a12 arranged in a row direction, wherein an opening region K is spaced between the first sub-display region a11 and the second sub-display region a12, and a first bezel region B1 is disposed between the opening region K and the second display region a 2; it is understood that the opening region is disposed at a side of the display panel, and may be disposed at one side or both sides of the display panel, for example, the opening region is disposed at a left side of the display panel in this embodiment.
Specifically, referring to fig. 3, fig. 3 is an enlarged schematic view of a position a in fig. 2 according to an embodiment of the present invention, in which the first display area a1 includes a first data line 10, and the pixel cells in the same column in the first display area a1 are connected by the first data line 10, that is, the pixel cells in the same column in the first sub-display area a11 and the second sub-display area a12 are connected by the same first data line 10; the first data line 10 includes a first sub data line 11, a second sub data line 12 and a first connecting wire 13, the first sub data line 11 is disposed in the first sub display area a11, the second sub data line 12 is disposed in the second sub display area a12, where it should be noted that each column of pixel cells in the first sub display area a11 is connected through the first sub data line 11, and similarly, each column of pixel cells in the second sub display area a12 is connected through the second sub data line 12;
with continued reference to fig. 3, the first connecting wire 13 includes a first sub-connecting wire 131, the first sub-connecting wire 131 is disposed in the first frame region B1, and the first connecting wire 13 connects the first sub-data line 11 and the second sub-data line 12. It is understood that the pixel cells of the columns in the first sub-display area a11 and the pixel cells of the columns in the second sub-display area a12 are connected in a one-to-one correspondence by the first connection wires 13.
With continued reference to fig. 2, the display panel 100 further includes a driving circuit 6 surrounding the first display region a11 and the second display region a12, the driving circuit 6 includes a first driving circuit 60 located in the first frame region B1, and the first driving circuit 60 is electrically connected to at least one gate driving signal line G;
it can be understood that the driving circuits are located in the non-display areas at both sides of the display panel, and meanwhile, the gate signal lines G in each row of the first display area a1 and the second display area a2 are respectively connected to the driving circuits 6 at both ends of the display area a; it should be noted that the opening region K of the display panel does not affect the dual-side driving mode of the display region, that is, the first driving circuit 60 is also disposed at the first frame region B1 corresponding to the opening region K, so that the delay difference between the gate signal lines in each row of the first display region and the gate signal lines in each row of the second display region can be reduced, and the problem of display non-uniformity of the display panel is effectively solved.
Further, referring to fig. 4, fig. 4 is a schematic cross-sectional structure view along a section line XX 'in fig. 2 according to an embodiment of the present invention, the display panel further includes a substrate 20, and the first sub-connecting wire 131 is further illustrated on the substrate 20, referring to fig. 4, fig. 4 is a schematic cross-sectional structure view along a section line XX' in fig. 2 according to an embodiment of the present invention, the first sub-connecting wire 131 is disposed above the first driving circuit 60, and specifically, a front projection of the first sub-connecting wire 131 on the substrate completely falls into a front projection of the first driving circuit 60 on the substrate.
It should be noted that the orthographic projection of the first sub-connecting wire 131 on the substrate 20 may also partially fall into the orthographic projection of the first driving circuit 60 on the substrate, that is, the orthographic projection of the first sub-connecting wire 131 on the substrate 20 and the orthographic projection of the first driving circuit 60 on the substrate 20 may partially overlap or completely overlap, and naturally, the larger the overlapping area is, the more beneficial to the implementation of the present scheme is.
In this embodiment, the first driving circuit is disposed at the first frame region, so that the display region corresponding to the opening region in the display panel adopts a bilateral driving mode, which can reduce the delay difference of the gate signal lines; in the prior art, the display panel is provided with the opening region, so that the data signal line corresponding to the opening region needs to be wound to the first frame region, and the width of the first frame region is increased by the wound first sub-connecting wire. And overlap first sub-connecting wire and first drive circuit at least part in this scheme in the direction of perpendicular to display panel to first sub-connecting wire need not extra frame region that occupies display panel, but occupies first frame regional space jointly with first drive circuit, thereby compare current design, has reduced first sub-connecting wire and has occupied the regional width of first frame, thereby be favorable to realizing display panel's narrow frame design, improve display effect.
Optionally, referring to fig. 5, fig. 5 is another schematic cross-sectional structure view along a section line XX' in fig. 2 according to an embodiment of the disclosure, in which the display panel 100 includes an array substrate 1, the array substrate 1 includes the substrate 20, and a pixel circuit 2 and an organic light emitting device layer 3 located on the substrate 20, and the pixel circuit 2 is disposed on a side of the organic light emitting device layer 3 close to the substrate 20; specifically, the organic light-emitting device layer 3, which is controlled to emit light by the pixel circuit 2, includes a planarization layer 31, an anode 32, a light-emitting layer 33, a cathode 34, a pixel defining layer 35;
meanwhile, a supporting column 36 is arranged on the pixel defining layer 35, the supporting column 36 is arranged on one side of the pixel separation region of the pixel defining layer 35, which is away from the substrate 20, and the display panel 100 further comprises a glass cover plate 40, and the glass cover plate 40 is arranged on one side of the supporting column 36, which is away from the substrate 20; when the glass cover plate 40 is under pressure, the supporting columns 36 can support the glass cover plate 40, so that the bearing strength and the compressive strength of the panel are improved.
Further, with reference to fig. 5, the first connecting wire 13 and the anode 32 are disposed in the same layer. It should be noted that, the term "disposed in the same layer" should be understood that the first connecting wires 13 are replaced by the anodes 32, that is, the first connecting wires 13 are made of the same material as the anodes 32 and are made of the same mask, which can simplify the process and improve the manufacturing efficiency of the display panel.
Optionally, referring to fig. 6, fig. 6 is another enlarged schematic view of a position a in fig. 2 according to an embodiment of the present invention, in which the first driving circuit 60 includes a gate control circuit 61 and a light-emitting control circuit 62, and the orthographic projections of the first connecting wires 131 and the gate control circuit 61 on the substrate 20 are not overlapped; and the first sub-connection wires 131 overlap with the orthographic projection of the light emission control circuit 62 on the base substrate 20.
Note that, the orthographic projection of the first sub-connection lead 131 on the substrate 20 may partially overlap with the orthographic projection of the light emission control circuit 62 on the substrate, or may completely overlap with the orthographic projection of the first sub-connection lead 131 on the substrate 20, but the orthographic projection of the first sub-connection lead 131 on the substrate 20 may partially overlap with the orthographic projection of the light emission control circuit 62 on the substrate, as shown in fig. 6.
Specifically, in the display panel provided in the embodiment of the present invention, the first sub-connection wires 131 and the light-emitting control circuit 62 are at least partially overlapped in the orthogonal projection perpendicular to the substrate, so that the first sub-connection wires do not need to additionally occupy the frame area of the display panel, but occupy the space of the first frame area together with the light-emitting control circuit, thereby reducing the width of the first frame area, facilitating the implementation of the narrow frame design of the display panel, and improving the display effect.
Specifically, in the display panel provided by the embodiment of the present invention, the orthographic projections of the first sub-connecting wire 131 and the gate control circuit 61 on the substrate do not overlap. It can be understood that the gate control circuit is used for alternately transmitting the gate driving signal to the pixel units to realize the line-by-line scanning of each pixel unit in the display panel, wherein the gate driving signal is turned on for a short time, and the frequency of the transmission signal is fast and greatly influenced. Therefore, when the first sub-connection wire 131 and the gate driving circuit 61 are located in different metal layers and an insulating layer is located between the first sub-connection wire 131 and the gate driving circuit 61 when the orthographic projection of the first sub-connection wire and the gate driving circuit 61 on the substrate generates an overlapping region, the overlapping region of the orthographic projection of the first sub-connection wire 131 and the gate driving circuit 61 on the substrate generates a parasitic capacitance, and the parasitic capacitance increases the load of the gate driving circuit 61, thereby affecting the normal driving load of the gate driving circuit, and finally affecting the display effect of the display panel. Compared with the light-emitting control circuit, the light-emitting control signal controlled by the light-emitting drive circuit is longer in opening time and is less influenced after being interfered by the outside, so that the influence of parasitic capacitance can not be obviously received.
Optionally, referring to fig. 7, fig. 7 is another enlarged schematic diagram of a position a in fig. 2 according to an embodiment of the present invention, where the first driving circuit 60 includes a thin film transistor TFT, and a high-level signal line VGH and a low-level signal line VGL electrically connected to the thin film transistor TFT; the first sub-connection wire 131 overlaps both the high-level signal line VGH and the low-level signal line VGL on the orthographic projection of the display panel;
in the embodiment of the present invention, the high-level signal line VGH and the low-level signal line VGL are fixed potential signal lines of the display panel, so that when the first sub-connecting wire and the orthographic projection of the high-level signal line VGH or the low-level signal line VGL with a fixed potential signal on the substrate generate an overlapping region to generate a parasitic capacitance, the parasitic capacitance does not generate an obvious influence on the high-level signal line VGH and the low-level signal line VGL with the fixed potential; meanwhile, the first sub-connection wires 131 are at least partially overlapped with the high-level signal lines VGH or the orthographic projection of the low-level signal lines VGL on the substrate, so that the frame area of the display panel occupied by the first sub-connection wires can be reduced, the width of the first frame area is further reduced, and the screen occupation ratio of the display panel is improved.
Optionally, referring to fig. 7, the first driving circuit 60 further includes a first clock signal line CX and a second clock signal line XCK, wherein the first sub-connecting wire 131 and the first clock signal line CK or the second clock signal line XCK do not overlap each other in the orthographic projection of the substrate 20.
It can be understood that the first sub-connecting wire 131 transmits a frequency conversion signal which is a data signal, similarly, the first clock signal line CX and the second clock signal line XCK are both pulse signals, when the first sub-connecting wire 131 and the orthographic projection of the first clock signal line CX or the second clock signal line XCK on the substrate have an overlapping region, the parasitic capacitance generated by the overlapping region may change the load on the clock signal line, and the clock signal line is a pulse signal and is easily affected by the load generated by the parasitic capacitance, thereby affecting the transmission of the clock signal. Therefore, in this embodiment, the first sub-connection wires and the first clock signal wires or the second clock signal wires do not overlap with each other in the orthographic projection on the substrate, so that the clock signals can be prevented from being disordered, and the display of the display panel is prevented from being poor.
Optionally, referring to fig. 8, fig. 8 is an enlarged schematic view of a position B in fig. 5 according to an embodiment of the present invention, wherein the anode 32 structure layer includes a three-layer structure consisting of a first transparent conductive layer 321, an opaque metal layer 322, and a second transparent conductive layer 323; in general, the first transparent conductive layer 321 and the second transparent conductive layer 323 are made of the same transparent material, such as ITO, so that the process flow can be simplified, and the production efficiency can be improved; the material of the opaque metal layer 322 may be Al or Ag, and for example, the anode 32 in the embodiment of the present invention adopts a three-layer conductive layer structure of ITO/Ag/ITO, although the anode in the embodiment is not limited to this three-layer structure.
Further, the first connection wire 131 includes one layer structure of a three-layer structure, or a two-layer structure, or a three-layer structure. Specifically, the structure and material of the first connecting wire are further described below:
in an alternative embodiment, when the first connecting wire 131 has one layer of the three-layer structure, it can be understood that the material of the first connecting wire 131 may be the same as the first transparent conductive layer 321, the opaque metal layer 322, or the first transparent conductive layer 323, which can reduce the process and cost.
In another optional embodiment, when the first connection wire 131 has a two-layer structure of the three-layer structure, similarly, the material of the first connection wire 131 may be the same as the material of the two-layer structure formed by the first transparent conductive layer 321/the opaque metal layer 322, or may be the same as the material of the other two-layer structure formed by the opaque transparent metal layer 322/the second transparent conductive layer 323, so that the process is simplified, and the process cost is reduced.
In another alternative embodiment, when the first connection wire 131 is a three-layer structure of the above three-layer structures, that is, the first connection wire 131 is composed of the first transparent conductive layer 321, the opaque metal layer 322, and the first transparent conductive layer 323, the material of the first connection wire 131 is completely the same as that of the anode 32, so that the process can be simplified, and the process cost can be reduced.
In the embodiment of the present invention, as shown in fig. 8, for example, the material and structure of the first connecting wire 131 are ITO/Ag/ITO, on one hand, the first connecting wire includes a metal material Ag, which does not increase the load on the signal line, and on the other hand, the first connecting wire includes a semiconductor material ITO, which can effectively reduce the influence of parasitic capacitance generated by the orthographic projection overlapping of other metal layers and the first connecting wire on the substrate, thereby improving the display effect of the display panel.
Further, since the data signal lines in the display panel are usually made of metal, when the first sub-connecting conductive line 131 is disposed on the same layer as the anode 32 and made of the same material, the resistance load on the first sub-connecting conductive line 131 is inevitably increased, and in order to further balance the load on the first display area and the second display area and reduce the difference of the display brightness, the data signal lines in the second display area are processed as follows:
in an alternative embodiment, please refer to fig. 9, where fig. 9 is a further enlarged schematic diagram of a position a in fig. 2 provided in the embodiment of the present invention, in which an average line width of the first connecting wire 13 is d1, and the average line width of the first sub-data line 11 and the average line width of the second sub-data line 12 are both d2, where d1 > d 2.
In the embodiment of the present invention, in a normal condition, the line widths of the first sub-data line 11, the second sub-data line 12 and the first connection wire 13 are uniform, since the first connection wire 13 is routed through the anode 32, the resistance load of the first connection wire 13 is increased, in order to balance the resistance load, the line width of the first connection wire 13 with a larger resistance value is set to be wider, and the line widths of the first sub-data line 11 and the second sub-data line 12 with a smaller resistance value are set to be narrower, so that the extra increased load of the first connection wire 13 is compensated, and finally, the brightness uniformity of each pixel unit in the first display area is realized, and the display effect of the display panel is enhanced.
It should be noted that, only two of the first connecting wires 13 are taken as an example for illustration, in this embodiment, the plurality of first connecting wires 13 may be widened to compensate for a resistance load difference caused by a large resistance due to a material of the first connecting wires 13, and the specific line width is set according to a specific routing condition, which is not limited in the present invention.
In another alternative embodiment, please refer to fig. 10, fig. 10 is a further enlarged schematic view of the position a in fig. 2 according to an embodiment of the present invention, wherein the second display area a2 includes a third sub-display area a21, a fourth sub-display area a22, and a fifth sub-display area a23 sequentially arranged along the extending direction of the data signal line, and the fourth sub-display area a22 is located between the third sub-display area a21 and the fifth sub-display area a 23; the first driving circuit 60 controls the pixel cells of the fourth sub-display area a22 to emit light through the gate driving signal line G;
further, the second display area a2 includes a second data line 50, the second data line 50 includes a third sub data line 51, a fourth sub data line 52, and a fifth sub data line 53, the third sub data line 51 is disposed in the third sub display area a21, the fourth sub data line 52 is disposed in the fourth sub display area a22, and the fifth sub data line 53 is disposed in the fifth sub display area a 23; wherein the content of the first and second substances,
the average line width of the third sub data line 51 and the fifth sub data line 53 is d3, and the average line width of the fourth sub data line is d4, wherein d3 > d 4.
In this embodiment, the line width of the fourth sub-data line corresponding to the pixel unit in the fourth sub-display area is reduced, which may increase the resistance and increase the load of the fourth sub-data line, thereby increasing the load on the second display area, which may be consistent with the increased load when the first connecting wire is replaced with an anode to a certain extent, so that the loads of the first display area and the second display area approach to be balanced at the opening area, and the uniformity of the brightness of the display panel is maintained.
It should be noted that the line widths of the third sub-data line 51 and the fifth sub-data line 53 are uniform, that is, the line widths are d3 everywhere, and meanwhile, the data line width d2 and the data line width d3 in the embodiment of the present invention may be of the same width, which may ensure the simplification of the process and the uniformity of the load of the display panel; while the line width of the fourth sub-data line 52 may be uniform or non-uniform, the present invention is not limited in detail herein, and for example, as shown in fig. 11, the line width of the fourth sub-data line 52 is uniform.
Further, referring to fig. 11, fig. 11 is another enlarged schematic view of a position a in fig. 2 according to an embodiment of the present invention, a width of an overlapping portion of the fourth sub-data line 52 and the gate output signal line G is d5, and a width of a non-overlapping portion of the fourth sub-data line 52 and the gate driving signal line G is d6, where d5 > d 6.
It is understood that, the average line width of the line width d5 and the line width d6 is d4, that is, d5 > d4 > d6, in the embodiment of the present invention, the width d5 of the fourth sub data line 52 overlapping with the gate output signal line may be equal to the width d3 of the third sub data line, so as to ensure that the load output by the gate driving signal line is not reduced.
In this embodiment, the width of the overlapping portion of the fourth sub data line and the gate driving signal line is kept unchanged, and the width of the non-line overlapping portion of the fourth sub data line and the gate driving signal line is reduced, so that the resistance load on the fourth sub data line is increased, the load on the gate signal line is not increased, the load on the fourth sub data line and the load on the first connecting wire are symmetrically balanced, and the problem of split display is avoided.
The following further describes the wiring manner of the first connecting wires with reference to the film layer structure of the display panel:
optionally, referring to fig. 12, fig. 12 is another schematic cross-sectional structure view along a section line YY' in fig. 3 according to an embodiment of the present invention, where the pixel circuit 2 includes an active layer 21 disposed on a substrate 20, a Gate metal layer Gate, source and drain metal layers S-D, and a capacitor metal layer C; the source and drain electrode metal S-D layer is positioned in the planarization layer 31; the first sub data line 11, the second sub data line 12 and the second data line 50 are all arranged on the same layer as the source-drain metal layer S-D, and the first connecting wire 13 is electrically connected with the first sub data line 11 and the second sub data line 12 through a through hole H.
In the embodiment of the invention, the first sub data line, the second data line and the source drain layer are arranged on the same layer, and the first connecting lead and the anode layer are arranged on the same layer, so that the process can be simplified, and the manufacturing efficiency of the display panel can be improved.
Optionally, referring to fig. 13, fig. 13 is another schematic cross-sectional structure view taken along a section line YY' in fig. 3 according to an embodiment of the present invention, wherein a pixel defining layer 35 is located on a side of the planarization layer 31 away from the substrate 20, and the anode layer 32 is located on a side of the pixel defining layer 35 away from the substrate 20.
In this embodiment, the anode layer 32 is disposed above the pixel defining layer 35, that is, during the process, the pixel defining layer 35 is first fabricated, and then the anode layer 32 is fabricated. At this time, the anode layer 32 and the source and drain metal layers S-D are separated by two insulating layers, namely the planarization layer 31 and the pixel defining layer 35, and compared with the conventional arrangement, the pixel defining layer is additionally added to the anode layer 32 and the source and drain metal layers S-D in this embodiment. Because the anode layer 32 and the source-drain metal layers S-D are respectively equivalent to two metal plates of the capacitor, when the distance between the anode layer 32 and the source-drain metal layers S-D is increased, that is, the distance between the two metal plates in the capacitor is increased, the parasitic capacitance in the capacitor is finally reduced, and the influence of the parasitic capacitance on the control signal of the first driving circuit is reduced.
When the first connecting wires 13 and the anode layer 32 are disposed on the same layer, the reduction of the parasitic capacitance can also reduce the load on the first connecting wires, so that the brightness of the display panel is more uniform.
The invention also provides a display device comprising the display panel provided by the invention. Specifically, referring to fig. 14, fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 900 provided in fig. 14 includes the display panel 100 according to the embodiment. It should be noted that fig. 14 illustrates a mobile phone as an example of the display device 900, but the display device 900 is not limited to a mobile phone, and specifically, the display device 900 may include any display device or electronic device having a display function, such as a computer, a television, or a vehicle-mounted display, and the present invention is not limited to this.
According to the display panel and the display device provided by the embodiment of the invention, the first connecting lead is arranged above the gate driving circuit area through the anode metal layer and is overlapped with the gate driving circuit on the orthographic projection of the display panel, so that the first connecting lead does not occupy space, the proportion of a non-display area is reduced, and a narrow frame is further realized. Meanwhile, through resistance compensation, the load difference between the first display area and the second display area is reduced, the display brightness uniformity of the display panel is improved, and the display effect is enhanced.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (12)
1. A display panel, comprising:
the display device comprises a display area, a driving circuit and a control circuit, wherein the display area comprises a plurality of data signal lines and a plurality of grid signal lines which are arranged in a crossed manner, and pixel units defined by the crossed data signal lines and the grid signal lines;
the first display area and the second display area are arranged along the extending direction of the grid signal line, and the number of any column of pixel units in the first display area is less than that of any column of pixel units in the second display area;
the first display area comprises a first sub display area and a second sub display area which are arranged along the extending direction of the data signal line, an opening area is arranged between the first sub display area and the second sub display area at intervals, and a first frame area is arranged between the opening area and the second display area;
the first display area comprises first data lines, and the pixel units in the same column in the first display area are connected by the first data lines;
the first data line comprises a first sub data line, a second sub data line and a first connecting lead, the first sub data line is located in the first sub display area, the second sub data line is located in the second sub display area, the first connecting lead comprises a first sub connecting lead, the first sub connecting lead is arranged in the first frame area, and the first connecting lead is connected with the first sub data line and the second sub data line;
a driving circuit surrounding the first display area and the second display area, the driving circuit including a first driving circuit located in the first bezel area,
the first driving circuit is electrically connected with at least one grid driving signal line;
the display panel further comprises a substrate base plate, and the orthographic projection of the first sub-connecting lead on the substrate base plate is at least partially overlapped with the orthographic projection of the first driving circuit on the substrate base plate.
2. The display panel according to claim 1, comprising an array substrate including the base substrate and a pixel circuit and an organic light emitting device layer on the base substrate, the pixel circuit being disposed on a side of the organic light emitting device layer adjacent to the base substrate, wherein,
the organic light-emitting device layer comprises a planarization layer, a cathode, a light-emitting layer, an anode and a pixel defining layer;
the first connecting lead and the anode are arranged on the same layer.
3. The display panel according to claim 2, wherein the first driving circuit includes a gate control circuit and a light emission control circuit, and the first connection wire does not overlap with an orthogonal projection of the gate control circuit on the substrate base plate;
the first sub-connecting lead overlaps with an orthographic projection of the light emission control circuit on the substrate base plate.
4. The display panel according to claim 2, wherein the first driver circuit includes a thin film transistor, and a high-level signal line and a low-level signal line electrically connected to the thin film transistor;
the first sub-connecting lead is overlapped with orthographic projections of the high-level signal line and the low-level signal line on the substrate.
5. The display panel according to claim 4, wherein the first driving circuit comprises a first clock signal line and a second clock signal line, and wherein the first sub-connection wire does not overlap with an orthographic projection of the first clock signal line or the second clock signal line on the substrate.
6. The display panel according to claim 2, wherein the anode comprises a three-layer structure of a first transparent conductive layer/an opaque metal layer/a second transparent conductive layer;
the first connecting wire includes one layer structure, or two layers structure, or three layers structure of the three-layer structure.
7. The display panel according to claim 2,
the average line width of the first connecting lead is d1, and the average line width of the first sub data line and the average line width of the second sub data line are both d2, wherein d1 is greater than d 2.
8. The display panel according to claim 7, wherein the second display region includes a third sub-display region, a fourth sub-display region, and a fifth sub-display region arranged in this order along a direction in which the data signal line extends, the fourth sub-display region being located between the third sub-display region and the fifth sub-display region;
the first driving circuit controls the pixel unit of the fourth sub-display area to emit light through the grid driving signal line;
the second display area comprises a second data line, the second data line comprises a third sub-display area, a fourth sub-display area and a fifth sub-display area, the third sub-display area is located on the third sub-display area, the fourth sub-display area is located on the fourth sub-display area, and the fifth sub-display area is located on the fifth sub-display area; wherein the content of the first and second substances,
the average line width of the third sub data line and the average line width of the fifth sub data line are d3, and the average line width of the fourth sub data line is d4, wherein d3 is greater than d 4.
9. The display panel according to claim 8,
the width of the overlapping part of the fourth sub data line and the gate driving signal line is d5, and the width of the non-overlapping part of the fourth sub data line and the gate driving signal line is d6, wherein d5 is greater than d 6.
10. The display panel according to claim 8, wherein the pixel circuit includes an active layer, a gate metal layer, a source drain metal layer, and a capacitor metal layer disposed on the substrate;
the source drain electrode metal layer is positioned in the planarization layer;
the first sub data line, the second sub data line and the second data line are arranged on the same layer with the source and drain metal layer;
the first connecting lead is electrically connected with the first sub data line and the second sub data line through via holes.
11. The display panel according to claim 2, wherein the pixel defining layer is located on a side of the planarization layer away from the substrate base plate, and the anode is located on a side of the pixel defining layer away from the substrate base plate.
12. A display device, characterized in that it comprises a display panel according to any one of the preceding claims 1-11.
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