CN114937420B - Display panel and display device - Google Patents
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- CN114937420B CN114937420B CN202210594426.9A CN202210594426A CN114937420B CN 114937420 B CN114937420 B CN 114937420B CN 202210594426 A CN202210594426 A CN 202210594426A CN 114937420 B CN114937420 B CN 114937420B
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- 238000005516 engineering process Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0067—Devices for protecting against damage from electrostatic discharge
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
Abstract
The invention discloses a display panel and a display device, comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form the steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. According to the invention, the static protection area is arranged at the step, so that the non-display area can be further compressed in the column direction, and a narrow frame is realized.
Description
Technical Field
The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.
Background
The conventional display devices include a display, a television, a mobile phone, a tablet computer, etc., and along with the development of electronic technology, the manufacturing of a display panel is also mature, and the display panel provided in the prior art includes a liquid crystal display panel, an organic light emitting display panel, a plasma display panel, etc.
A liquid crystal display panel (LCD, liquid Crystal Display) is a mature display panel in the current manufacturing process, and occupies a large market in the field of display panels with low cost, good manufacturing yield and good display effect. The liquid crystal display device has the advantages of thin body, power saving, no radiation and the like, is widely applied to the field of flat panel display, such as liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computer screens or notebook computer screens and the like; organic light emitting diodes are increasingly used as a current-type light emitting device in high performance display, and an OLED display panel has excellent characteristics of self-luminescence, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panel, rich color, flexible display realization, wide operating temperature range and the like, so that the OLED display panel is known as a next-generation 'star' flat panel display technology. The OLED display panel comprises an anode, a cathode, a hole transmission layer, an organic light-emitting layer and an electron transmission layer, wherein the hole transmission layer, the organic light-emitting layer and the electron transmission layer are arranged between the anode and the cathode, the anode provides hole injection, the cathode provides electron injection, the holes and electrons injected by the cathode and the anode are combined in the organic light-emitting layer under the driving of external voltage, electron hole pairs (namely excitons) at a binding energy level are formed, and the excitons radiate and are de-excited to emit photons to generate visible light.
In recent years, based on the advantages of convenience in carrying, fashion, attractive appearance and the like, intelligent wearing equipment is increasingly popular with users. With the application of display technology in intelligent wearing and other portable electronic devices, the appearance of the display panel has diversified requirements, and then the special-shaped display panel appears.
In order to increase the aesthetic feeling of the display picture and the appearance of the intelligent wearable device, the display panel of the intelligent wearable device is higher and higher in demand for the narrow frame, but the display panel in the related art cannot compress the lower frame, so that the realization of the narrow frame is hindered.
Accordingly, there is a need to provide a display panel and a display device to realize a narrow bezel.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device to realize a narrow bezel.
In one aspect, the present invention provides a display panel including: a non-display region including a display region and at least partially surrounding the display region;
the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form the steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps;
the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits.
On the other hand, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:
a display panel of the present invention includes: a non-display region including a display region and at least partially surrounding the display region; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form the steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. The lower frame area of the display panel is provided with a step area and a fan-out wiring area, the fan-out wiring area is positioned between the step area and the display area, and a multiplexer and an electrostatic protection circuit are required to be arranged in the step area. According to the invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the step, the step is formed by unequal pixel numbers in adjacent pixel rows or adjacent pixel columns, so that only the multiplexer is arranged in the step area, the space corresponding to the step position in the lower frame is fully utilized, and of course, the multiplexer can be in one-to-one correspondence with the pixel columns as much as possible, the number of windings is reduced, and the width of the fanout line area in the longitudinal direction is reduced, so that the lower frame can be further compressed, and a narrow frame is realized.
Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic plan view of a display panel according to the related art;
FIG. 2 is an enlarged view of a portion of region M of FIG. 1;
FIG. 3 is a schematic plan view of a display panel according to the present invention;
FIG. 4 is an enlarged view of a portion of the N region of FIG. 3;
FIG. 5 is yet another enlarged partial view of the N region of FIG. 3;
FIG. 6 is yet another enlarged partial view of the N region of FIG. 3;
FIG. 7 is a further enlarged partial view of the N region of FIG. 3
FIG. 8 is yet another enlarged partial view of the N region of FIG. 3;
FIG. 9 is yet another enlarged partial view of the N region of FIG. 3;
fig. 10 is a schematic plan view of a display panel according to still another embodiment of the present invention;
FIG. 11 is an enlarged partial view of the area Q of FIG. 10;
FIG. 12 is a plan view of the electrostatic protection circuit of FIG. 11;
FIG. 13 is a cross-sectional view taken in the direction K-K' of FIG. 11;
FIG. 14 is a further cross-sectional view taken in the direction K-K' of FIG. 11;
FIG. 15 is a further cross-sectional view taken in the direction K-K' of FIG. 11;
FIG. 16 is a partial enlarged view of the first and second sub-non-display sections of FIG. 9;
FIG. 17 is a schematic plan view of a display panel according to another embodiment of the present invention;
fig. 18 is a schematic plan view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
In view of the problem that the lower bezel is difficult to achieve compression in the display panel of the related art, the inventors have studied the related art as follows: referring to fig. 1, fig. 1 is a schematic plan view of a display panel in the related art, fig. 2 is a partial enlarged view of an area M in fig. 1, the display panel in fig. 1 may be an intelligent wearable device, and may be circular, the display panel 0000 includes a display area AA and a non-display area BB surrounding the display area AA, the non-display area includes a lower frame 801, the lower frame 801 includes a binding area 01, a packaging area 02, a step area 03 and a fan-out routing area 04 which are sequentially arranged, a multiplexer 050 and an electrostatic protection circuit 0400 need to be disposed in the step area 03, as shown in fig. 2, an output end of the multiplexer 050 is electrically connected with a data line in the display area AA, and since a plurality of multiplexers 050 and electrostatic protection circuits 0400 need to be disposed in the step area 03, a pitch of the multiplexer 050 and a pitch of pixels in a row direction X are not equal, that is a one-to-one correspondence relationship between the multiplexer 050 and a pixel column in a column direction Y, a routing area 04 needs to be electrically connected with the data line in the display area in the fan-out routing area 03, and the column direction Y cannot be compressed in the column direction Y.
In order to solve the above technical problems, the present invention provides a display panel and a display device, and specific embodiments of the display panel and the display device will be described in detail below.
Referring to fig. 3 and 4, fig. 3 is a schematic plan view of a display panel according to the present invention, and fig. 4 is a partial enlarged view of an N region in fig. 3. The display panel 100 provided in this embodiment includes: a non-display area BB including a display area AA and at least partially surrounding the display area AA;
the display area AA includes a plurality of pixel rows 10 and a plurality of pixel columns 20, the periphery of the display area AA includes a plurality of steps 30, the number of pixels PX in two adjacent pixel rows 10 is unequal or the number of pixels PX in two adjacent pixel columns 20 is unequal to form a step 30, the non-display area BB includes a first non-display area BB1, and the first non-display area BB1 is adjacent to the step 30;
the first non-display area BB1 includes an electrostatic protection area 40, the electrostatic protection area 40 includes a plurality of electrostatic protection circuits 400, and a multiplexer 60 is included between portions of the electrostatic protection circuits 400.
Specifically, fig. 3 illustrates the display panel 100 as a circular display panel 100, and of course, other special-shaped display panels 100 may be used as long as the steps 30 are formed by the display panel 100 having different numbers of adjacent two pixel rows 10 or different numbers of pixels PX in adjacent two pixel columns 20. In fig. 3, only the non-display area BB completely surrounds the display area AA, but the non-display area BB may also partially surround the display area AA, such as a water droplet screen or Liu Haibing, which is not limited herein. The number of pixels PX in fig. 3 is only schematically illustrated, and is not a limitation of the actual product.
Also shown in fig. 4 are signal lines (not shown in fig. 3) in the package region 2 and first pads 51 (shown in fig. 3 and 4) in the bonding region 1, and of course, a flexible circuit board may be bonded in the bonding region 1, and second pads 52 on the flexible circuit board are electrically connected to the first pads 51 in a one-to-one correspondence. In this embodiment, a Chip On Film (COF) is taken as an example, that is, a driving chip IC is fixed on a die pad on a flexible circuit board, and a flexible additional circuit board is used as a package chip carrier to combine a chip with a flexible substrate circuit, or a flexible additional circuit board of a single-finger unpackaged chip; of course, the flexible circuit board in the present invention may also have no driving chip IC, and the driving chip IC may be directly manufactured in the binding area 1 of the display panel 100 at this time, that is, the COG technology.
The display area AA in the present embodiment includes a plurality of pixel rows 10 and a plurality of pixel columns 20, each pixel row 10 is composed of pixels PX arranged in a row direction X, each pixel column 20 is composed of pixel columns 20 arranged in a column direction Y, and the display panel 100 includes data lines (not shown) extending in the row direction X and scan lines (not shown) extending in the row direction X. As can be seen from fig. 4, the number of pixels PX in the pixel row 1001 and the pixel row 1002 is not equal, the number of pixels PX in the pixel row 1002 and the pixel row 1003 is not equal, the number of pixels PX in the pixel row 1003 and the pixel row 1004 is not equal, the number of pixels PX in the pixel row 1001 is exactly smaller than the number of pixels PX in the pixel row 1002, the number of pixels PX in the pixel row 1002 is smaller than the number of pixels PX in the pixel row 1003, whereby a step 30 is formed at the positions of the pixel row 1001 and the pixel row 1002, and the positions of the pixel row 1002 and the pixel row 1003; of course, it is also considered that the step 30 is formed by two adjacent pixel columns 20, specifically, the number of pixels PX in the pixel columns 2001 and 2002 is not equal, the number of pixels PX in the pixel columns 2003 and 2004 is not equal, the number of pixels PX in the pixel columns 2005 and 2006 is not equal, specifically, the number of pixels PX in the pixel columns 2001 is less than the number of pixels PX in the pixel columns 2002, the number of pixels PX in the pixel columns 2003 is less than the number of pixels PX in the pixel columns 2004, and the number of pixels PX in the pixel columns 2005 is less than the number of pixels PX in the pixel columns 2006, thereby forming the step 30.
The non-display area BB includes a first non-display area BB1, the first non-display area BB1 is adjacent to the step 30, as shown in fig. 3 and 4, along the column direction Y, the first non-display area BB1 corresponds to and is adjacent to the step 30, the first non-display area BB1 includes an electrostatic protection area 40, the electrostatic protection area 40 includes an electrostatic protection circuit 400, and the electrostatic protection circuit 400 is configured to conduct static electricity in the display panel 100 to prevent static electricity from entering the display panel 100 to generate electrostatic breakdown, which affects the performance of the display panel 100. The multiplexer 60 is included between the parts of the esd protection circuit 400 of the esd protection area 40, and in order to reduce the number of pads of the driver chip IC, the multiplexer 60 is generally used to supply signals to a plurality of data lines through a signal line, the signal line is connected to the plurality of data lines through a switch, and the reception of data signals on the corresponding data lines is controlled through the switch.
In fig. 4, along the column direction Y, the lengths of the multiplexer 60 and the electrostatic protection circuit 400 in the first non-display area BB1 in the column direction Y are not identical, and of course, only the length of the electrostatic protection circuit 400 in the column direction Y is greater than the length of the multiplexer 60 in the column direction Y, and of course, the length of the electrostatic protection circuit 400 in the column direction Y may be equal to the length of the multiplexer 60 in the column direction Y, which is not limited herein.
It can be understood that in this embodiment, the electrostatic protection circuit 400 originally disposed in the step area 3 is disposed in the first non-display area BB1 corresponding to the step 30, where the step 30 is formed by unequal numbers of pixels PX in the adjacent pixel rows 10 or the adjacent pixel columns 20, so that only the multiplexer 60 is disposed in the step area 3, and the space corresponding to the step 30 in the lower frame 801 is fully utilized, and of course, the multiplexer 60 can be in one-to-one correspondence with the pixel columns 20 as much as possible, so as to reduce the number of windings, thereby reducing the width of the fanout routing area 4 in the longitudinal direction, and further compressing the lower frame 801 to realize a narrow frame; on the other hand, the portion of the multiplexer 60 originally provided entirely in the step area 3 is transferred to the first non-display area BB1, so that the pitch of the multiplexer 60 in the step area 3 can be further increased to be in one-to-one correspondence with the pixel columns 20. Furthermore, since the width of the first non-display area BB1 in the column direction Y is larger than the width of the step area 3 in the column direction Y corresponding to the position of the step 30, the width in the column direction Y is sufficient to arrange the electrostatic protection circuit 400, and the length of the electrostatic protection circuit 400 in the column direction Y can be set larger, thereby maximizing the space utilization.
In some alternative embodiments, with continued reference to fig. 4, the electrostatic protection circuit 400 is arranged along the row direction X and extends along the column direction Y.
As can be seen from fig. 4, the first non-display area BB1 is adjacent to the step area 3 in the row direction X, so that the area is parallel to the step area 3, the arrangement direction of the electrostatic protection circuit 400 in the area may be the same as the arrangement direction of the multiplexer 60 in the step area 3, and the electrostatic protection circuit 400 in the area does not need to be rotated or tilted, which is more beneficial to manufacturing.
In some alternative embodiments, with continued reference to fig. 4, the multiplexers 60 are arranged along the row direction X and extend along the column direction Y.
As can be seen from fig. 4, the first non-display area BB1 is adjacent to the step area 3 in the row direction X, so that the first non-display area BB1 is parallel to the step area 3, the arrangement direction of the multiplexers 601 in the first non-display area BB1 may be the same as the arrangement direction of the multiplexers 602 in the step area 3, or the length of the multiplexers 601 in the column direction Y in the first non-display area BB1 may be the same as the length of the multiplexers 602 in the column direction Y in the step area 3, or the width of the multiplexers 601 in the row direction X in the first non-display area BB1 may be the same as the width of the multiplexers 602 in the row direction X in the step area 3, so that the multiplexers 60 in the two areas may be fabricated simultaneously, thereby reducing the fabrication difficulty.
In some alternative embodiments, referring to fig. 5, 6 and 7, fig. 5 is a further enlarged partial view of the N region in fig. 3, fig. 6 is a further enlarged partial view of the N region in fig. 3, and fig. 7 is a further enlarged partial view of the N region in fig. 3, with the electrostatic protection circuit 400 alternating with the multiplexer 60 in the row direction X.
Referring to fig. 5 to 7, the electrostatic protection circuits 400 and the multiplexers 60 of the first non-display area BB1 in fig. 5 are alternately arranged one by one, the electrostatic protection circuits 400 and the multiplexers 60 of the first non-display area BB1 in fig. 6 are alternately arranged two by two, the electrostatic protection circuits 400 and the multiplexers 60 of the first non-display area BB1 in fig. 7 are alternately arranged two by two, that is, two electrostatic protection circuits 400, three multiplexers 60, three electrostatic protection circuits 400 and one multiplexer 60 are arranged along the direction of the first non-display area BB1 toward the step area 3, though the number of alternately arranged electrostatic protection circuits 400 and multiplexers 60 is not particularly limited, of course, the arrangement modes of the electrostatic protection circuit 400 and the multiplexer 60 are not particularly limited, and only the electrostatic protection circuit 400 and the multiplexer 60 are required to be arranged in the electrostatic protection area 40, and the electrostatic protection circuit 400 and the multiplexer 60 which are originally all arranged in the step area 3 are partially arranged in the first non-display area BB1 corresponding to the step 30, so that only the multiplexer 60 is arranged in the step area 3, the space corresponding to the step 30 in the lower frame 801 is fully utilized, the multiplexer 60 can be in one-to-one correspondence with the pixel columns 20 as many as possible, the number of windings is reduced, and the width of the fanout routing area 4 in the longitudinal direction is reduced, and therefore the lower frame 801 can be further compressed, and a narrow frame is realized.
In some alternative embodiments, referring to fig. 8, fig. 8 is a further enlarged partial view of the N region in fig. 3, the step 30 of the present embodiment includes adjacent first and second steps 301 and 302, the number of pixels PX in the pixel row 10 of the first step 301 is m, the number of pixels PX in the pixel row 10 of the second step 302 is N, m and N are both positive integers, and m is greater than N;
the first non-display area BB1 includes a first sub non-display area BB11 and a second sub non-display area BB12, the first sub non-display area BB11 being adjacent to the first step 301 and the second sub-non-display area BB12 being adjacent to the second step 302;
the electrostatic protection region 40 of the first sub non-display region BB11 includes a first electrostatic protection circuit 401; the electrostatic protection region 40 of the second sub-non-display region BB12 includes a second electrostatic protection circuit 402;
in the row direction X, the width of the first electrostatic protection circuit 401 is smaller than the width of the second electrostatic protection circuit 402;
in the column direction Y, the length of the first electrostatic protection circuit 401 is greater than the length of the second electrostatic protection circuit 402.
Referring to fig. 8, the steps 30 include adjacent first steps 301 and second steps 302, the number of pixels PX in the pixel row 10 of the first steps 301 is different from the number of pixels PX in the pixel row 10 of the second steps 302, the number of pixels PX in the pixel row 10 of the first steps 301 is m, the number of pixels PX in the pixel row 10 of the second steps 302 is n, and m is greater than n, that is, the distance between the first steps 301 and the binding area 1 is greater than the distance between the second steps 302 and the binding area 1, the space of the corresponding first sub-non-display area BB11 in the column direction Y is greater than the distance between the second sub-non-display area BB12 in the column direction Y, the electrostatic protection area 40 of the first sub-non-display area BB11 includes the first electrostatic protection circuit 401, the electrostatic protection area 40 of the second sub-non-display area BB12 includes the second electrostatic protection circuit 402, and the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 both extend in the column direction Y along the column direction X, that is, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 are not arranged in rotation.
The optional first sub non-display area BB11 is located on the side of the second sub non-display area BB12 remote from the step area 3, i.e. the second sub non-display area BB12 is adjacent to the step area 3. In this embodiment, only the width of the first multiplexer 60a in the first sub non-display area BB11 in the row direction X and the width of the second multiplexer 60b in the second sub non-display area BB12 in the row direction X are schematically shown to be unequal, and the length of the first multiplexer 60a in the first sub non-display area BB11 in the column direction Y and the length of the second multiplexer 60b in the second sub non-display area BB12 in the column direction Y are not equal, however, the width of the first multiplexer 60a in the first sub non-display area BB11 in the row direction X and the width of the second multiplexer 60b in the second sub non-display area BB12 in the row direction X are not equal, and the length of the first multiplexer 60a in the first sub non-display area BB11 in the column direction Y and the length of the second multiplexer 60b in the second sub-display area BB12 are not specifically limited thereto.
In fig. 8, the second step 302 is located at the pixel row 1001 and the pixel row 1002, and the first step 301 is located at the pixel row 1002 and the pixel row 1003, so that the length of the first electrostatic protection circuit 401 in the column direction Y may be set larger, that is, the length of the first electrostatic protection circuit 401 in the column direction Y is greater than the length of the second electrostatic protection circuit 402 in the column direction Y, but in order to ensure the integrity of the electronic components in the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402, the width of the first electrostatic protection circuit 401 in the row direction X is smaller than the width of the second electrostatic protection circuit 402 in the row direction X, so that both the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 can play a role of electrostatic protection.
Of course, the present embodiment also has the technical effects of any one of the above embodiments, which will not be described in detail herein, and in addition, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 with different widths and lengths are respectively configured by fully utilizing the spatial differences of the first sub-non-display area BB11 and the second sub-non-display area BB12 in the column direction Y in the present embodiment.
In some alternative embodiments, referring to fig. 9, fig. 9 is a further enlarged partial view of the region N in fig. 3, the electrostatic protection region 40 of the first sub-non-display area BB11 further includes a first multiplexer 60a, and the electrostatic protection region 40 of the second sub-non-display area BB12 further includes a second multiplexer 60b;
in the row direction X, the width of the first multiplexer 60a is equal to the width of the second multiplexer 60b; in the column direction Y, the length of the first multiplexer 60a is equal to the length of the second multiplexer 60 b.
Referring to fig. 9, the electrostatic protection region 40 of the first sub non-display region BB11 further includes a first multiplexer 60a, the first multiplexer 60a being between the first electrostatic protection circuits 401, and the electrostatic protection region 40 of the second sub non-display region BB12 further includes a second multiplexer 60b, the second multiplexer 60b being between the second electrostatic protection circuits 402, the width of the first multiplexer 60a in the row direction X being equal to the width of the second multiplexer 60b in the row direction X, the length of the first multiplexer 60a in the column direction Y being equal to the length of the second multiplexer 60b in the column direction Y, so that the first multiplexer 60a and the second multiplexer 60b can be fabricated simultaneously, simplifying the fabrication process.
Alternatively, the first multiplexer 60a and the second multiplexer 60b may be fabricated simultaneously with the multiplexer 60 in the step region 3, and the width in the row direction X and the length in the column direction Y are both equal, which facilitates fabrication and further simplifies the fabrication process.
In some alternative embodiments, with continued reference to fig. 3 and 8, the non-display area BB includes an upper border 802 and a lower border 801 disposed opposite along the column direction Y;
the display panel 100 includes K pixel rows 10, the lower frame 801 includes a step area 3 and a fanout line area 4, and a first non-display area BB1, the fanout line area 4 is located between the step area 3 and the kth pixel row 10 along the column direction Y, and the second step 302 is located at a side of the first step 301 close to the fanout line area 4 along the row direction X;
the step area 3 includes a third multiplexer 60c, and the width of the third multiplexer 60c is greater than the width of the second multiplexer 60b in the row direction X; in the column direction Y, the length of the third multiplexer 60c is smaller than the length of the second multiplexer 60 b.
Referring to fig. 3, the display panel 100 includes K pixel rows 10, the lower frame 801 includes a step area 3 and a fanout line area 4, and a first non-display area BB1, the fanout line area 4 is located between the step area 3 and the kth pixel row 10 along the column direction Y, that is, the fanout line area 4 is adjacent to the last row of pixel rows 10 along the row direction X, the second step 302 is located at a side of the first step 301 near the fanout line area 4, the second sub-non-display area BB12 of the first non-display area BB1 is located at a side of the first sub-non-display area BB11 of the first non-display area BB1 near the step area 3, a third multiplexer 60c is disposed in the step area 3, and a width of the third multiplexer 60c is greater than a width of the second multiplexer 60b along the row direction X; in the column direction Y, the length of the third multiplexer 60c is smaller than the length of the second multiplexer 60b, and as shown in fig. 8, in the row direction X, since part of the multiplexers 60 in the step region 3 are disposed in the first non-display region BB1, the space in the step region 3 in the row direction X is sufficient, and at this time, in the row direction X, the width of the third multiplexer 60c is larger than the width of the second multiplexer 60b, and the length in the column direction Y of the second sub-non-display region BB12 is larger than the length in the column direction Y of the step region 3, the length in the column direction Y of the second multiplexer 60b may be larger than the length in the column direction Y of the third multiplexer 60 c. Thereby fully utilizing the space of the second sub non-display section BB12 adjacent to the step section 3.
In some alternative embodiments, referring to fig. 10 and 11, fig. 10 is a schematic plan view of still another display panel according to the present invention; fig. 11 is a partial enlarged view of the Q region in fig. 10, and the non-display region BB further includes a gate drive circuit 90;
the non-display area BB further includes a gate driving signal line X11 surrounding the display area AA, the gate driving signal line X11 being electrically connected to the gate driving circuit 90 and the electrostatic protection circuit 400, respectively.
The gate driving signal line X11 is not shown in fig. 10, and the gate driving circuit 90 is used to realize progressive scanning of scanning lines in the pixels PX, and for the circular display panel 100, the axes of the gate driving circuits 90 in the left frame 803 and the right frame 804 need to match the diameter of the circular display panel 100, i.e., the gate driving circuit 90 is rotated to some extent. Static electricity is generated during the process of manufacturing the display panel 100, so the static electricity protection circuits 400 are arranged on the gate driving signal lines X11, and in one embodiment, each static electricity protection circuit 400 is connected with a different gate driving signal line X11, that is, the number of the static electricity protection circuits 400 corresponds to the number of the gate driving signal lines X11 one by one, so that each gate driving signal line X11 can realize static electricity protection, and the static electricity protection circuit can be arranged according to the requirement of static electricity protection, which is not limited in the application.
In some alternative embodiments, referring to fig. 12, fig. 12 is a plan view of the electrostatic protection circuit of fig. 11, fig. 13 is a cross-sectional view taken along the direction K-K ' in fig. 11, fig. 14 is a further cross-sectional view taken along the direction K-K ' in fig. 11, and fig. 15 is a further cross-sectional view taken along the direction K-K ' in fig. 11.
The display panel 100 includes a substrate C01, a first metal layer C03 located on one side of the substrate C01, a capacitor metal layer C04 located on a side of the first metal layer C03 away from the substrate C01, a second metal layer C05 located on a side of the capacitor metal layer C04 away from the substrate C01, a third metal layer C06 located on a side of the second metal layer C05 away from the substrate C01, a gate driving signal line X11 and the second metal layer C05 are in the same layer, the electrostatic protection circuit 400 includes a first transistor T1 and a second transistor T2 connected in parallel, a drain electrode of the first transistor T1 and a drain electrode of the second transistor T2 are electrically connected to the gate driving signal line X11 through a first conductive portion DD, the first conductive portion DD and the first metal layer C03 are in the same layer, or the first conductive portion DD and the capacitor metal layer C04 are in the same layer, or the first conductive portion DD and the third metal layer C06 are in the same layer.
It is to be understood that, since the gate driving signal line X11 is generally located in the second metal layer C05, the first conductive portion DD needs to be disposed in the same layer as the first metal layer C03, or the capacitor metal layer C04, or the third metal layer C06, that is, the first conductive portion DD cannot be disposed in the second metal layer C05. Fig. 13 to 15 schematically show the structure of each film layer in the display panel 100, which includes a substrate C01, a first metal layer C03 located on one side of the substrate C01, a capacitor metal layer C04 located on one side of the first metal layer C03 away from the substrate C01, a second metal layer C05 located on one side of the capacitor metal layer C04 away from the substrate C01, and a third metal layer C06 located on one side of the second metal layer C05 away from the substrate C01, and of course, an insulating layer is further included between the first metal layer C03, the capacitor metal layer C04, the second metal layer C05, and the third metal layer C06, and the display panel further includes an active layer C02, that is, an active layer C02 of the first transistor T1 and the second transistor T2. The display panel further includes a driving transistor T for driving the light emitting element EM to emit light, and a light emitting element EM including an anode C07, a light emitting layer C08, and a cathode C09, wherein the encapsulation layer C10 in fig. 13-15 is used for encapsulation to prevent water oxygen from entering the panel, and optionally a touch layer (not shown) may be further disposed on a side of the encapsulation layer C01 away from the side C01 of the substrate, a first conductive portion DD is disposed on the first metal layer C03 in fig. 13, and the first conductive portion DD is electrically connected to the gate driving signal line X11 through a via hole, the first conductive portion DD is disposed on the capacitor metal layer C04 in fig. 14, and the first conductive portion DD is disposed on the third metal layer C06 in fig. 15.
The electrostatic protection circuit 400 includes a first transistor T1 and a second transistor T2, where the gate of the first transistor T1 and the source of the first transistor T1 are electrically connected to the high potential signal line VGH, the drain of the first transistor T1 is electrically connected to the gate driving signal line X11, the gate of the second transistor T2 and the drain of the second transistor T2 are electrically connected to the gate driving signal line X11, the source of the second transistor T2 is electrically connected to the low potential signal line VGL, the optional first transistor T1 and second transistor T2 are P-type transistors, the drain of the first transistor T1 and the drain of the second transistor T2 are electrically connected to the gate driving signal line X11 through the first conductive portion DD, when static electricity accumulated in the gate driving signal line X11 is at a low potential, the gate of the second transistor T2 is turned on at this time, if the potential on the gate driving signal line X11 is at a negative potential and lower than the low potential signal line VGL, and current flows from the gate driving signal line X11 to the low potential signal line VGL, so that static electricity is removed from the gate driving signal line VGL to the low potential line VGL. When the potential of the gate driving signal line X11 is high and higher than the potential of the high potential signal line VGH, the gate-source voltage difference of the first transistor T1 is positive, the first transistor T1 is turned on, and a current flows from the gate driving signal line X11 to the high potential signal line VGH, so that the potential of the gate driving signal line X11 is pulled down to be equal to the high potential signal line VGH, and static charge is eliminated.
In some alternative embodiments, with continued reference to fig. 11-15, and with reference to fig. 16, fig. 16 is a partial enlarged view of the first and second sub-non-display regions of fig. 9, and the gate driving signal line X11 includes a trigger signal line, a clock signal line of the gate driving circuit 90, and a test signal line for testing an output signal of the gate driving circuit 90.
It is understood that the gate driving signal line X11 includes trigger signal lines (STV 1 and STV 2) of two gate driving circuits, four clock signal lines (CK 1, CK2, XCK1, XCK 2), and two test signal lines (SOUT 1, SOUT 2) for testing output signals of the gate driving circuits, and then 8 electrostatic protection circuits are required to be provided in one-to-one correspondence with the gate driving signal line X11 to achieve electrostatic protection of the gate driving signal line X11.
In some alternative embodiments, with continued reference to FIG. 8, in the column direction Y, the first electrostatic protection circuit 401 has a length L1, 200 μm L1 250 μm, and the second electrostatic protection circuit 402 has a length L2, 100L 2 < 200 μm.
As described above, the space of the first sub non-display area BB11 in the column direction Y may be greater than the distance of the second sub non-display area BB12 in the column direction Y, and optionally, the length of the first electrostatic protection circuit 401 in the first sub non-display area BB11 in the column direction Y may be greater than the length of the second electrostatic protection circuit 402 in the second sub non-display area BB12 in the column direction Y, and in the column direction Y, the length of the first electrostatic protection circuit 401 may be L1, 200 μm or less L1 or less 250 μm, and the length of the second electrostatic protection circuit 402 may be L2, 100 or less L2 or less 200 μm, so that the space requirements of the first sub non-display area BB11 and the second sub non-display area BB12 in the column direction Y may be satisfied.
In some alternative embodiments, with continued reference to fig. 3 and with reference to fig. 17, fig. 17 is a schematic plan view of yet another display panel provided by the present invention, and the shape of the display area AA includes a circular shape or a rounded rectangle shape.
The display area of the display panel in fig. 3 is circular, the display area of the display panel in fig. 17 is rounded rectangle, and steps are formed at the positions of the rounded corners R, and the setting manner of the electrostatic protection circuit can refer to the embodiment in fig. 3, which is not repeated here. As long as the steps are formed when the number of pixels in the adjacent two pixel rows is not equal or the number of pixels in the adjacent two pixel columns is not equal, the static electricity protection region may be disposed in the first non-display region adjacent to the steps.
The embodiment also provides a display device including the display panel. Referring to fig. 18, fig. 18 is a schematic plan view of a display device according to the present invention. Fig. 18 provides a display device 1000 including a display panel 100, where the display panel 100 is the display panel 100 provided in any of the above embodiments of the present invention. The embodiment of fig. 18 only uses an intelligent wearable device as an example to describe the display device 1000, and it can be understood that the display device 1000 provided in the embodiment of the present invention may be other display devices 1000 with display functions, such as a computer, a television, a vehicle-mounted display panel, etc., which is not particularly limited in the present invention. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and the specific description of the display panel in each of the above embodiments may be referred to specifically, and this embodiment is not repeated here.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
a display panel of the present invention includes: a non-display region including a display region and at least partially surrounding the display region; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form the steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. The lower frame area of the display panel is provided with a step area and a fan-out wiring area, the fan-out wiring area is positioned between the step area and the display area, and a multiplexer and an electrostatic protection circuit are required to be arranged in the step area. According to the invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the step, the step is formed by unequal pixel numbers in adjacent pixel rows or adjacent pixel columns, so that only the multiplexer is arranged in the step area, the space corresponding to the step position in the lower frame is fully utilized, and of course, the multiplexer can be in one-to-one correspondence with the pixel columns as much as possible, the number of windings is reduced, and the width of the fanout line area in the longitudinal direction is reduced, so that the lower frame can be further compressed, and a narrow frame is realized.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (12)
1. A display panel, comprising: a display region and a non-display region at least partially surrounding the display region;
the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form the steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps;
the first non-display region includes an electrostatic protection region including a plurality of electrostatic protection circuits and a multiplexer located between a portion of the electrostatic protection circuits;
the steps comprise a first step and a second step which are adjacent, the number of pixels in the pixel row of the first step is m, the number of pixels in the pixel row of the second step is n, m and n are positive integers, and m is larger than n;
the first non-display area comprises a first sub-non-display area and a second sub-non-display area, the first sub-non-display area is adjacent to the first step, and the second sub-non-display area is adjacent to the second step;
the electrostatic protection area of the first sub-non-display area comprises a first electrostatic protection circuit; the electrostatic protection area of the second sub-non-display area comprises a second electrostatic protection circuit;
the width of the first electrostatic protection circuit is smaller than that of the second electrostatic protection circuit along the row direction;
along the column direction, the length of the first electrostatic protection circuit is longer than that of the second electrostatic protection circuit.
2. The display panel according to claim 1, wherein the static electricity protection circuit is arranged in the row direction to extend in the column direction.
3. The display panel of claim 2, wherein the multiplexers are arranged in the row direction extending in the column direction.
4. A display panel according to claim 3, wherein the electrostatic protection circuits are alternately arranged with the multiplexers in the row direction.
5. The display panel of claim 4, wherein the static electricity protection area of the first sub-non-display area comprises a first multiplexer, and the static electricity protection area of the second sub-non-display area comprises a second multiplexer;
the width of the first multiplexer is equal to the width of the second multiplexer along the row direction; along the column direction, the length of the first multiplexer is equal to the length of the second multiplexer.
6. The display panel of claim 5, wherein the non-display area includes an upper bezel and a lower bezel disposed opposite along the column direction;
the display panel comprises K pixel rows, the lower frame comprises a step area, a fanout wiring area and the first non-display area, the fanout wiring area is positioned between the step area and the K pixel row along the column direction, and the second step is positioned at one side, close to the fanout wiring area, of the first step along the row direction;
the step region includes a third multiplexer having a width in the row direction that is greater than a width of the second multiplexer; the length of the third multiplexer is smaller than the length of the second multiplexer along the column direction.
7. The display panel of claim 1, wherein the non-display region further comprises a gate driving circuit;
the non-display region further includes a gate driving signal line surrounding the display region, the gate driving signal line being electrically connected to the gate driving circuit and the electrostatic protection circuit, respectively.
8. The display panel according to claim 7, further comprising a substrate, a first metal layer located on a side of the substrate, a capacitance metal layer located on a side of the first metal layer away from the substrate, a second metal layer located on a side of the capacitance metal layer away from the substrate, a third metal layer located on a side of the second metal layer away from the substrate, the gate driving signal line and the second metal layer being in the same layer, wherein the electrostatic protection circuit comprises a first transistor and a second transistor connected in parallel, a drain of the first transistor and a drain of the second transistor being electrically connected to the gate driving signal line through a first conductive portion, the first conductive portion and the first metal layer being in the same layer, or the first conductive portion and the capacitance metal layer being in the same layer, or the first conductive portion and the third metal layer being in the same layer.
9. The display panel according to claim 7, wherein the gate driving signal line includes a trigger signal line of a gate driving circuit, a clock signal line, and a test signal line for testing an output signal of the gate driving circuit.
10. The display panel according to claim 1, wherein a length of the first electrostatic protection circuit is L1, 200 μm is L1 is 250 μm along the column direction, and a length of the second electrostatic protection circuit is L2, 100 is L2 is less than 200 μm.
11. The display panel of claim 1, wherein the shape of the display area comprises a circular shape or a rounded rectangle shape.
12. A display device comprising the display panel according to any one of claims 1 to 11.
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| CN114937420A (en) | 2022-08-23 |
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