CN114937420A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN114937420A CN114937420A CN202210594426.9A CN202210594426A CN114937420A CN 114937420 A CN114937420 A CN 114937420A CN 202210594426 A CN202210594426 A CN 202210594426A CN 114937420 A CN114937420 A CN 114937420A
- Authority
- CN
- China
- Prior art keywords
- display area
- display
- electrostatic protection
- area
- multiplexer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000012360 testing method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000005611 electricity Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 238000004804 winding Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000005525 hole transport Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101000805729 Homo sapiens V-type proton ATPase 116 kDa subunit a 1 Proteins 0.000 description 1
- 101000854879 Homo sapiens V-type proton ATPase 116 kDa subunit a 2 Proteins 0.000 description 1
- 101000854873 Homo sapiens V-type proton ATPase 116 kDa subunit a 4 Proteins 0.000 description 1
- 102100020737 V-type proton ATPase 116 kDa subunit a 4 Human genes 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0067—Devices for protecting against damage from electrostatic discharge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
Abstract
The invention discloses a display panel and a display device, comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. The electrostatic protection area is arranged at the step, so that the non-display area can be further compressed in the column direction, and a narrow frame is realized.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The conventional display devices include displays, televisions, mobile phones, tablet computers, and the like, and with the development of electronic technology, the manufacture of display panels is mature, and the display panels provided in the prior art include liquid crystal display panels, organic light emitting display panels, plasma display panels, and the like.
As a Display panel with a mature manufacturing process at present, a Liquid Crystal Display (LCD) occupies a large market in the field of Display panels with low cost, good manufacturing yield and good Display effect. The liquid crystal display device has the advantages of thin body, electricity saving, no radiation and the like, is widely applied, such as a liquid crystal television, a mobile phone, a personal digital assistant, a digital camera, a computer screen or a notebook computer screen and the like, and is dominant in the field of flat panel display; organic Light Emitting Diodes (OLEDs) are increasingly used in high performance display as a current-mode light emitting device, and OLED display panels have many excellent characteristics such as self-luminescence, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panels, rich colors, flexible display, and wide operating temperature range, and are therefore known as "star" flat panel display technologies of the next generation. The OLED display panel comprises an anode, a cathode, a hole transport layer, an organic light emitting layer and an electron transport layer, wherein the hole transport layer, the organic light emitting layer and the electron transport layer are arranged between the anode and the cathode, the anode provides hole injection, the cathode provides electron injection, holes and electrons injected by the cathode and the anode are compounded in the organic light emitting layer under the driving of an external voltage to form electron-hole pairs (namely excitons) at bound energy levels, and the excitons radiate and de-excite to emit photons to generate visible light.
In recent years, intelligent wearable devices are increasingly favored by users due to advantages such as portability and fashionable beauty. With the application of display technology in intelligent wearing and other portable electronic devices, the appearance of the display panel is required to be diversified, and accordingly, the special-shaped display panel appears.
In order to increase the aesthetic feeling of the display image and the appearance of the intelligent wearable device, the display panel of the intelligent wearable device has higher and higher requirements on the narrow frame, but the display panel in the related art cannot compress the lower frame, so that the narrow frame is prevented from being realized.
Therefore, it is desirable to provide a display panel and a display device to realize a narrow bezel.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display apparatus to realize a narrow bezel.
In one aspect, the present invention provides a display panel, comprising: comprising a display area and a non-display area at least partially surrounding the display area;
the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the steps are formed by the unequal number of pixels in two adjacent pixel rows or the unequal number of pixels in two adjacent pixel columns, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps;
the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits.
In another aspect, the invention further provides a display device comprising the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
a display panel of the present invention includes: comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the steps are formed by the unequal number of pixels in two adjacent pixel rows or the unequal number of pixels in two adjacent pixel columns, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. All have step district and fan-out wiring district in display panel's lower frame region, fan-out wiring district is located between step district and the display area, multiplexer and electrostatic protection circuit need to set up in the step district, because the electrostatic protection circuit here has taken the space of horizontal direction, so the multiplexer can not be with the pixel row one-to-one in the display area, must realize through wire-wound mode and be connected with the data line or the touch-control line electricity in the display area, the wire-wound can occupy fore-and-aft space, also can't compress the lower frame on longitudinal direction, the lower frame has been hindered and the narrow frame is realized. According to the invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the steps, the steps are formed due to the fact that the number of pixels in adjacent pixel rows or adjacent pixel columns is different, only the multiplexer is arranged in the step area, the space of the lower frame corresponding to the step position is fully utilized, the multiplexer can be in one-to-one correspondence with the pixel columns as much as possible, the number of winding wires is reduced, the width of the fan-out wiring area in the longitudinal direction is reduced, and therefore the lower frame can be further compressed, and the narrow frame is realized.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic plan view of a display panel in the related art;
FIG. 2 is an enlarged view of a portion of the area M in FIG. 1;
FIG. 3 is a schematic plane structure diagram of a display panel according to the present invention;
FIG. 4 is an enlarged view of a portion of the area N of FIG. 3;
FIG. 5 is a further enlarged view of a portion of the area N in FIG. 3;
FIG. 6 is a further enlarged view of a portion of the area N in FIG. 3;
FIG. 7 is a further enlarged view of a portion of the area N in FIG. 3
FIG. 8 is a further enlarged partial view of the area N in FIG. 3;
FIG. 9 is a further enlarged fragmentary view of area N of FIG. 3;
FIG. 10 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 11 is an enlarged partial view of the area Q of FIG. 10;
FIG. 12 is a plan view of the electrostatic protection circuit of FIG. 11;
FIG. 13 is a cross-sectional view taken along line K-K' of FIG. 11;
FIG. 14 is a further sectional view taken along line K-K' of FIG. 11;
FIG. 15 is a further sectional view taken along line K-K' of FIG. 11;
fig. 16 is a partially enlarged view of a first sub non-display area and a second sub non-display area in fig. 9;
FIG. 17 is a schematic plan view of a display panel according to another embodiment of the present invention;
fig. 18 is a schematic plan view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In view of the problem that the display panel of the related art has difficulty in compressing the lower frame, the inventors have conducted the following studies on the related art: referring to fig. 1, fig. 1 is a schematic plan view of a display panel in the related art, fig. 2 is a partial enlarged view of an area M in fig. 1, the display panel in fig. 1 may be an intelligent wearable device and may be circular, the display panel 0000 includes a display area AA and a non-display area BB surrounding the display area AA, the non-display area includes a lower bezel 801, the lower bezel 801 includes a bonding area 01, a packaging area 02, a step area 03 and a fan-out routing area 04, a multiplexer 050 and an electrostatic protection circuit 0400 are required to be disposed in the step area 03, as shown in fig. 2, an output end of the multiplexer 050 is electrically connected to data lines in the display area AA, and since more multiplexers 050 and electrostatic protection circuits 0400 are required to be disposed in the step area 03, a pitch of the multiplexer 050 in a row direction X is not equal to a pitch of pixels PX, that is, the multiplexers and columns of pixels 050 in a column direction Y do not have a one-to one correspondence relationship, therefore, in the fan-out routing area 04, it is necessary to have a routing line electrically connected to the data line in the display area AA, and the routing line is arranged in the column direction Y, so that the lower frame cannot be compressed in the column direction Y.
In order to solve the above technical problems, the present invention provides a display panel and a display device, and specific embodiments of the display panel and the display device will be described in detail below.
Referring to fig. 3 and 4, fig. 3 is a schematic plan view of a display panel according to the present invention, and fig. 4 is a partial enlarged view of an N region in fig. 3. The display panel 100 provided in the present embodiment includes: comprises a display area AA and a non-display area BB at least partially surrounding the display area AA;
the display area AA includes a plurality of pixel rows 10 and a plurality of pixel columns 20, a periphery of the display area AA includes a plurality of steps 30, the number of pixels PX in adjacent two pixel rows 10 is unequal or the number of pixels PX in adjacent two pixel columns 20 is unequal to form the steps 30, the non-display area BB includes a first non-display area BB1, the first non-display area BB1 is adjacent to the steps 30;
the first non-display area BB1 includes an esd protection area 40, the esd protection area 40 includes a plurality of esd protection circuits 400, and a multiplexer 60 is included between some of the esd protection circuits 400.
Specifically, in fig. 3, the display panel 100 is only illustrated as a circular display panel 100, but it is needless to say that other irregular display panels 100 may be adopted as long as the display panel 100 has a step 30 formed by the unequal number of the pixels PX in the two adjacent pixel rows 10 or the unequal number of the pixels PX in the two adjacent pixel columns 20. In fig. 3, only the non-display area BB completely surrounds the display area AA, but the non-display area BB may also partially surround the display area AA, such as a water drop screen or a bang screen, and is not limited herein. The number of pixels PX in fig. 3 is only an exemplary illustration and is not a limitation of an actual product.
Also shown in fig. 4 are signal lines (not shown in fig. 3) in the package region 2 and first pads 51 (shown in fig. 3 and 4) in the bonding region 1, although the flexible circuit board may be bonded in the bonding region 1, and the second pads 52 on the flexible circuit board are electrically connected to the first pads 51 in a one-to-one correspondence. In this embodiment, a Chip On Film (COF) is taken as an example, that is, a driving chip IC is fixed on a die flex on a flexible circuit board, and a flexible additional circuit board is used as a package chip carrier to combine a chip and a flexible substrate circuit, or a single flexible additional circuit board without a packaged chip; of course, the flexible circuit board of the present invention may also have no driver IC, and the driver IC may be directly disposed in the bonding region 1 of the display panel 100, that is, the COG technology.
The display area AA in the present embodiment includes a plurality of pixel rows 10 and a plurality of pixel columns 20, each pixel row 10 is composed of pixels PX arranged in a row direction X, each pixel column 20 is composed of pixel columns 20 arranged in a column direction Y, and of course the display panel 100 further includes data lines (not shown in the figure) extending in the row direction X and scan lines (not shown in the figure) extending in the row direction X. As can be seen from fig. 4, the number of pixels PX in the pixel row 1001 and the pixel row 1002 are not equal, the number of pixels PX in the pixel row 1002 and the pixel row 1003 are not equal, and the number of pixels PX in the pixel row 1003 and the pixel row 1004 are not equal, specifically, the number of pixels PX in the pixel row 1001 is less than the number of pixels PX in the pixel row 1002, and the number of pixels PX in the pixel row 1002 is less than the number of pixels PX in the pixel row 1003, thereby forming a step 30 at the positions of the pixel row 1001 and the pixel row 1002, and at the positions of the pixel row 1002 and the pixel row 1003; it is needless to say that the step 30 is formed by two adjacent pixel columns 20, specifically, the number of pixels PX in the pixel column 2001 and the pixel column 2002 is not equal, the number of pixels PX in the pixel column 2003 and the pixel column 2004 is not equal, the number of pixels PX in the pixel column 2005 and the pixel column 2006 is not equal, specifically, the number of pixels PX in the pixel column 2001 is smaller than the number of pixels PX in the pixel column 2002, the number of pixels PX in the pixel column 2003 is smaller than the number of pixels PX in the pixel column 2004, and the number of pixels PX in the pixel column 2005 is smaller than the number of pixels PX in the pixel column 2006, thereby forming the step 30.
The non-display area BB includes a first non-display area BB1, the first non-display area BB1 is adjacent to the step 30, as shown in fig. 3 and 4, the first non-display area BB1 corresponds to and is adjacent to the step 30 along the column direction Y, the first non-display area BB1 includes an electrostatic protection area 40, the electrostatic protection area 40 includes an electrostatic protection circuit 400, and the electrostatic protection circuit 400 is configured to conduct static electricity in the display panel 100 out to prevent the static electricity from entering the display panel 100 to generate electrostatic breakdown, which affects the performance of the display panel 100. In order to reduce the number of pads of the driver IC, the multiplexer 60 is included between the electrostatic discharge protection circuits 400 of the electrostatic discharge protection region 40, and the multiplexer 60 is typically used to provide signals to a plurality of data lines via a signal line, which is connected to the plurality of data lines via switches, and the switches are used to control the reception of data signals on the corresponding data lines.
In fig. 4, the lengths of the multiplexer 60 and the electrostatic protection circuit 400 in the first non-display area BB1 in the column direction Y are not the same, and it is needless to say that the length of the electrostatic protection circuit 400 in the column direction Y is greater than the length of the multiplexer 60 in the column direction Y, but the length of the electrostatic protection circuit 400 in the column direction Y may be equal to the length of the multiplexer 60 in the column direction Y, and this is not particularly limited.
It can be understood that, in this embodiment, the electrostatic protection circuit 400 originally disposed in the step area 3 is disposed in the first non-display area BB1 corresponding to the step 30, the step 30 is formed by different numbers of pixels PX in the adjacent pixel rows 10 or the adjacent pixel columns 20, so that only the multiplexer 60 is disposed in the step area 3, and the space in the lower frame 801 corresponding to the step 30 is fully utilized, and of course, the multiplexers 60 can correspond to the pixel columns 20 one by one as much as possible, so as to reduce the number of winding lines, thereby reducing the width of the fanout wiring area 4 in the longitudinal direction, and thus, the lower frame 801 can be further compressed, and a narrow frame is realized; on the other hand, partially transferring the multiplexers 60 originally all disposed in the stepped region 3 into the first non-display region BB1 can further increase the pitch of the multiplexers 60 in the stepped region 3 to correspond one-to-one to the pixel columns 20. Furthermore, since the width of the first non-display area BB1 in the column direction Y is greater than the width of the step area 3 in the column direction Y corresponding to the position of the step 30, the width in the column direction Y is sufficient for arranging the esd protection circuit 400, and the length of the esd protection circuit 400 in the column direction Y can be set to be larger, thereby maximizing the use of space.
In some alternative embodiments, with continued reference to fig. 4, the electrostatic protection circuits 400 are arranged along the row direction X extending along the column direction Y.
As can be seen from fig. 4, the first non-display area BB1 is only adjacent to the step area 3 in the row direction X, so that the area is parallel to the step area 3, and the direction of the esd protection circuit 400 in the area may be the same as the arrangement direction of the multiplexers 60 in the step area 3, and the esd protection circuit 400 in the area does not need to be rotated or tilted, which is more beneficial for manufacturing.
In some alternative embodiments, with continued reference to FIG. 4, the multiplexers 60 are arranged along the row direction X to extend along the column direction Y.
As can be seen from fig. 4, the first non-display area BB1 is adjacent to the step area 3 only in the row direction X, so the first non-display area BB1 is parallel to the step area 3, the direction of arrangement of the multiplexers 601 in the first non-display area BB1 may be the same as the direction of arrangement of the multiplexers 602 in the step area 3, or the length of the multiplexers 601 in the first non-display area BB1 in the column direction Y may be the same as the length of the multiplexers 602 in the step area 3 in the column direction Y, or the width of the multiplexers 601 in the first non-display area BB1 in the row direction X may be the same as the width of the multiplexers 602 in the step area 3 in the row direction X, so that the multiplexers 60 in both areas can be simultaneously manufactured, thereby reducing the difficulty of manufacturing.
In some alternative embodiments, referring to fig. 5, 6 and 7, fig. 5 is a further partial enlarged view of the region N in fig. 3, fig. 6 is a further partial enlarged view of the region N in fig. 3, and fig. 7 is a further partial enlarged view of the region N in fig. 3, and the electrostatic protection circuits 400 alternate with the multiplexers 60 along the row direction X.
Referring to fig. 5 to 7, the esd protection circuits 400 and the multiplexers 60 in the first non-display area BB1 in fig. 5 are alternately arranged one by one, the esd protection circuits 400 and the multiplexers 60 in the first non-display area BB1 in fig. 6 are alternately arranged two by two, and the esd protection circuits 400 and the multiplexers 60 in the first non-display area BB1 in fig. 7 are alternately arranged two by three, i.e., two esd protection circuits 400, three multiplexers 60, three esd protection circuits 400, and one multiplexer 60 are arranged along the direction of the first non-display area BB1 pointing to the step area 3, of course, the number of the alternate arrangements of the esd protection circuits 400 and the multiplexers 60 is not specifically limited, and of course, the arrangements of the esd protection circuits 400 and the multiplexers 60 are not specifically limited, as long as the esd protection circuits 400 and the multiplexers 60 are disposed in the esd protection area 40, since the electrostatic protection circuit 400 and the multiplexer 60, which are originally all disposed in the step area 3, are partially disposed in the first non-display area BB1 corresponding to the step 30, only the multiplexer 60 is disposed in the step area 3, and the space at the position corresponding to the step 30 in the lower frame 801 is fully utilized, so that the multiplexers 60 can be in one-to-one correspondence with the pixel columns 20 as much as possible, the number of winding lines is reduced, the width of the fan-out routing area 4 in the longitudinal direction is reduced, and the lower frame 801 can be further compressed, thereby realizing a narrow frame.
In some alternative embodiments, referring to fig. 8, fig. 8 is a partial enlarged view of the region N in fig. 3, the step 30 of the present embodiment includes a first step 301 and a second step 302 which are adjacent to each other, the number of pixels PX in the pixel row 10 of the first step 301 is m, the number of pixels PX in the pixel row 10 of the second step 302 is N, m and N are positive integers, and m is greater than N;
the first non-display region BB1 includes a first sub non-display region BB11 and a second sub non-display region BB12, the first sub non-display region BB11 is adjacent to the first ladder 301, and the second sub non-display region BB12 is adjacent to the second ladder 302;
the electrostatic protection region 40 of the first sub non-display region BB11 includes a first electrostatic protection circuit 401; the electrostatic protection region 40 of the second sub non-display region BB12 includes the second electrostatic protection circuit 402;
in the row direction X, the width of the first electrostatic protection circuit 401 is smaller than the width of the second electrostatic protection circuit 402;
in the column direction Y, the length of the first electrostatic protection circuit 401 is greater than the length of the second electrostatic protection circuit 402.
Referring to fig. 8, the ladder 30 includes adjacent first and second ladders 301 and 302, the number of pixels PX in the pixel row 10 of the first ladder 301 is different from the number of pixels PX in the pixel row 10 of the second ladder 302, the number of pixels PX in the pixel row 10 of the first ladder 301 is m, the number of pixels PX in the pixel row 10 of the second ladder 302 is n, and m is greater than n, that is, the first ladder 301 is farther from the bonded region 1 than the bonded region 1 of the second ladder 302, the space of the corresponding first sub non-display region BB11 in the column direction Y is greater than the distance of the second sub-non-display region BB12 in the column direction Y, the electrostatic protection region 40 of the first sub-non-display region BB11 includes a first electrostatic protection circuit 401, the electrostatic protection region 40 of the second sub-non-display region BB12 includes a second electrostatic protection circuit 402, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 are arranged to extend in the column direction X, namely, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 are not rotatably arranged, so that the manufacture is convenient.
The optional first sub non-display region BB11 is located on the side of the second sub non-display region BB12 away from the step region 3, i.e. the second sub non-display region BB12 is adjacent to the step region 3. It is only schematically shown in the present embodiment that the width in the row direction X of the first multiplexer 60a located in the first sub non-display area BB11 and the width in the row direction X of the second multiplexer 60b located in the second sub non-display area BB12 are not equal, while the length in the column direction Y of the first multiplexer 60a located in the first sub non-display area BB11 and the length in the column direction Y of the second multiplexer 60b located in the second sub non-display area BB12 are not equal, it is of course also possible that the width in the row direction X of the first multiplexer 60a located in the first sub non-display area BB11 and the width in the row direction X of the second multiplexer 60b in the second sub non-display area BB12 are equal, while the length in the column direction Y of the first multiplexer 60a located in the first sub non-display area BB11 and the length in the column direction Y of the second multiplexer 60b in the second sub non-display area BB12 are equal, and is not particularly limited herein.
In fig. 8, the second step 302 is located at the pixel row 1001 and the pixel row 1002, and the first step 301 is located at the pixel row 1002 and the pixel row 1003, so the length of the first electrostatic protection circuit 401 in the column direction Y can be set to be larger, that is, the length of the first electrostatic protection circuit 401 in the column direction Y is larger than the length of the second electrostatic protection circuit 402 in the column direction Y, but in order to ensure the integrity of electronic components in the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402, the width of the first electrostatic protection circuit 401 in the row direction X is smaller than the width of the second electrostatic protection circuit 402 in the row direction X, and it is ensured that the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 can both perform electrostatic protection.
Of course, this embodiment also has the technical effects of any of the above embodiments, and details are not repeated here, and in this embodiment, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 with different widths and lengths are respectively set by making full use of the spatial difference between the first sub non-display area BB11 and the second sub non-display area BB12 in the column direction Y.
In some alternative embodiments, referring to fig. 9, fig. 9 is a further partial enlarged view of the region N in fig. 3, the electrostatic protection region 40 of the first sub non-display region BB11 further includes a first multiplexer 60a, and the electrostatic protection region 40 of the second sub non-display region BB12 further includes a second multiplexer 60 b;
in the row direction X, the width of the first multiplexer 60a is equal to the width of the second multiplexer 60 b; in the column direction Y, the length of the first multiplexer 60a is equal to the length of the second multiplexer 60 b.
Referring to fig. 9, the electrostatic protection region 40 of the first sub non-display region BB11 further includes a first multiplexer 60a, the first multiplexer 60a is between the first electrostatic protection circuits 401, the electrostatic protection region 40 of the second sub non-display region BB12 further includes a second multiplexer 60b, the second multiplexer 60b is between the second electrostatic protection circuits 402, a width of the first multiplexer 60a in the row direction X is equal to a width of the second multiplexer 60b in the row direction X, and a length of the first multiplexer 60a in the column direction Y is equal to a length of the second multiplexer 60b in the column direction Y, so that the first multiplexer 60a and the second multiplexer 60b can be simultaneously manufactured, and the manufacturing process is simplified.
Alternatively, the first multiplexer 60a and the second multiplexer 60b can be fabricated simultaneously with the multiplexers 60 in the step area 3, and the widths in the row direction X and the lengths in the column direction Y are equal, which is more advantageous for fabrication and further simplifies the fabrication process.
In some alternative embodiments, with continued reference to fig. 3 and 8, the non-display area BB includes an upper frame 802 and a lower frame 801 disposed oppositely along the column direction Y;
the display panel 100 includes K pixel rows 10, the lower frame 801 includes a step area 3, a fan-out routing area 4, and a first non-display area BB1, the fan-out routing area 4 is located between the step area 3 and the K pixel row 10 along the column direction Y, and the second step 302 is located on one side of the first step 301 close to the fan-out routing area 4 along the row direction X;
the step area 3 includes a third multiplexer 60c, and the width of the third multiplexer 60c is greater than the width of the second multiplexer 60b in the row direction X; in the column direction Y, the length of the third multiplexer 60c is smaller than the length of the second multiplexer 60 b.
Referring to fig. 3, the display panel 100 includes K pixel rows 10, the lower bezel 801 includes a step area 3 and a fan-out routing area 4, and a first non-display area BB1, the fan-out routing area 4 is located between the step area 3 and the K-th pixel row 10 in the column direction Y, that is, the fan-out routing area 4 is adjacent to the last pixel row 10, the second step 302 is located on a side of the first step 301 close to the fan-out routing area 4 in the row direction X, the second sub-non-display area BB12 of the first non-display area BB1 is located on a side of the first sub-non-display area BB11 of the first non-display area BB1 close to the step area 3, a third multiplexer 60c is disposed in the step area 3, and a width of the third multiplexer 60c is greater than a width of the second multiplexer 60b in the row direction X; in the column direction Y, the length of the third multiplexer 60c is smaller than the length of the second multiplexer 60b, and as described in fig. 8, in the row direction X, since part of the multiplexer 60 in the stepped region 3 is disposed in the first non-display region BB1, the space in the stepped region 3 in the row direction X is sufficient, and at this time, in the row direction X, the width of the third multiplexer 60c is larger than the width of the second multiplexer 60b, and the length in the column direction Y in the second sub non-display region BB12 is larger than the length of the stepped region 3 in the column direction Y, so the length of the second multiplexer 60b in the column direction Y may be larger than the length of the third multiplexer 60c in the column direction Y. Thereby making full use of the space of the second sub non-display area BB12 adjacent to the plateau region 3.
In some alternative embodiments, referring to fig. 10 and 11, fig. 10 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention; fig. 11 is a partial enlarged view of a region Q in fig. 10, and a non-display area BB further includes a gate driving circuit 90;
the non-display area BB further includes a gate driving signal line X11 surrounding the display area AA, and the gate driving signal line X11 is electrically connected to the gate driving circuit 90 and the electrostatic protection circuit 400, respectively.
The gate driving signal lines X11 are not shown in fig. 10, the gate driving circuit 90 is used to realize progressive scanning of the scanning lines in the pixels PX, and for the circular display panel 100, the axes of the gate driving circuits 90 in the left frame 803 and the right frame 804 need to match the diameter of the circular display panel 100, that is, the gate driving circuit 90 is rotated to some extent. Static electricity is generated in the process of manufacturing the display panel 100, so the gate driving signal lines X11 are connected by arranging the electrostatic protection circuits 400, in an embodiment, each electrostatic protection circuit 400 is connected to different gate driving signal lines X11, that is, the number of the electrostatic protection circuits 400 corresponds to the number of the gate driving signal lines X11 one by one, so that each gate driving signal line X11 can realize electrostatic protection, and certainly, the electrostatic protection circuits can be arranged according to the requirement of electrostatic protection, which is not further limited in the present application.
In some alternative embodiments, referring to FIG. 12, FIG. 12 is a plan view of the ESD protection circuit of FIG. 11, FIG. 13 is a cross-sectional view taken along line K-K ' of FIG. 11, FIG. 14 is a further cross-sectional view taken along line K-K ' of FIG. 11, and FIG. 15 is a further cross-sectional view taken along line K-K ' of FIG. 11.
The display panel 100 includes a substrate C01, a first metal layer C03 on a side of the substrate C01, a capacitor metal layer C04 on a side of the first metal layer C03 away from the substrate C01, a second metal layer C05 on a side of the capacitor metal layer C04 away from the substrate C01, and a third metal layer C06 on a side of the second metal layer C05 away from the substrate C01, the gate driving signal line X11 and the second metal layer C05 are in the same layer, the esd protection circuit 400 includes a first transistor T1 and a second transistor T2 connected in parallel, a drain of the first transistor T1 and a drain of the second transistor T2 are electrically connected to the gate driving signal line X11 through a first conductive portion DD, the first conductive portion and the first metal layer C03, the first DD conductive portion and the capacitor metal layer C04 are in the same layer, or the first conductive portion and the third metal layer C06.
It is understood that, in general, the gate driving signal line X11 is located on the second metal layer C05, so the first conductive part DD needs to be disposed on the same layer as the first metal layer C03, the same layer as the capacitor metal layer C04, or the same layer as the third metal layer C06, i.e., the first conductive part DD cannot be disposed on the second metal layer C05. Fig. 13 to 15 schematically show the structure of each film layer in the display panel 100, which includes a substrate C01, a first metal layer C03 located on the substrate C01 side, a capacitor metal layer C04 located on the first metal layer C03 side away from the substrate C01, a second metal layer C05 located on the capacitor metal layer C04 side away from the substrate C01 side, and a third metal layer C06 located on the second metal layer C05 side away from the substrate C01 side, where of course, an insulating layer is further included between the first metal layer C03, the capacitor metal layer C04, the second metal layer C05, and the third metal layer C06, and an active layer C02, that is, an active layer C02 of the first transistor T1 and the second transistor T2, is further included in the display panel. The display panel further includes a driving transistor T for driving the light emitting element EM to emit light, and the light emitting element EM includes an anode C07, a light emitting layer C08, and a cathode C09, an encapsulation layer C10 in fig. 13-15 is used for encapsulation to prevent water and oxygen from entering into the panel, optionally, a touch layer (not shown in the figure) may be further disposed on a side of the encapsulation layer C01 away from a side C01 of the substrate, a first conductive portion DD in fig. 13 is disposed on the first metal layer C03, and the first conductive portion DD is electrically connected to the gate driving signal line X11 through a via hole, the first conductive portion DD in fig. 14 is disposed on the capacitor metal layer C04, and the first conductive portion DD in fig. 15 is disposed on the third metal layer C06.
The esd protection circuit 400 includes a first transistor T1 and a second transistor T2, a gate of the first transistor T1 and a source of the first transistor T1 are both electrically connected to a high potential signal line VGH, a drain of the first transistor T1 is both electrically connected to a gate driving signal line X11, a gate of the second transistor T2 and a drain of the second transistor T2 are both electrically connected to a gate driving signal line X11, a source of the second transistor T2 is electrically connected to a low potential signal line VGL, the optional first transistor T1 and the second transistor T2 are P-type transistors, a drain of the first transistor T1 and a drain of the second transistor T2 are electrically connected to the gate driving signal line X11 through a first conductive portion DD, when static electricity accumulated in the gate driving signal line X11 is a low potential, a gate of the second transistor T2 is turned on, for example, a potential on the gate driving signal line X11 is a negative potential and is lower than the low potential signal line VGL, a current flows from the gate driving signal line X11 to the low potential signal line VGL, so that the potential of the gate driving signal line X11 is raised to a potential equal to the low potential signal line VGLVGL, and static charges are removed. When the gate driving signal line X11 is at a high potential and the potential is higher than the potential of the high potential signal line VGH, and the gate-source voltage difference of the first transistor T1 is positive, the first transistor T1 is turned on, and a current flows from the gate driving signal line X11 to the high potential signal line VGH, so that the potential of the gate driving signal line X11 is pulled down to a potential equal to the high potential signal line VGH, thereby eliminating static charges.
In some alternative embodiments, with continuing reference to fig. 11 to 15 and with further reference to fig. 16, fig. 16 is a partially enlarged view of the first and second sub non-display regions in fig. 9, and the gate driving signal line X11 includes a trigger signal line, a clock signal line, and a test signal line for testing an output signal of the gate driving circuit 90.
It is understood that the gate driving signal lines X11 include two triggering signal lines (STV1 and STV2) of the gate driving circuit, four clock signal lines (CK1, CK2, XCK1, XCK2), and two testing signal lines (SOUT1, SOUT2) for testing the output signals of the gate driving circuit, and then 8 esd protection circuits are required to be disposed in one-to-one correspondence with the gate driving signal lines X11 to implement esd protection on the gate driving signal lines X11.
In some alternative embodiments, with continued reference to FIG. 8, along the column direction Y, the first electrostatic protection circuit 401 has a length L1, 200 μm L1 μm 250 μm, and the second electrostatic protection circuit 402 has a length L2, 100L 2 < 200 μm.
As described above, the space of the first sub non-display area BB11 in the column direction Y is greater than the distance of the second sub non-display area BB12 in the column direction Y, the length of the optional first electrostatic protection circuit 401 in the first sub non-display area BB11 in the column direction Y is greater than the length of the second electrostatic protection circuit 402 in the second sub non-display area BB12 in the column direction Y, the length of the first electrostatic protection circuit 401 is L1, 200 μm ≦ L1 ≦ 250 μm, the length of the second electrostatic protection circuit 402 is L2, 100 ≦ L2 ≦ 200 μm, and the space requirements of the first sub non-display area BB11 and the second sub non-display area BB12 in the column direction Y can be satisfied.
In some alternative embodiments, with continuing reference to fig. 3 and with reference to fig. 17, fig. 17 is a schematic plan view of another display panel provided by the present invention, and the shape of the display area AA includes a circle or a rectangle with rounded corners.
The display area of the display panel in fig. 3 is circular, the display area of the display panel in fig. 17 is a rounded rectangle, a step is formed at the position of the rounded corner R, and for the arrangement manner of the electrostatic protection circuit, reference may be made to the embodiment in fig. 3, which is not repeated here. The electrostatic protection region may be disposed in the first non-display region adjacent to the step, as long as the step is formed when the number of pixels in adjacent two pixel rows is not equal or the number of pixels in adjacent two pixel columns is not equal.
The embodiment also provides a display device comprising the display panel. Referring to fig. 18, fig. 18 is a schematic plan view of a display device according to the present invention. Fig. 18 provides a display device 1000 including a display panel 100, wherein the display panel 100 is the display panel 100 according to any of the above embodiments of the present invention. The embodiment in fig. 18 only illustrates the display device 1000 by taking an intelligent wearable device as an example, and it should be understood that the display device 1000 provided in the embodiment of the present invention may be other display devices 1000 having a display function, such as a computer, a television, a vehicle-mounted display panel, and the present invention is not limited in this respect. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel in the foregoing embodiments, which is not repeated herein.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
a display panel of the present invention includes: comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the steps are formed by unequal numbers of pixels in two adjacent pixel rows or unequal numbers of pixels in two adjacent pixel columns, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. The lower frame area of the display panel is provided with a step area and a fan-out wiring area, the fan-out wiring area is located between the step area and the display area, a multiplexer and an electrostatic protection circuit are required to be arranged in the step area, the electrostatic protection circuit occupies the space in the transverse direction, the multiplexer cannot correspond to pixel columns in the display area one by one, the data line or the touch control line in the display area is electrically connected in a necessary mode of winding, the winding can occupy the longitudinal space, namely, the lower frame cannot be compressed in the longitudinal direction, and the lower frame is prevented from realizing a narrow frame. According to the invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the steps, the steps are formed due to the fact that the number of pixels in adjacent pixel rows or adjacent pixel columns is different, only the multiplexer is arranged in the step area, the space of the lower frame corresponding to the step position is fully utilized, the multiplexer can be in one-to-one correspondence with the pixel columns as much as possible, the number of winding wires is reduced, the width of the fan-out wiring area in the longitudinal direction is reduced, and therefore the lower frame can be further compressed, and the narrow frame is realized.
Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (13)
1. A display panel, comprising: comprising a display area and a non-display area at least partially surrounding the display area;
the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the steps are formed by unequal numbers of pixels in two adjacent pixel rows or unequal numbers of pixels in two adjacent pixel columns, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps;
the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits.
2. The display panel according to claim 1, wherein the electrostatic protection circuits are arranged in a row direction and extend in a column direction.
3. The display panel according to claim 2, wherein the multiplexers are arranged in a row direction extending in a column direction.
4. The display panel according to claim 1, wherein the electrostatic protection circuits are alternately arranged with the multiplexers in the row direction.
5. The display panel according to claim 3, wherein the stairs comprise a first stair and a second stair which are adjacent, the number of pixels in the pixel rows of the first stair is m, the number of pixels in the pixel rows of the second stair is n, m and n are positive integers, and m is greater than n;
the first non-display area comprises a first sub non-display area and a second sub non-display area, the first sub non-display area is adjacent to the first ladder, and the second sub non-display area is adjacent to the second ladder;
the electrostatic protection region of the first sub non-display region includes a first electrostatic protection circuit; the electrostatic protection region of the second sub non-display region includes a second electrostatic protection circuit;
in the row direction, the width of the first electrostatic protection circuit is smaller than that of the second electrostatic protection circuit;
the length of the first electrostatic protection circuit is greater than that of the second electrostatic protection circuit along the column direction.
6. The display panel according to claim 5, wherein the electrostatic protection region of the first sub non-display region further comprises a first multiplexer, and the electrostatic protection region of the second sub non-display region further comprises a second multiplexer;
a width of the first multiplexer is equal to a width of the second multiplexer along the row direction; the length of the first multiplexer is equal to the length of the second multiplexer along the column direction.
7. The display panel according to claim 6, wherein the non-display region includes an upper bezel and a lower bezel which are disposed opposite to each other in the column direction;
the display panel comprises K pixel rows, the lower frame comprises a step area, a fan-out wiring area and the first non-display area, the fan-out wiring area is located between the step area and the Kth pixel row along the column direction, and the second step is located on one side, close to the fan-out wiring area, of the first step along the row direction;
the step region includes a third multiplexer having a width greater than a width of the second multiplexer along the row direction; a length of the third multiplexer is less than a length of the second multiplexer along the column direction.
8. The display panel according to claim 1, wherein the non-display region further comprises a gate driving circuit;
the non-display area further comprises a grid driving signal line surrounding the display area, and the grid driving signal line is electrically connected with the grid driving circuit and the electrostatic protection circuit respectively.
9. The display panel according to claim 8, further comprising a substrate base, a first metal layer on a side of the substrate base, a capacitor metal layer on a side of the first metal layer away from the substrate base, a second metal layer on a side of the capacitor metal layer away from the substrate base, a third metal layer on a side of the second metal layer away from the substrate base, the gate driving signal line and the second metal layer are on the same layer, the electrostatic protection circuit comprises a first transistor and a second transistor which are connected in parallel, a drain of the first transistor and a drain of the second transistor are electrically connected to the gate driving signal line through a first conductive portion, the first conductive part and the first metal layer are on the same layer, or the first conductive part and the capacitor metal layer are on the same layer, or the first conductive part and the third metal layer are on the same layer.
10. The display panel according to claim 8, wherein the gate drive signal line comprises a trigger signal line, a clock signal line, and a test signal line for testing an output signal of the gate drive circuit.
11. The display panel according to claim 5, wherein the first electrostatic discharge protection circuit has a length L1, 200 μm L1 μm 250 μm, and the second electrostatic discharge protection circuit has a length L2, 100L 2 < 200 μm in the column direction.
12. The display panel of claim 1, wherein the shape of the display area comprises a circle or a rounded rectangle.
13. A display device comprising the display panel according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210594426.9A CN114937420B (en) | 2022-05-27 | 2022-05-27 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210594426.9A CN114937420B (en) | 2022-05-27 | 2022-05-27 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114937420A true CN114937420A (en) | 2022-08-23 |
| CN114937420B CN114937420B (en) | 2024-02-09 |
Family
ID=82866194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210594426.9A Active CN114937420B (en) | 2022-05-27 | 2022-05-27 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114937420B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024046054A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display apparatus |
Citations (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003121875A (en) * | 2001-10-09 | 2003-04-23 | Seiko Epson Corp | Method for manufacturing element substrate device, method for manufacturing electrooptical device, and reticle |
| KR20070113120A (en) * | 2006-05-23 | 2007-11-28 | 가시오게산키 가부시키가이샤 | Display device |
| US20150379927A1 (en) * | 2014-06-30 | 2015-12-31 | Shanghai Tianma Am-Oled Co.,Ltd. | Oled pixel driving circuit, electrostatic discharge protection circuit and detection method |
| CN107180593A (en) * | 2017-06-30 | 2017-09-19 | 厦门天马微电子有限公司 | A kind of special-shaped display panel and display device |
| CN107219660A (en) * | 2017-07-12 | 2017-09-29 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107331297A (en) * | 2017-06-28 | 2017-11-07 | 厦门天马微电子有限公司 | A kind of special-shaped display panel and display device |
| CN107561799A (en) * | 2017-08-25 | 2018-01-09 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107819020A (en) * | 2017-11-03 | 2018-03-20 | 武汉天马微电子有限公司 | A kind of organic electroluminescence display panel and display device |
| CN107993579A (en) * | 2017-11-29 | 2018-05-04 | 武汉天马微电子有限公司 | A kind of display panel and its driving method, display device |
| US20180129106A1 (en) * | 2017-09-11 | 2018-05-10 | Shanghai Tianma AM-OLED Co., Ltd. | Display panel and display device |
| CN108470522A (en) * | 2018-05-14 | 2018-08-31 | 昆山国显光电有限公司 | Display panel and its display device |
| CN108492761A (en) * | 2018-03-29 | 2018-09-04 | 上海中航光电子有限公司 | A kind of display panel and electronic equipment |
| CN109375443A (en) * | 2018-12-25 | 2019-02-22 | 厦门天马微电子有限公司 | Display panel and display device |
| CN109524445A (en) * | 2018-12-20 | 2019-03-26 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| US20190164515A1 (en) * | 2017-11-29 | 2019-05-30 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Goa circuit and embedded touch display panel |
| CN110299075A (en) * | 2019-04-30 | 2019-10-01 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111427469A (en) * | 2020-02-21 | 2020-07-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111681554A (en) * | 2020-06-30 | 2020-09-18 | 上海中航光电子有限公司 | Display panel and display device |
| WO2021102971A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113554969A (en) * | 2021-07-16 | 2021-10-26 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113611240A (en) * | 2021-09-15 | 2021-11-05 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2021238801A1 (en) * | 2020-05-29 | 2021-12-02 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| WO2022068383A1 (en) * | 2020-09-30 | 2022-04-07 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
-
2022
- 2022-05-27 CN CN202210594426.9A patent/CN114937420B/en active Active
Patent Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003121875A (en) * | 2001-10-09 | 2003-04-23 | Seiko Epson Corp | Method for manufacturing element substrate device, method for manufacturing electrooptical device, and reticle |
| KR20070113120A (en) * | 2006-05-23 | 2007-11-28 | 가시오게산키 가부시키가이샤 | Display device |
| US20150379927A1 (en) * | 2014-06-30 | 2015-12-31 | Shanghai Tianma Am-Oled Co.,Ltd. | Oled pixel driving circuit, electrostatic discharge protection circuit and detection method |
| CN107331297A (en) * | 2017-06-28 | 2017-11-07 | 厦门天马微电子有限公司 | A kind of special-shaped display panel and display device |
| CN107180593A (en) * | 2017-06-30 | 2017-09-19 | 厦门天马微电子有限公司 | A kind of special-shaped display panel and display device |
| CN107219660A (en) * | 2017-07-12 | 2017-09-29 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107561799A (en) * | 2017-08-25 | 2018-01-09 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| US20180166467A1 (en) * | 2017-08-25 | 2018-06-14 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel and display device |
| US20180129106A1 (en) * | 2017-09-11 | 2018-05-10 | Shanghai Tianma AM-OLED Co., Ltd. | Display panel and display device |
| CN107819020A (en) * | 2017-11-03 | 2018-03-20 | 武汉天马微电子有限公司 | A kind of organic electroluminescence display panel and display device |
| CN107993579A (en) * | 2017-11-29 | 2018-05-04 | 武汉天马微电子有限公司 | A kind of display panel and its driving method, display device |
| US20190164515A1 (en) * | 2017-11-29 | 2019-05-30 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Goa circuit and embedded touch display panel |
| CN108492761A (en) * | 2018-03-29 | 2018-09-04 | 上海中航光电子有限公司 | A kind of display panel and electronic equipment |
| CN108470522A (en) * | 2018-05-14 | 2018-08-31 | 昆山国显光电有限公司 | Display panel and its display device |
| CN109524445A (en) * | 2018-12-20 | 2019-03-26 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| CN109375443A (en) * | 2018-12-25 | 2019-02-22 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110299075A (en) * | 2019-04-30 | 2019-10-01 | 厦门天马微电子有限公司 | Display panel and display device |
| WO2021102971A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111427469A (en) * | 2020-02-21 | 2020-07-17 | 厦门天马微电子有限公司 | Display panel and display device |
| WO2021238801A1 (en) * | 2020-05-29 | 2021-12-02 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN111681554A (en) * | 2020-06-30 | 2020-09-18 | 上海中航光电子有限公司 | Display panel and display device |
| WO2022068383A1 (en) * | 2020-09-30 | 2022-04-07 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN113554969A (en) * | 2021-07-16 | 2021-10-26 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN113611240A (en) * | 2021-09-15 | 2021-11-05 | 京东方科技集团股份有限公司 | Display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024046054A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114937420B (en) | 2024-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107863374B (en) | OLED display panel and display device | |
| CN113744649A (en) | Display panel and display device | |
| KR102443121B1 (en) | Display panel, manufacturing method thereof, and display device | |
| CN109494243B (en) | Display panel and display device | |
| US20230413607A1 (en) | Display panel and display device including the same that includes display area facing front of window, where emission areas of corner display area are places, and display device oncluding the same | |
| US20230030745A1 (en) | Display substrate and display apparatus | |
| CN113345933A (en) | Display device | |
| CN115346486A (en) | Display panel and display device | |
| US11687191B2 (en) | Display device | |
| CN114937420B (en) | Display panel and display device | |
| US20230086927A1 (en) | Display panel and display apparatus | |
| US11967274B2 (en) | Display substrate, display panel, and display device | |
| CN113534992A (en) | Display device | |
| CN117500314A (en) | Display device | |
| CN113517327B (en) | Display panel, display device and display method | |
| CN114613822A (en) | Display panel and display device | |
| US11257879B2 (en) | Display panels and display devices thereof | |
| CN113672114A (en) | Display device | |
| CN112786658A (en) | Display device | |
| US20230320148A1 (en) | Display device | |
| US11450836B2 (en) | Display device | |
| US20240147785A1 (en) | Display Substrate and Preparation Method Therefor, and Display Apparatus | |
| US11937473B2 (en) | Display panel and display apparatus | |
| US11330700B2 (en) | Display device | |
| US20240118760A1 (en) | Input sensor and electronic device including the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |