CN210514885U - Array substrate, light control panel and display device - Google Patents
Array substrate, light control panel and display device Download PDFInfo
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- CN210514885U CN210514885U CN201921976113.XU CN201921976113U CN210514885U CN 210514885 U CN210514885 U CN 210514885U CN 201921976113 U CN201921976113 U CN 201921976113U CN 210514885 U CN210514885 U CN 210514885U
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Abstract
An array substrate, a light control panel and a display device are provided. The array substrate comprises a data line layer, and a substrate, a first electrode layer, an insulating layer and a second electrode layer which are sequentially arranged. The first electrode layer comprises a plurality of grid lines, each whole of the grid lines extends along the first direction and comprises a plurality of first folding line structures which are sequentially and directly connected with each other in the first direction; the data line layer includes a plurality of data lines, each of the plurality of data lines extending entirely in a second direction crossing the first direction; the plurality of gate lines and the plurality of data lines cross each other to define a plurality of light-controlling pixel units; the second electrode layer comprises a plurality of common electrodes arranged in an array, and each common electrode is arranged in at least one of the light control pixel units; at least one of the plurality of gate lines at least partially overlaps with an orthographic projection of at least one of the common electrodes on the first electrode layer.
Description
Technical Field
Embodiments of the present disclosure relate to an array substrate, a light control panel and a display device.
Background
The liquid crystal display device includes a backlight module (backlight unit) and a liquid crystal panel, the backlight module being disposed on a non-display side of the liquid crystal panel to provide a light source for a display operation of the display panel. The liquid crystal panel includes a polarizer, an array substrate, a counter substrate, and a liquid crystal molecular layer filled between the two substrates. The liquid crystal display device enables liquid crystal molecules in a liquid crystal molecule layer to deflect by forming an electric field between the array substrate and the opposite substrate, and the deflected liquid crystal molecules can form a liquid crystal light valve by matching with the polarizer. Since the liquid crystal molecule layer does not emit light, the display function needs to be realized by the backlight module. With the continuous development of display technologies, users have made higher and higher requirements on contrast, brightness uniformity, and the like of display devices.
SUMMERY OF THE UTILITY MODEL
At least one embodiment of the present disclosure provides an array substrate including a data line layer, and a substrate, a first electrode layer, an insulating layer, and a second electrode layer, which are sequentially disposed. The first electrode layer comprises a plurality of grid lines, each whole of the grid lines extends along the first direction and comprises a plurality of first folding line structures which are sequentially and directly connected with each other in the first direction; the data line layer includes a plurality of data lines, each of the plurality of data lines extending entirely in a second direction crossing the first direction; the plurality of gate lines and the plurality of data lines cross each other to define a plurality of light-controlling pixel units; the second electrode layer comprises a plurality of common electrodes arranged in an array, and each common electrode is arranged in at least one of the light control pixel units; and at least one of the plurality of gate lines at least partially overlaps with an orthographic projection of at least one of the common electrodes on the first electrode layer.
For example, in at least one example of the array substrate, orthographic projections of two opposite sides of each of the plurality of common electrodes in the second direction on the first electrode layer are respectively overlapped with one sides of two corresponding gate lines close to each of the plurality of common electrodes.
For example, in at least one example of the array substrate, a space is provided between two adjacent common electrodes in the second direction, and a gate line overlapping with orthogonal projections of the two adjacent common electrodes in the second direction on the first electrode layer overlaps with an orthogonal projection of the space on the first electrode layer.
For example, in at least one example of the array substrate, each of the plurality of common electrodes includes: a plurality of stripe-shaped electrodes arranged in parallel in the first direction and a first connection sub-electrode and a second connection sub-electrode as two opposite sides of each of the plurality of common electrodes in the second direction; the first connector electrode is connected with the first ends of the strip electrodes, and the second connector electrode is connected with the second ends of the strip electrodes; and orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer are respectively overlapped with one side parts, close to each of the plurality of common electrodes, of the two corresponding grid lines.
For example, in at least one example of the array substrate, each of the first and second connection sub-electrodes has the same extension tendency as a corresponding region of the plurality of gate lines, the corresponding region of the plurality of gate lines being a region of the plurality of gate lines overlapping with each of the first and second connection sub-electrodes in the second direction; and the plurality of strip-shaped electrodes and corresponding regions of the plurality of data lines have the same extension trend, and the corresponding regions of the plurality of data lines are regions of the plurality of data lines which are overlapped with the plurality of strip-shaped electrodes in the first direction.
For example, in at least one example of the array substrate, each of the plurality of data lines includes a plurality of second fold line structures directly connected in sequence in the second direction; the plurality of first fold line structures that many grid lines include with a plurality of accuse light pixel unit one-to-one, a plurality of second fold line structures that many data lines include with a plurality of accuse light pixel unit one-to-one.
For example, in at least one example of the array substrate, the first electrode layer further includes a plurality of pixel electrodes; each of the plurality of pixel electrodes is arranged in the corresponding light control pixel unit; and the plurality of pixel electrodes and the plurality of grid lines are arranged at intervals.
For example, in at least one example of the array substrate, the pixel electrode is a plate electrode, and an orthographic projection of the plate electrode on the second electrode layer is a continuous plane.
For example, in at least one example of the array substrate, each of the plurality of common electrodes includes: a plurality of stripe-shaped electrodes arranged in parallel in the first direction and a first connection sub-electrode and a second connection sub-electrode as two opposite sides of each of the plurality of common electrodes in the second direction; the first connector electrode is connected with the first ends of the strip electrodes, and the second connector electrode is connected with the second ends of the strip electrodes; orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer are respectively overlapped with one side of each of the two corresponding grid lines close to the plurality of common electrodes; and orthographic projections of the pixel electrodes on the second electrode layer are exposed from gaps between adjacent strip-shaped electrodes included in the corresponding common electrode.
For example, in at least one example of the array substrate, each of the plurality of common electrodes and the pixel electrode includes a transparent conductive oxide, and each of the plurality of gate lines includes a metal.
For example, in at least one example of the array substrate, a surface of each of the plurality of gate lines on a side close to the second electrode layer has a concave-convex structure.
At least one embodiment of the present disclosure also provides a light control panel, including: the liquid crystal display device comprises an opposite substrate, a liquid crystal layer and an array substrate provided by at least one embodiment of the disclosure. The array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.
For example, in at least one example of the light management panel, the opposite substrate includes a black matrix layer; the black matrix layer comprises a plurality of black matrix units, and each whole of the plurality of black matrix units extends along the first direction; and orthographic projections of the grid lines on the black matrix layer are respectively positioned in the corresponding black matrix units.
For example, in at least one example of the light control panel, each of the plurality of black matrix units includes a plurality of black matrix structures directly connected in sequence in the first direction, and orthogonal projections of a plurality of first fold line structures included in the plurality of gate lines on the black matrix layer are respectively located in the corresponding black matrix structures.
For example, in at least one example of the light management panel, a ratio of a width of each of the plurality of black matrix units to a width of the corresponding gate line is between 1 and 2.5.
At least one embodiment of the present disclosure also provides a display device including: display panel, backlight unit and the accuse light panel that at least one embodiment of this disclosure provided. The display panel, the light control panel and the backlight unit are arranged in a stacked mode, the display panel is located on the light emitting side of the light control panel, and the backlight unit is located on one side, far away from the display panel, of the light control panel.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1A shows a schematic cross-sectional view of a liquid crystal display device;
FIG. 1B shows a schematic plan view of a light management panel and a display panel of the liquid crystal display device shown in FIG. 1A;
FIG. 1C is a schematic plan view of a light management panel of the liquid crystal display device shown in FIG. 1A;
FIG. 1D illustrates a light-controlling pixel cell of the light-controlling panel shown in FIG. 1A;
FIG. 2A is a schematic diagram illustrating a gate line blocking condition of the LCD device shown in FIG. 1A at a first viewing angle;
FIG. 2B is a schematic diagram illustrating a shielding of the gate lines of the LCD device shown in FIG. 1A at a second viewing angle;
FIG. 3A is another schematic plan view of the light management panel shown in FIG. 1C;
FIG. 3B is a schematic cross-sectional view of the light management panel shown in FIGS. 1C and 3A;
FIG. 3C is another schematic cross-sectional view of the light management panel shown in FIG. 3B;
FIG. 4A is an enlarged schematic plan view of a first region of the light management panel shown in FIG. 3A;
FIG. 4B is a schematic cross-sectional view of a first region of the light management panel shown in FIG. 4A;
FIG. 4C is an enlarged schematic plan view of a second region of the light management panel shown in FIG. 3A;
FIG. 5 is a schematic cross-sectional view of a light management panel provided by at least one embodiment of the present disclosure;
FIG. 6A is a schematic plan view of an array substrate of the light control panel shown in FIG. 5;
FIG. 6B is another schematic plan view of the array substrate shown in FIG. 6A;
FIG. 7A is another schematic cross-sectional view of the light management panel shown in FIG. 5;
fig. 7B is a surface of a side of each of a plurality of gate lines of the array substrate, the side being close to the second electrode layer, according to at least one embodiment of the present disclosure;
fig. 8A is a schematic plan view of a common electrode provided by at least one embodiment of the present disclosure;
fig. 8B is an enlarged view of a first region of the array substrate shown in fig. 6B;
fig. 9A is an enlarged view of a second region of the array substrate shown in fig. 6B;
fig. 9B is a schematic cross-sectional view of a second region of the array substrate shown in fig. 9A;
FIG. 10A is another schematic view of the array substrate shown in FIG. 6B;
fig. 10B is a schematic plan view of another first fold structure and a first connector sub-electrode (or a second connector sub-electrode) provided in at least one embodiment of the present disclosure;
fig. 11 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure;
fig. 12A is a schematic plan view of a display panel of the display device shown in fig. 11; and
fig. 12B is a schematic plan view of the display device shown in fig. 11.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The present disclosure provides a liquid crystal display device, which has a low contrast ratio of a display screen, and a method for manufacturing the same, and a liquid crystal display device having the same. The utility model discloses a utility model designer notices in studying, can adopt the liquid crystal display device who has two liquid crystal cells to promote the contrast of display screen, and the following is exemplified in connection with fig. 1A.
Fig. 1A shows a schematic cross-sectional view of a liquid crystal display device 500. As shown in fig. 1A, the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502, and a display panel 501, which are sequentially disposed. Fig. 1B shows a schematic plan view of the light control panel 502 and the display panel 501 of the liquid crystal display device 500 shown in fig. 1A. Fig. 1C shows a schematic plan view of the light control panel 502 (the array substrate 551 of the light control panel 502) of the liquid crystal display device 500 shown in fig. 1A. For example, the light control panel 502 is configured to adjust the intensity of light emitted by the backlight unit 503 and incident on the display panel 501. For example, the light emitted from the light control panel 502 is white light, that is, the light control panel 502 does not have a color adjusting function.
As shown in fig. 1B, the display panel 501 includes a plurality of first signal lines 541 extending in a first direction D1 and a plurality of second signal lines 542 extending in a second direction D2; the plurality of first signal lines 541 and the plurality of second signal lines 542 intersect to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 530 arranged in an array; each display pixel unit 530 includes a first display sub-pixel unit 531, a second display sub-pixel unit 532, and a third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532 and the third display sub-pixel unit 533 are, for example, a red display sub-pixel unit, a green display sub-pixel unit and a blue display sub-pixel unit, respectively. For example, the first direction D1 is perpendicular to the second direction D2. For example, the first signal lines 541 are gate lines of the display panel 501, and the second signal lines 542 are data lines of the display panel 501.
As shown in fig. 1B and 1C, the light control panel 502 (the array substrate 551 of the light control panel 502) includes a plurality of gate lines 510 respectively extending in a first direction D1 and a plurality of data lines 521 respectively extending in a second direction D2 intersecting the first direction D1; the plurality of gate lines 510 and the plurality of data lines 521 intersect to define a plurality of light-controlling pixel cells 523. For example, the light control panel 502 further includes a plurality of common electrode lines 522 extending in the second direction D2, respectively. For example, the light control panel 502 includes a plurality of light control units arranged in an array, and the plurality of light control pixel units 523 of the array substrate 551 are respectively disposed in the corresponding light control units.
For example, the light control panel 502 can adjust the transmittance of each light control unit of the light control panel based on the data signal received by the data line 521, so that the light control unit of the light control panel 502 can be used to control the intensity of the light incident on the display sub-pixel unit of the display panel 501 corresponding to the light control unit, and thus the light control panel 502 can be used to provide the adjusted backlight to the display panel 501. For example, by providing the light control panel 502 in the display device 500, the transmittance of the light control unit corresponding to the region of the display screen of the liquid crystal display device with low luminance (e.g., luminance zero) can be made low (e.g., transmittance equal to or close to zero), in which case the possible dark state light leakage problem of the display panel 501 has less adverse effect on the contrast of the display screen, and thus the use of the liquid crystal display device with the dual liquid crystal cells (i.e., the display device with the light control panel) can improve the contrast of the display screen.
For example, the width of the first signal line 541 is greater than the width of the gate line 510. For example, the sizes of the first, second, and third display sub-pixel units 531, 532, and 533 in the first direction D1 are the same as each other, and for example, the sizes of the first, second, and third display sub-pixel units 531, 532, and 533 in the second direction D2 are the same as each other.
As shown in fig. 1B and 1C, each gate line 510 of the light-controlling panel 502 is implemented as a meander line, each gate line 510 includes a plurality of first routing portions 511 and a plurality of second routing portions 512, the plurality of first routing portions 511 and the plurality of second routing portions 512 are alternately arranged, and the adjacent first routing portions 511 and second routing portions 512 are connected to each other, as shown in fig. 1B, an included angle α (acute angle) between the first routing portions 511 (or/and the second routing portions 512) and the first direction D1 is about 50-70 degrees, so as to reduce the moire problem of the liquid crystal display device 500.
FIG. 1D shows light-controlling pixel cell 523 of light-controlling panel 502 shown in FIG. 1A. As shown in fig. 1D, the size of the light-controlling pixel unit 523 in the first direction D1 is S1, and the size of the light-controlling pixel unit 523 in the second direction D2 is S2. As shown in fig. 1B-1D, a size S1 of the light-controlling pixel unit 523 in the first direction D1 is equal to twice a size of the display pixel unit 530 in the first direction D1, and a size S2 of the light-controlling pixel unit 523 in the second direction D2 is equal to four times a size of the display pixel unit 530 in the second direction D2.
The utility model discloses a designer notices in studying, walks the line through making grid line 510 realize being the broken line, can restrain the inhomogeneous problem of luminance of liquid crystal display device 500, for example, this inhomogeneous problem of luminance is that black and white line is bad or horizontal line is bad (for example, black and white line is bad under the angle of looking aside) the problem. The specific analysis is as follows. In the case where the gate lines 510 (and the black matrix units shielding the gate lines) are implemented as straight lines, if an alignment error occurs when the light control panel 502 and the display panel 501 are attached, an orthographic projection of the gate lines 510 (straight lines) on the display panel 501 will overlap with one row of display pixels of the display panel 501, the gate lines 510 will shield light from the backlight unit 503, and make the brightness of the area of the liquid crystal display device 500 corresponding to the gate lines 510 close to zero (i.e., corresponding to black stripes), and the area of the liquid crystal display device 500 other than the area corresponding to the gate lines 510 corresponds to white stripes; in this case, the liquid crystal display device 500 has black stripes and white stripes alternately arranged in the second direction D2, that is, there may be a problem of poor black and white stripes in the liquid crystal display device 500. In the case where the gate lines 510 are implemented as a meander line, the black-and-white stripe defect or the horizontal stripe defect of the liquid crystal display device 500 can be suppressed.
The utility model designer of the present disclosure also notices in the research that the liquid crystal display device 500 shown in fig. 1A and 1B may have a problem of color unevenness (rainbow stripes). The rainbow texture problem is a problem of uneven color mixing in different areas of the display device. Specifically, when a predetermined display screen of the display device is a white screen, the user observes that the actual screen has color stripes. The rainbow texture problem is related to the difference in shading of light emitted from the backlight unit at different viewing angles in the regions of the gate lines 510 (and the black matrix units shading the gate lines) corresponding to the display sub-pixel units of different colors. The rainbow texture problem is exemplarily described below with reference to fig. 2A and 2B. Fig. 2A is a schematic diagram illustrating a case where the gate lines 510 of the liquid crystal display device 500 illustrated in fig. 1A are shielded at a first viewing angle (e.g., a front viewing angle), and fig. 2B is a schematic diagram illustrating a case where the gate lines 510 of the liquid crystal display device 500 illustrated in fig. 1A are shielded at a second viewing angle (e.g., a side viewing angle). For convenience of explanation, it is assumed here that: the sizes of the first, second, and third display sub-pixel units 531, 532, and 533 in the first direction D1 are the same as each other; the first trace portion 511 and the second trace portion 512 are both straight trace portions. As shown in fig. 2A and 2B, since the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 have the same size in the first direction D1, the length of the portion of the routing portion (e.g., the first routing portion 511) corresponding to the first display sub-pixel unit 531, the length of the portion of the routing portion (e.g., the first routing portion 511) corresponding to the second display sub-pixel unit 532, and the length of the portion of the routing portion (e.g., the first routing portion 511) corresponding to the third display sub-pixel unit 533 are the same as each other. As shown in fig. 2A, at the first viewing angle, since the portion of the routing portion (e.g., the first routing portion 511) corresponding to the second display sub-pixel unit 532 also overlaps the first signal line 541, at the first viewing angle, both the overlapping area of the routing portion (e.g., the first routing portion 511) and the first display sub-pixel unit 531 and the overlapping area of the routing portion (e.g., the first routing portion 511) and the third display sub-pixel unit 533 are larger than the overlapping area of the routing portion (e.g., the first routing portion 511) and the second display sub-pixel unit 532, that is, the light emitted by the backlight unit is shielded by the routing portion (e.g., the first routing portion 511) corresponding to the second display sub-pixel unit 532 to the minimum, and the intensity of the light incident on the second display sub-pixel unit 532 is the strongest; in this case, the display frame at the first viewing angle is biased to the color of the second display sub-pixel unit 532. For similar reasons, as shown in fig. 2B, the display frame at the second viewing angle is biased to the color of the first display sub-pixel unit 532 (i.e., the display sub-pixel unit in the column where the routing portion overlaps with the first signal line 541). Since the user views the liquid crystal display device 500 in a certain viewing angle range, the actual screen viewed by the user has color stripes. It should be noted that the portion of the trace portion corresponding to the display sub-pixel unit refers to a portion between two intersections of the trace portion and a boundary of the display sub-pixel unit (for example, a column of display sub-pixel units where the display sub-pixel unit is located) in the first direction.
The utility model discloses a designer notices again in studying, in order to avoid the grid line 510 periphery of the accuse light panel shown in fig. 1C probably to have dark state light leak problem for the width of the black matrix unit who shelters from grid line 510 increases, and this makes the rainbow line problem of the display device including the accuse light panel shown in fig. 1C comparatively serious. The following is an exemplary description with reference to fig. 3A-3C and fig. 4A and 4B.
FIG. 3A is another schematic plan view of the light-controlling panel 502 (the array substrate 551 of the light-controlling panel 502) shown in FIG. 1C. In contrast to fig. 1C, fig. 3A shows a pixel electrode comprised by a light-controlling pixel cell. FIG. 3B is a schematic cross-sectional view of the light management panel 502 shown in FIGS. 1C and 3A, the schematic cross-sectional view shown in FIG. 3B corresponding to line AA' shown in FIG. 3A.
As shown in fig. 3A and 3B, the light control panel 502 includes an array substrate 551 and an opposite substrate 552 that are opposite to each other and a liquid crystal layer 553 interposed between the array substrate 551 and the opposite substrate 552, and light incident to the light control panel 502 may be incident into the light control panel 502 from the array substrate 551 and may exit the light control panel 502 from the opposite substrate 552. As shown in fig. 3B, the opposite substrate 552 includes black matrix units 564 and a second base substrate 565.
As shown in fig. 3A and 3B, the array substrate 551 includes a data line layer, and a first substrate 561, a first electrode layer, an insulating layer (e.g., including a first insulating layer 562 or a second insulating layer 563), and a second electrode layer, which are sequentially disposed. The first electrode layer includes a plurality of gate lines 510, each of the plurality of gate lines 510 extending entirely in a first direction D1; the data line layer includes a plurality of data lines 521, each of the plurality of data lines 521 extends in a second direction D2 crossing the first direction D1 as a whole; a plurality of gate lines 510 and a plurality of data lines 521 cross each other to define a plurality of light-controlling pixel units 523; the second electrode layer includes a plurality of pixel electrodes 524 arranged in an array, and each of the plurality of pixel electrodes 524 is disposed in the plurality of light-controlling pixel units 523.
As shown in fig. 3A and 3B, an orthographic projection of the pixel electrode 524 on the first electrode layer does not overlap the gate line 510, and an electric field formed by the pixel electrode 524 and the gate line 510 enters the liquid crystal layer 553 located at the pixel electrode 524 away from the gate line 510. Since a voltage difference still exists between the pixel electrode 524 and the gate line 510 in a dark state (that is, a light-controlling unit where the light-controlling pixel unit 523 driven by the gate line 510 is located is theoretically in a light-tight state), an electric field formed by the pixel electrode 524 and the gate line 510 causes liquid crystal molecules near the gate line 510 to deviate from a predetermined orientation in the dark state, and causes the liquid crystal molecules near the gate line 510 to allow a part of light incident on the light-controlling panel 502 to pass through an area of the liquid crystal layer 553 corresponding to the gate line 510 and to be incident on the opposite substrate 552 in the dark state. If the counter substrate 552 includes the black matrix units 564 having a width equal to that of the corresponding gate lines 510, the light passes through the regions of the liquid crystal layer 553 corresponding to the gate lines 510 and is incident on the counter substrate 552, and then passes through the counter substrate 552 and exits the light control panel 502, in which case the regions of the light control panel 502 corresponding to the vicinity of the gate lines 510 will have a dark state light leakage problem. To avoid the above-mentioned dark state light leakage problem of the light control panel 502, the width of the black matrix unit 564 is greater than the width of the corresponding gate line 510.
FIG. 3C is another schematic cross-sectional view of the light management panel 502 shown in FIG. 3B. As shown in fig. 3C, a pitch L3 of an orthographic projection of the gate line 510 and the corresponding pixel electrode 524 on the first electrode layer in the fourth direction DA (i.e., in a direction perpendicular to an extending direction of the trace portion of the gate line 510) may be equal to 6 to 10 micrometers (e.g., 8 micrometers), and a pitch L1 of a side of the gate line 510 opposite to the fourth direction DA of an orthographic projection of the black matrix unit 564 on the first electrode layer may be equal to 18 to 22 micrometers (e.g., 20 micrometers); the difference between the width of the black matrix unit 564 in the fourth direction DA and the width of the corresponding gate line 510 in the fourth direction DA is equal to 2 × L1. For example, the width of the black matrix unit 564 in the fourth direction DA is equal to 52 micrometers to 60 micrometers (e.g., 56 micrometers), and the width of the gate line 510 in the fourth direction DA is equal to 12 micrometers to 20 micrometers (e.g., 16 micrometers).
For example, since the width of the black matrix unit 564 is large, the difference of the overlapping areas of the gate lines 510 (or the black matrix units 564) of the light control panel 502 and the display sub-pixels of different colors of the display panel 501 is large, and the difference of shielding of the areas of the gate lines 510 (or the black matrix units 564) corresponding to the display sub-pixels of different colors from the backlight unit is large, so that the difference of the intensities of the light incident on the display sub-pixels of different colors of the display panel 503 emitted by the backlight unit 503 is large, and the rainbow streak problem of the display device including the light control panel 501502 is serious.
FIG. 4A is an enlarged schematic plan view of the first region RE1 of the light control panel 502 shown in FIG. 3A. FIG. 4B is a schematic cross-sectional view of the light management panel 502 shown in FIG. 4A, the schematic cross-sectional view shown in FIG. 4B corresponding to the dashed line with arrows shown in FIG. 4A. It should be noted that, for convenience of description, fig. 4B also shows the common electrode 525 included in the light-controlling pixel unit 523.
As shown in fig. 4A and 4B, the pixel electrode 524 may include a plurality of stripe electrodes 5243 arranged in parallel in the first direction D1 and a first connection sub-electrode 5241 and a second connection sub-electrode 5242 as opposite sides of the pixel electrode 524 in the second direction D2, that is, the pixel electrode 524 may be implemented as a slit electrode. Note that the first and second connector electrodes 5241 and 5242 shown in fig. 4A and 4B respectively belong to two pixel electrodes 524 adjacent in the second direction D2. As shown in fig. 4B, the common electrode 525 is a plate-shaped electrode, and a spacing L2 between the common electrode 525 and the corresponding gate line 510 in the fourth direction DA may be equal to 6-10 micrometers (e.g., 7.5 micrometers). For example, a pitch L3 of the orthogonal projections of the gate lines 510 and the corresponding pixel electrodes 524 (the first connection sub-electrodes 5241 or the second connection sub-electrodes 5242) on the first electrode layer in the fourth direction DA is greater than a pitch L2 of the common electrodes 525 and the corresponding gate lines 510 in the fourth direction DA, whereby a portion of the common electrodes 525 is exposed from an interval between the orthogonal projections of the first connection sub-electrodes 5241 and the second connection sub-electrodes 5242 on the first electrode layer.
As shown in fig. 4A, the gate line 510 is located within a gap formed by two sides 5641 and 5642 of the black matrix unit 564 opposing in the fourth direction (perpendicular to the extending direction of the black matrix unit 564) in the orthographic projection of the black matrix unit 564 on the first electrode layer, that is, the gate line 510 is located within the orthographic projection of the black matrix unit 564 on the first electrode layer.
Fig. 4C is an enlarged schematic plan view of a partial area of another light management panel, and as shown in fig. 4C, the plurality of common electrode lines 522 are not limited to being implemented as straight lines parallel to the second direction D2, and may include a zigzag structure.
At least one embodiment of the present disclosure provides an array substrate, a light control panel and a display device. The array substrate comprises a data line layer, and a substrate, a first electrode layer, an insulating layer and a second electrode layer which are sequentially arranged. The first electrode layer comprises a plurality of grid lines, and each whole of the grid lines extends along a first direction and comprises a plurality of first folding line structures which are sequentially and directly connected with each other in the first direction; the data line layer comprises a plurality of data lines, and the whole of each data line extends along a second direction crossed with the first direction; a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of light-controlling pixel units; the second electrode layer comprises a plurality of common electrodes which are arranged in an array mode, and each common electrode is arranged in at least one of the light control pixel units; at least one of the plurality of gate lines at least partially overlaps with an orthographic projection of the at least one common electrode on the first electrode layer. By enabling at least one of the grid lines to at least partially overlap with the orthographic projection of the at least one common electrode on the first electrode layer, the array substrate can prevent an electric field formed by the grid lines and the common electrode from entering one side, far away from the first electrode layer, of the second electrode layer.
At least one embodiment of the present disclosure also provides a light control panel, including: the liquid crystal display device comprises an opposite substrate, a liquid crystal layer and an array substrate provided by at least one embodiment of the disclosure. The array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.
For example, by making at least one of the plurality of gate lines of the array substrate of the light control panel at least partially overlap with an orthographic projection of at least one common electrode on the first electrode layer, the light control panel has the capability of suppressing (e.g., completely suppressing) a dark-state light leakage problem of the light control panel without providing a black matrix layer or reducing the size of a black matrix cell of the black matrix layer, and suppressing a rainbow streak problem of a display device including the light control panel.
In the following, the array substrate and the light control panel provided according to the embodiments of the present disclosure are described in a non-limiting manner by several examples and embodiments, and as described below, different features of these specific examples and embodiments may be combined with each other without mutual conflict, so as to obtain new examples and embodiments, which also belong to the protection scope of the present disclosure.
FIG. 5 is a schematic cross-sectional view of a light management panel 10 provided by at least one embodiment of the present disclosure. Such as
As shown in fig. 5, the light management panel 10 includes: an array substrate 100 and a counter substrate 200 facing each other in the third direction D3, and a liquid crystal layer 300 interposed between the array substrate 100 and the counter substrate 200.
As shown in fig. 5, the array substrate 100 includes a data line layer (not shown in fig. 5) and a first substrate 101, a first electrode layer, an insulating layer (for example, the insulating layer may be one of the first insulating layer 102 and the second insulating layer 103), and a second electrode layer sequentially disposed (sequentially disposed in the third direction D3), the second electrode layer being closer to the liquid crystal layer 300 with respect to the first substrate 101.
As shown in fig. 5, the opposite substrate 200 includes a second substrate 210 and a black matrix layer 220. For example, the black matrix layer 220 is closer to the liquid crystal layer 300 with respect to the second substrate 210; the black matrix layer 220 includes a plurality of black matrix units 221 extending entirely in the first direction D1.
Fig. 6A is a schematic plan view of the array substrate 100 of the light-controlling panel 10 shown in fig. 5, and as shown in fig. 5 and 6A, the first electrode layer includes a plurality of gate lines 110, each of the plurality of gate lines 110 extends along the first direction D1 and includes a plurality of first folding line structures 111 sequentially and directly connected to each other in the first direction D1; the data line layer (not labeled in fig. 6A) includes a plurality of data lines 120, and each of the plurality of data lines 120 extends along the second direction D2; the plurality of gate lines 110 and the plurality of data lines 120 cross each other to define a plurality of light-controlling pixel units 130. For example, the first direction D1, the second direction D2, and the third direction D3 intersect each other (e.g., are perpendicular to each other).
For example, the light-controlling panel 10 may include a plurality of light-controlling units arranged in an array, and the plurality of light-controlling pixel units 130 of the array substrate 100 are respectively disposed at the corresponding light-controlling units. For example, the light controlling unit further includes a portion of the liquid crystal layer and a portion of the opposite substrate that overlap the light controlling pixel unit 130 in the third direction D3. For example, the light control panel may adjust the transmittance of each light control unit of the light control panel based on the data signal received by the light control panel, and thus, the light control unit of the light control panel may be used to control the intensity of light incident on the display sub-pixel unit of the display panel corresponding to the light control unit, and thus the light control panel may be used to provide adjusted backlight to the display panel of the display device including the light control panel.
For example, as shown in fig. 5 and 6A, each of the plurality of data lines 120 includes a plurality of second fold structures 121 directly connected in sequence in the second direction D2. It should be noted that the extension of each of the plurality of gate lines 110 along the first direction D1 only defines the extending direction of the gate line 110, and does not indicate that the trace included in the gate line 110 is parallel to the first direction D1. For example, the gate line 110 includes a first number (2 or more) of line segments, and some of the line segments may cross the first direction D1. Correspondingly, the extension of each of the plurality of data lines 120 along the second direction D2 defines only the extending direction of the data lines 120, and does not mean that the traces included in the data lines 120 are parallel to the second direction D2.
For example, the plurality of gate lines 110 include a plurality of first fold line structures 111 corresponding to the plurality of light-controlling pixel units 130, and the plurality of data lines 120 include a plurality of second fold line structures 121 corresponding to the plurality of light-controlling pixel units 130. For example, each of the plurality of light controlling pixel units 130 partially overlaps the corresponding gate line 110. For example, each of the plurality of light-controlling pixel units 130 partially overlaps the corresponding data line 120.
Fig. 6B is another schematic plan view of the array substrate 100 shown in fig. 6A. In contrast to the situation shown in figure 6A,
fig. 6B shows the common electrode 131 included in the light-controlling pixel unit 130, and the cross-sectional view shown in fig. 5 corresponds to the line AA' shown in fig. 6B. As shown in fig. 5, 6A and 6B, the second electrode layer includes a plurality of common electrodes 131 arranged in an array, and each of the plurality of common electrodes 131 is disposed in at least one of the plurality of light-controlling pixel units 130. For example, the plurality of common electrodes 131 and the plurality of light-controlling pixel units 130 are in one-to-one correspondence, and each of the plurality of common electrodes 131 is disposed (e.g., entirely located) in the corresponding light-controlling pixel unit 130.
As shown in fig. 5 and 6B, at least one of the plurality of gate lines 110 at least partially overlaps with an orthographic projection of the at least one common electrode 131 on the first electrode layer. For example, each of the plurality of gate lines 110 at least partially overlaps an orthographic projection of each common electrode 131 on the first electrode layer in one or two rows of common electrodes 131 adjacent to the gate line 110 in the second direction D2.
For example, the size of the orthographic projection of the gate line 110 and the corresponding common electrode 131 on the first electrode layer may be set according to practical application requirements (e.g., according to requirements of a light control panel and a display device for capacitance), which is not particularly limited in the embodiments of the present disclosure. For example, for a 65-inch display device, the overall size of the gate line 110 overlapping with the orthographic projection of the corresponding common electrode 131 on the first electrode layer may be located at more than 0 and less than or equal to G _ WL, where G _ WL is the width of the gate line 110. For example, in the case where the orthographic projections of the two common electrodes 131 on the first electrode layer overlap the gate line 110, the overall size refers to the sum of the overlapping sizes of the orthographic projections of the two common electrodes 131 on the first electrode layer and the gate line 110.
FIG. 7A is another schematic cross-sectional view of the light management panel 10 shown in FIG. 5. For example, the gate line 110 and the orthographic projection of the corresponding common electrode 131 on the first electrode layer slightly overlap, so that an electric field formed by the gate line 110 and the common electrode 131 overlapping with the gate line 110 can be prevented from entering one side of the second electrode layer far away from the first electrode layer. For example, as shown in fig. 5 and 7A, the slight overlap means: the width OV1 of the region of the gate line 110 overlapping the orthographic projection of the corresponding common electrode 131 on the first electrode layer in the fourth direction DA is greater than 0 and less than 1 micrometer. The fourth direction DA refers to a direction perpendicular to the extending direction of a line segment of the gate line 110. Since the extending directions of the plurality of line segments included in the gate line 110 are not completely the same, the fourth direction DA corresponding to different line segments of the gate line 110 may be different.
For example, the width OV1 of the region of the gate line 110 overlapping with the orthogonal projection of the corresponding common electrode 131 on the first electrode layer in the fourth direction DA (i.e., the direction perpendicular to the extending direction of the gate line 110) may be located between 3 micrometers and 7 micrometers (4 micrometers, 5 micrometers, or 6 micrometers). For example, by making the width OV1 of the region of the gate line 110 overlapping the orthographic projection of the corresponding common electrode 131 on the first electrode layer in the fourth direction DA be between 3 micrometers and 7 micrometers (4 micrometers, 5 micrometers, or 6 micrometers), it is possible to avoid both the problem that the orthographic projection of the gate line 110 and the corresponding common electrode 131 on the first electrode layer may not overlap in an actual product due to a potential alignment error between the gate line 110 and the corresponding common electrode 131, and the problem that the charging time required by the gate line 110 and the common electrode 131 is long due to an excessively large capacitance between the gate line 110 and the corresponding common electrode 131.
For example, by at least partially overlapping at least one of the plurality of gate lines 110 with an orthographic projection of at least one common electrode 131 on the first electrode layer, the array substrate 100 can prevent an electric field formed by the gate line 110 and the common electrode 131 overlapping with the gate line 110 from entering a side of the second electrode layer away from the first electrode layer (e.g., entering the liquid crystal layer 300 located at the side of the second electrode layer away from the first electrode layer). Therefore, although a voltage difference still exists between the common electrode 131 and the gate line 110 in a dark state (i.e., a light-controlling unit where the light-controlling pixel unit 130 driven by the gate line 110 is located is theoretically in a light-opaque state), an electric field formed by the common electrode 131 and the gate line 110 cannot make liquid crystal molecules near the gate line 110 deviate from a predetermined orientation in the dark state, and thus the light-controlling panel 10 including the array substrate 100 has an ability to suppress the dark-state light leakage problem of the light-controlling panel 10 without providing the black matrix layer 220 or reducing the size of the black matrix unit 221 of the black matrix layer 220.
For example, the gate line 110 may be formed using a metal material (e.g., copper, aluminum, or an aluminum alloy). For example, as shown in fig. 7A, orthographic projections of the gate lines 110 on the black matrix layer 220 are respectively located within the corresponding black matrix cells 221. For example, each of the plurality of black matrix units 221 includes a plurality of first black matrix structures (not labeled) directly connected in sequence in the first direction D1, and orthogonal projections of a plurality of first folding line structures 111 included in the plurality of gate lines 110 on the black matrix layer 220 are respectively located in the corresponding first black matrix structures.
For example, the extension tendency of each of the plurality of first black matrix structures is the same as that of the corresponding first folding line structure 11. It should be noted that the extending trend of each of the plurality of first black matrix structures is the same as the extending trend of the corresponding first fold line structure 11, which means that: each of the first black matrix structures has a first number of black matrix sub-structures, and an extending direction of each black matrix sub-structure of each first black matrix structure is the same as an extending direction of a corresponding line segment of a corresponding first fold line structure 111.
For example, by respectively locating orthographic projections of a plurality of gate lines 110 on the black matrix layer 220 within corresponding black matrix units 221, the black matrix units 221 can be utilized to suppress light reflection of the gate lines 110. For example, the width of the black matrix unit 221 in the fourth direction DA may be equal to the width of the corresponding gate line 110 in the fourth direction DA. For another example, the width of the black matrix unit 221 in the fourth direction DA may be greater than the width of the corresponding gate line 110 in the fourth direction DA, so that under the condition that an alignment error exists between the black matrix unit 221 and the gate line 110, orthographic projections of the plurality of gate lines 110 on the black matrix layer 220 can still be respectively located in the corresponding black matrix units 221, and thus, the effect of the black matrix unit 221 on suppressing light reflection of the gate lines 110 can be improved.
For example, the width of the black matrix unit 221 in the fourth direction DA may be set according to practical application requirements, which is not specifically limited by the embodiment of the disclosure. For example, a ratio of the width of each of the plurality of black matrix units 221 to the width of the corresponding gate line 110 is between 1-2.5 (e.g., 2). For example, as shown in fig. 7A, the difference between the width of the black matrix cells 221 in the fourth direction DA and the width of the corresponding gate lines 110 in the fourth direction DA is equal to 2 × L1, and the pitch L1 between the opposite sides of the gate lines 110 in the fourth direction DA and the opposite sides of the orthographic projection of the corresponding black matrix cells 221 on the first electrode layer in the fourth direction DA may be equal to 6-10 micrometers (e.g., 8 micrometers). For example, the width of the black matrix unit 221 in the fourth direction DA is equal to 28 micrometers to 36 micrometers (e.g., 32 micrometers), and the width of the gate line 110 in the fourth direction DA is equal to 12 micrometers to 20 micrometers (e.g., 16 micrometers).
For example, compared to the light management panel shown in fig. 3B and 4B, the light management panel 10 shown in fig. 5 reduces the size of the black matrix cells 221 of the black matrix layer 220, it is possible to reduce the difference in the overlapping area of the black matrix unit 221 of the light control panel 10 and the display sub-pixels of different colors of the display panel (the display panel of the display device including the light control panel 10), reduce the difference in the shielding of the backlight unit from the regions of the black matrix unit 221 corresponding to the display sub-pixels of different colors, thereby, the difference in the intensity of light emitted by the backlight unit (the backlight unit of the display device including the light control panel 10) and incident on the display sub-pixels of different colors of the display panel (the display panel of the display device including the light control panel 10) is reduced, and the rainbow streak problem of the display device including the light control panel 10 can be suppressed.
For example, the black matrix layer 220 further includes a plurality of second black matrix cells 221, each of the plurality of second black matrix cells 221 extending entirely in the second direction D2; orthographic projections of the data lines 120 on the black matrix layer 220 are respectively located in the corresponding second black matrix units 221. For example, each of the plurality of second black matrix units 221 includes a plurality of second black matrix structures directly connected in sequence in the second direction D2, and orthogonal projections of the plurality of second fold line structures 121 included in the plurality of gate lines 110 on the black matrix layer 220 are respectively located in the corresponding second black matrix structures.
Note that, in some examples, the counter substrate 200 may not be provided with the black matrix layer. Fig. 7B is a surface of a side of each of a plurality of gate lines of the array substrate, the side being close to the second electrode layer, according to at least one embodiment of the present disclosure. For example, as shown in fig. 7B, a surface of one side of each of the plurality of gate lines 110 close to the second electrode layer is a diffuse reflection surface and has a concave-convex structure 191 (i.e., a concave structure and a convex structure). For example, a pitch RU _ L between two adjacent protrusion structures on a surface of one side of each of the plurality of gate lines 110 close to the second electrode layer is less than 1 mm, and a pitch RU _ L between two adjacent recess structures on a surface of one side of each of the plurality of gate lines 110 close to the second electrode layer is less than 1 mm.
For example, compared to the light control panel shown in fig. 7A, by making the surface of the side close to the second electrode layer of each of the plurality of gate lines 110 a diffuse reflection surface and having the concave-convex structure 191, the gate line 110 has a small reflectance with respect to light incident on the surface of the side close to the second electrode layer of each of the plurality of gate lines 110, in this case, the counter substrate 200 may not be provided with a black matrix layer, thereby further reducing the difference in intensity of light of different colors incident on the display panel (the display panel of the display device including the light control panel 10) emitted by the backlight unit (the backlight unit of the display device including the light control panel 10), and further suppressing the rainbow streak problem of the display device including the light control panel 10.
For example, the width of the black matrix unit 221 may be equal to or greater than zero micrometers and equal to or less than 32 micrometers.
For example, as shown in fig. 5 and 6B, orthographic projections of two opposite sides of each of the plurality of common electrodes 131 in the second direction D2 on the first electrode layer are respectively overlapped (e.g., partially overlapped) with one side of the corresponding two gate lines 110 close to each of the plurality of common electrodes 131, so that the array substrate 100 can better prevent an electric field formed by the plurality of gate lines 110 and the common electrodes 131 overlapped with the plurality of gate lines 110 from entering one side of the second electrode layer far from the first electrode layer (e.g., entering the liquid crystal layer 300 on the side of the second electrode layer far from the first electrode layer).
For example, as shown in fig. 5 and 6B, a space is provided between two adjacent common electrodes 131 in the second direction D2, and the gate line 110 overlapping with both of the orthographic projections of the two adjacent common electrodes 131 in the second direction D2 on the first electrode layer overlaps with the orthographic projection of the space on the first electrode layer. For example, the orthographic projections of the above-mentioned intervals on the first electrode layer are located (e.g., entirely located) within the gate line 110 overlapping with the orthographic projections of the two adjacent common electrodes 131 in the second direction D2 on the first electrode layer.
For example, by providing a space between two adjacent common electrodes 131 in the second direction D2, an excessively large capacitance between the gate line 110 and the corresponding common electrode 131 can be avoided, and thus a potential problem of a long charging time required for the gate line 110 and the common electrode 131 can be avoided. In other examples, no space may be provided between two adjacent common electrodes 131 in the second direction D2, that is, two adjacent common electrodes 131 in the second direction D2 may directly contact or the gate line 110 may be completely covered by two adjacent common electrodes 131 in the second direction D2, thereby further improving the ability of the light control panel 10 to suppress dark-state light leakage.
For example, the specific shape of the common electrode 131 may be set according to practical application requirements, and embodiments of the present disclosure are not particularly limited in this regard. For example, the common electrode 131 may be a plate electrode or a slit electrode. Fig. 8A is a schematic plan view of the common electrode 131 provided in at least one embodiment of the present disclosure. As shown in fig. 8A, the common electrode 131 includes a plurality of stripe electrodes 132 arranged in parallel in the first direction D1 and a first connection sub-electrode 133 and a second connection sub-electrode 134 as opposite two sides of each of the plurality of common electrodes 131 in the second direction D2; the first connection sub-electrode 133 is connected to first ends of the plurality of stripe electrodes 132, and the second connection sub-electrode 134 is connected to second ends of the plurality of stripe electrodes 132.
Fig. 8B is an enlarged view of the first region RE1 of the array substrate 100 shown in fig. 6B, fig. 9A is an enlarged view of the second region RE2 of the array substrate 100 shown in fig. 6B, fig. 9B is a schematic cross-sectional view of the second region RE2 of the array substrate 100 shown in fig. 9A, and the schematic cross-sectional view shown in fig. 9B corresponds to a dotted line with arrows shown in fig. 9A. Fig. 10A is another schematic view of the array substrate 100 shown in fig. 6B. It should be noted that, for convenience of description, fig. 9B also shows the pixel electrode 135 included in the light-controlling pixel unit 130.
As shown in fig. 8B, 9A to 9B, and 10A, the common electrode 131 includes a plurality of stripe electrodes 132 arranged in parallel in the first direction D1 and a first connection sub-electrode 133 and a second connection sub-electrode 134 as opposite two sides of each of the plurality of common electrodes 131 in the second direction D2; the first connection sub-electrode 133 is connected to a first end of the plurality of stripe electrodes 132, and the second connection sub-electrode 134 is connected to a second end of the plurality of stripe electrodes 132; an orthogonal projection of the first connection sub-electrode 133 on the first electrode layer overlaps (e.g., partially overlaps or completely overlaps) a side of the corresponding gate line 110 near the first connection sub-electrode 133, and an orthogonal projection of the second connection sub-electrode 134 on the first electrode layer overlaps (e.g., partially overlaps or completely overlaps) a side of the corresponding gate line 110 near the second connection sub-electrode 134. For example, that the orthographic projection of the first connection sub-electrode 133 (or the second connection sub-electrode 134) on the first electrode layer completely overlaps with the side of the corresponding gate line 110 near the first connection sub-electrode 133 (or the second connection sub-electrode 134) means that the orthographic projection of the first connection sub-electrode 133 (or the second connection sub-electrode 134) on the first electrode layer is located within the gate line 110.
Note that the first connection sub-electrode 133 and the second connection sub-electrode 134 shown in fig. 9A and 9B respectively belong to two common electrodes 131 adjacent in the second direction D2. For example, the first and second connection sub-electrodes 133 and 134 shown in fig. 9A and 9B have a space therebetween, and the gate line 110 overlapping with both of the orthographic projections of the first and second connection sub-electrodes 133 and 134 on the first electrode layer overlaps with (e.g., partially overlaps with) the orthographic projection of the space on the first electrode layer.
For example, as shown in fig. 6B, 8A, 8B and 9A, each of the first and second connection sub-electrodes 133 and 134 has the same or similar shape as the corresponding first folding line structure 111 (the first folding line structure 111 of the plurality of gate lines 110 overlapping each of the first and second connection sub-electrodes 133 and 134 in the second direction D2); each of the plurality of stripe electrodes 132 has the same or similar shape as the corresponding second fold structure 121 (the second fold structure 121 of the plurality of data lines 120 overlapping each of the plurality of stripe electrodes 132 in the first direction D1).
For example, each of the first and second connection sub-electrodes 133 and 134 has the same extension tendency with the corresponding region of the plurality of gate lines 110 in the first direction D1, the corresponding region of the plurality of gate lines 110 being a region of the plurality of gate lines 110 overlapping with each of the first and second connection sub-electrodes 133 and 134 in the second direction D2 (i.e., the first folding structure 111 of the plurality of gate lines 110 overlapping with each of the first and second connection sub-electrodes 133 and 134 in the second direction D2); the plurality of stripe electrodes 132 and corresponding regions of the plurality of data lines 120 have the same extending trend in the second direction D2, and the corresponding regions of the plurality of data lines 120 are regions of the plurality of data lines 120 overlapping with the plurality of stripe electrodes 132 in the first direction D1 (i.e., the second fold line structures 121 of the plurality of data lines 120 overlapping with each of the plurality of stripe electrodes 132 in the first direction D1).
It should be noted that each of the first and second connection sub-electrodes 133 and 134 and the corresponding region of the plurality of gate lines 110 have the same extension tendency in the first direction D1, which means that: each of the first and second connection sub-electrodes 133 and 134 has a first number of electrode segments, and an extending direction of each electrode segment of each of the first and second connection sub-electrodes 133 and 134 is the same as an extending direction of a corresponding line segment of the corresponding first fold line structure 111; the strip-shaped electrodes 132 and the corresponding regions of the data lines 120 have the same extending trend in the second direction D2, which is: the plurality of stripe electrodes 132 have a second number of electrode segments (the second fold line structure 121 includes segments of the second data), and the extending direction of each electrode segment of each stripe electrode 132 is the same as the extending direction of the corresponding segment of the corresponding second fold line structure 121.
For example, as shown in fig. 6B, 8A, 8B, 9A and 10A, each of the plurality of first fold structures 111 includes a first trace portion (i.e., a line segment) 122 and a second trace portion 113 that are directly connected in sequence, and each of the first trace portion 112 and the second trace portion 113 intersects with the first direction D1 and the second direction D2; each of the first and second connection sub-electrodes 133 and 134 includes a first electrode portion 1131 and a second electrode portion 1132 which are directly connected in sequence, and each of the first electrode portion (electrode segment) 1131 and the second electrode portion 1132 intersects with the first direction D1 and the second direction D2. For example, the extending direction of the first trace portion 112 and the extending direction of the second trace portion 113 are equal to the extending direction of the first electrode portion 1131 and the extending direction of the second electrode portion 1132, respectively. For example, the first electrode portion 1131 and the second electrode portion 1132 overlap with the first trace portion 112 and the second trace portion 113, respectively, in the second direction D2.
For example, as shown in fig. 6B, 8A, 8B, 9A and 10A, each of the plurality of second fold structures 121 includes a third trace portion 122 and a fourth trace portion 123 directly connected in sequence, and each of the third trace portion 122 and the fourth trace portion 123 intersects with the first direction D1 and the second direction D2. Each of the plurality of stripe electrodes 132 includes third and fourth electrode portions 1321 and 1322 directly connected in sequence, each of the third and fourth electrode portions 1321 and 1322 intersecting the first and second directions D1 and D2. For example, the extending direction of the third trace portion 122 and the extending direction of the fourth trace portion 123 are the same as the extending direction of the third electrode portion 1321 and the extending direction of the fourth electrode portion 1322, respectively. For example, the third electrode portion 1321 and the fourth electrode portion 1322 overlap the third trace portion 122 and the fourth trace portion 123, respectively, in the first direction D1.
It should be noted that the first folding line structure 111 and the first connection sub-electrode 133 (or the second connection sub-electrode 134) of the array substrate 100 provided in at least one embodiment of the present disclosure are not limited to the structures shown in fig. 6B and fig. 8A, and the first folding line structure 111 and the first connection sub-electrode 133 (or the second connection sub-electrode 134) of the array substrate 100 provided in at least one embodiment of the present disclosure may also adopt the structure shown in fig. 10B according to practical application requirements.
Fig. 10B is a schematic plan view of another first folding structure 111 and a first connection sub-electrode 133 (or a second connection sub-electrode 134) provided in at least one embodiment of the present disclosure. As shown in fig. 10B, the first fold structure 111 further includes a fifth trace portion 114, a sixth trace portion 115, and a seventh trace portion 116, and each of the first and second connection sub-electrodes 133 and 134 further includes a fifth electrode portion 1133, a sixth electrode portion 1134, and a seventh electrode portion 1135.
For example, the extending direction of the fifth trace portion 114, the extending direction of the sixth trace portion 115 and the extending direction of the seventh trace portion 116 are respectively equal to the extending direction of the fifth electrode portion 1133, the extending direction of the sixth electrode portion 1134 and the extending direction of the seventh electrode portion 1135. For example, each of the fifth trace portion 114, the sixth trace portion 115, the seventh trace portion 116, the fifth electrode portion 1133, the sixth electrode portion 1134 and the seventh electrode portion 1135 is parallel to the first direction D1.
For example, as shown in fig. 10B, the fifth trace portion 114, the first trace portion 112, the sixth trace portion 115, the second trace portion 113 and the seventh trace portion 116 are sequentially connected in the first direction D1; the fifth electrode portion 1133, the first electrode portion 1131, the sixth electrode portion 1134, the second electrode portion 1132, and the seventh electrode portion 1135 are sequentially connected in the first direction D1. For example, the seventh trace portion 116 of each first fold structure 111 is directly connected to the fifth trace portion 114 of the first fold structure 111 located at the right side thereof, and the seventh electrode portion 1135 of each first connecting sub-electrode 133 (or the second connecting sub-electrode 134) is directly connected to the fifth electrode portion 1133 of the first connecting sub-electrode 133 (or the second connecting sub-electrode 134) located at the right side thereof.
For example, an orthographic projection of each of the plurality of data lines 120 on the first electrode layer overlaps at least one of the fifth trace portion 114 and the seventh trace portion 116 of the corresponding first fold line structure 111.
For example, as shown in fig. 9A, the gate line 110 is located within a gap formed by two opposite sides 2211 and 2212 in the fourth direction DA (perpendicular to the extending direction of the black matrix unit 221) by the orthographic projection of the black matrix unit 221 on the first electrode layer, that is, the gate line 110 is located within the orthographic projection of the black matrix unit 221 on the first electrode layer.
For example, as shown in fig. 9B, the first electrode layer further includes a plurality of pixel electrodes 135; each of the plurality of pixel electrodes 135 is disposed (e.g., entirely located) in a corresponding light-controlling pixel unit 130. For example, the plurality of pixel electrodes 135 and the plurality of light-controlling pixel units 130 correspond one to one. For example, the plurality of pixel electrodes 135 are disposed apart from each other, and the plurality of pixel electrodes 135 are not electrically connected to each other; as shown in fig. 9B, a plurality of pixel electrodes 135 are disposed to be spaced apart from the plurality of gate lines 110. For example, the width L2 of the space between each gate line 110 and the corresponding pixel electrode 135 in the fourth direction DA may be set according to practical application requirements, and this is not particularly limited by the embodiments of the present disclosure. For example, the width L2 of the space between each gate line 110 and the corresponding pixel electrode 135 in the fourth direction DA may be equal to 6-10 micrometers (e.g., 7.5 micrometers).
For example, as shown in fig. 9B, each of the plurality of pixel electrodes 135 is a plate-like electrode, and an orthographic projection of the plate-like electrode on the second electrode layer is a continuous plane. For example, as shown in fig. 9B, slits are formed between the plurality of stripe electrodes 132, and the orthographic projection of the pixel electrode 135 on the second electrode layer is exposed from the slits, so that the electric field formed by the pixel electrode 135 and the common electrode 131 can enter the side of the second electrode layer away from the first electrode layer (into the liquid crystal layer 300), and drive the liquid crystal molecules in the liquid crystal layer 300 to rotate as required.
For example, the pixel electrode 135 and the gate line 110 are formed in different patterning processes, respectively. For example, the pixel electrode 135 may be formed using a transparent conductive material. For example, the transparent conductive material is Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). For example, by making the first electrode layer include a plurality of gate lines 110 and a plurality of pixel electrodes 135 at the same time, the number of insulating layers disposed in a direction perpendicular to the first substrate base 101 may be reduced, and thus the thickness of the array substrate 100 may be reduced.
For example, as shown in fig. 10A, each light-controlling pixel unit 130 further includes a switching element 151, and the switching element 151 is, for example, a thin film transistor; the thin film transistor includes a gate electrode, a source electrode, and a drain electrode. For example, the gate electrode of the thin film transistor is at the same layer and electrically connected to the gate line 110, one of the source and drain electrodes of the thin film transistor is at the same layer and electrically connected to the data line 120, and the other of the source and drain electrodes of the thin film transistor is electrically connected to the pixel electrode 135 (e.g., electrically connected via a via hole). For example, the pixel electrode 135 is configured to receive a data signal provided by the data line 120. For example, the data signals received by the pixel electrodes 135 included in different light-controlling pixel units 130 may not be identical and may vary according to the display requirements. For example, the number of the switching elements 151 is equal to the number of the plurality of first folding line structures 111.
For example, the gate line 110 is configured to receive a gate scan signal. For example, the gate lines 110, the data lines 120, and the common electrode lines 140 are configured to be connected to different signal sources.
For example, as shown in fig. 6A, 6B and 10A, the array substrate 100 further includes a plurality of common electrode lines 140, each of the plurality of common electrode lines 140 extends along the second direction D2 in its entirety, and includes a plurality of third fold line structures 141 directly connected in sequence in the second direction D2. For example, the common electrode 131 is configured to receive a common voltage signal, for example, the common voltage signal is a constant voltage signal. For example, the plurality of common electrodes 131 are configured to be electrically connected to each other via the plurality of common electrode lines 140 such that the plurality of common voltage signals on the plurality of common electrodes 131 are identical to each other. For example, the common electrode lines 140 are alternately arranged with the data lines 120 in the first direction D1.
For example, as shown in fig. 6A, 6B and 10A, each of the plurality of third hinge structures 141 includes an eighth trace portion 142 and a ninth trace portion 143 that are directly connected in sequence, and each of the eighth trace portion 142 and the ninth trace portion 143 intersects the first direction D1 and the second direction D2. For example, the extending direction of the eighth routing portion 142 and the extending direction of the ninth routing portion 143 are the same as the extending direction of the third electrode portion 1321 and the extending direction of the fourth electrode portion 1322, respectively. For example, the eighth and ninth routing portions 142 and 143 overlap the third and fourth electrode portions 1321 and 1322, respectively, in the first direction D1.
For example, an orthographic projection of each of the plurality of common electrode lines 140 on the first electrode layer overlaps an intersection of the first trace portion 112 and the second trace portion 113 of the corresponding first fold line structure 111. For another example, an orthographic projection of each of the plurality of common electrode lines 140 on the first electrode layer overlaps with the corresponding sixth routing portion 115 of the first fold line structure 111.
For example, the common electrode 131 may be formed using a transparent conductive material. For example, the transparent conductive material is Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). For another example, the common electrode 131 may be formed using a metal material. For example, the first and second substrate boards 101 and 210 may be transparent boards. For example, the transparent substrate may be a glass substrate, a quartz substrate, a plastic substrate (e.g., a polyethylene terephthalate (PET) substrate), or a substrate made of other suitable materials. For example, the first insulating layer 102 and the second insulating layer 103 may be formed using an inorganic or organic material. For example, the first insulating layer 102 and the second insulating layer 103 may be formed using an organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride (SiNx). For example, the data line 120 may be formed using a metal material (e.g., copper, aluminum, or an aluminum alloy). For example, a data line layer may be disposed between the first insulating layer 102 and the second insulating layer 103.
At least one embodiment of the present disclosure also provides a display device 01. For example. The display device 01 may be implemented as a display device based on ADS (advanced super-dimensional field conversion technology) or a display device based on IPS-ADS (i.e., i-ADS, in-plane conversion-advanced super-dimensional field conversion technology) technology.
Fig. 11 is a schematic cross-sectional view of a display device 01 provided in at least one embodiment of the present disclosure. As shown in fig. 11, the display device 01 includes a display panel 30, a backlight unit 20, and any one of the light control panels 10 provided by at least one embodiment of the present disclosure, which are stacked on each other in a third direction D3. The display panel 30 is located at the light emitting side of the light control panel 10, and the backlight unit 20 is located at the side of the light control panel 10 away from the display panel 30. For example, as shown in fig. 11, the display panel 30, the light control panel 10 and the backlight unit 20 are sequentially disposed in the third direction D3. For example, the array substrate 100 of the light control panel 10 is closer to the backlight unit 20 than the opposite substrate 201 of the light control panel 10.
Fig. 12A is a schematic plan view of the display panel 30 of the display device 01 shown in fig. 11. As shown in fig. 12A, the display panel 30 includes a plurality of first signal lines 305 extending in a first direction D1 and a plurality of second signal lines 306 extending in a second direction D2; the plurality of first signal lines 305 and the plurality of second signal lines 306 intersect to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 304 arranged in an array. For example, the first signal lines 305 are gate lines of the display panel 20, and the second signal lines 306 are data lines of the display panel 30. For example, the plurality of first signal lines 305 and the plurality of second signal lines 306 are connected to different signal sources.
As shown in fig. 12A, each display pixel unit 304 includes a first display sub-pixel unit 3041, a second display sub-pixel unit 3042, and a third display sub-pixel unit 3043; the first display sub-pixel unit 3041, the second display sub-pixel unit 3042, and the third display sub-pixel unit 3043 are, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit, respectively.
Fig. 12B is a schematic plan view of the display device 01 shown in fig. 11. For example, as shown in fig. 12B, the size of each light-controlling pixel unit 130 in the first direction D1 is equal to twice the size of each display pixel unit 304 in the first direction D1, and the size of each light-controlling pixel unit 130 in the second direction D2 is equal to or slightly smaller than four times the size of each display pixel unit 304 in the second direction D1.
For example, the display device 01 further includes an isotropic diffusion film (not shown) disposed between the display panel 30 and the light control panel 10. The isotropic diffusion film may diffuse light emitted from the light control panel 10 within a small angle range, thereby blurring the pattern of the data lines to further eliminate moire, and at the same time, may not have a large influence on the direction of the light emitted from the light control panel 10.
For example, the display device 01 may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. It should be noted that, for other components of the display device 01 (for example, the control device, the image data encoding/decoding device, the row scan driver, the column scan driver, the clock circuit, etc.), suitable components can be adopted, which should be understood by those skilled in the art, and are not described herein again, nor should be taken as a limitation to the present disclosure.
Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.
The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.
Claims (16)
1. The array substrate comprises a data line layer, and sequentially arranged substrate, first electrode layer, insulating layer and second electrode layer,
the first electrode layer comprises a plurality of grid lines, and each whole of the grid lines extends along the first direction and comprises a plurality of first folding line structures which are sequentially and directly connected with each other in the first direction;
the data line layer includes a plurality of data lines, each of the plurality of data lines extending entirely in a second direction crossing the first direction;
the plurality of gate lines and the plurality of data lines cross each other to define a plurality of light-controlling pixel units;
the second electrode layer comprises a plurality of common electrodes arranged in an array, and each common electrode is arranged in at least one of the light control pixel units; and
at least one of the plurality of gate lines at least partially overlaps with an orthographic projection of at least one of the common electrodes on the first electrode layer.
2. The array substrate of claim 1, wherein orthographic projections of two opposite sides of each of the plurality of common electrodes in the second direction on the first electrode layer are respectively overlapped with one sides of the corresponding two gate lines close to each of the plurality of common electrodes.
3. The array substrate according to claim 2, wherein a space is provided between two adjacent common electrodes in the second direction, and a gate line overlapping with orthogonal projections of the two adjacent common electrodes in the second direction on the first electrode layer overlaps with an orthogonal projection of the space on the first electrode layer.
4. The array substrate of any of claims 1-3, wherein each of the plurality of common electrodes comprises: a plurality of stripe-shaped electrodes arranged in parallel in the first direction and a first connection sub-electrode and a second connection sub-electrode as two opposite sides of each of the plurality of common electrodes in the second direction;
the first connector electrode is connected with the first ends of the strip electrodes, and the second connector electrode is connected with the second ends of the strip electrodes; and
orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer are respectively overlapped with one side of each of the two corresponding grid lines close to the plurality of common electrodes.
5. The array substrate of claim 4, wherein each of the first and second connection sub-electrodes has the same extension tendency as a corresponding region of the plurality of gate lines, the corresponding region of the plurality of gate lines being a region of the plurality of gate lines overlapping with each of the first and second connection sub-electrodes in the second direction; and
the plurality of strip-shaped electrodes and corresponding regions of the plurality of data lines have the same extension trend, and the corresponding regions of the plurality of data lines are regions of the plurality of data lines which are overlapped with the plurality of strip-shaped electrodes in the first direction.
6. The array substrate of claim 4, wherein each of the plurality of data lines comprises a plurality of second fold line structures directly connected in sequence in the second direction; and
the plurality of first fold line structures that many grid lines include with a plurality of accuse light pixel unit one-to-one, a plurality of second fold line structures that many data lines include with a plurality of accuse light pixel unit one-to-one.
7. The array substrate of any of claims 1-3, wherein the first electrode layer further comprises a plurality of pixel electrodes;
each of the plurality of pixel electrodes is arranged in the corresponding light control pixel unit; and
the plurality of pixel electrodes and the plurality of grid lines are arranged at intervals.
8. The array substrate of claim 7, wherein the pixel electrode is a plate electrode, and an orthographic projection of the plate electrode on the second electrode layer is a continuous plane.
9. The array substrate of claim 8, wherein each of the plurality of common electrodes comprises: a plurality of stripe-shaped electrodes arranged in parallel in the first direction and a first connection sub-electrode and a second connection sub-electrode as two opposite sides of each of the plurality of common electrodes in the second direction;
the first connector electrode is connected with the first ends of the strip electrodes, and the second connector electrode is connected with the second ends of the strip electrodes;
orthographic projections of the first connecting sub-electrode and the second connecting sub-electrode on the first electrode layer are respectively overlapped with one side of each of the two corresponding grid lines close to the plurality of common electrodes; and
orthographic projections of the pixel electrodes on the second electrode layer are exposed from gaps between adjacent strip-shaped electrodes included in the corresponding common electrode.
10. The array substrate of claim 7, wherein each of the plurality of common electrodes and the pixel electrode comprises a transparent conductive oxide, and each of the plurality of gate lines comprises a metal.
11. The array substrate of any one of claims 1 to 3, wherein a surface of each of the plurality of gate lines on a side thereof adjacent to the second electrode layer has a relief structure.
12. A light management panel, comprising: the array substrate, the opposite substrate and the liquid crystal layer according to any one of claims 1 to 11,
the array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.
13. The light management panel of claim 12, wherein the counter substrate comprises a black matrix layer;
the black matrix layer comprises a plurality of black matrix units, and each whole of the plurality of black matrix units extends along the first direction; and
orthographic projections of the grid lines on the black matrix layer are respectively located in the corresponding black matrix units.
14. The light management panel of claim 13, wherein each of the plurality of black matrix units comprises a plurality of black matrix structures directly connected in sequence in the first direction, and orthogonal projections of a plurality of first folding line structures included in the plurality of gate lines on the black matrix layer are respectively located in the corresponding black matrix structures.
15. The light management panel of claim 13 or 14, wherein the ratio of the width of each of the plurality of black matrix units to the width of the corresponding gate line is between 1-2.5.
16. A display device, comprising: display panel, backlight unit and light management panel according to any of claims 12-15,
the display panel, the light control panel and the backlight unit are arranged in a stacked mode, the display panel is located on the light emitting side of the light control panel, and the backlight unit is located on one side, far away from the display panel, of the light control panel.
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| CN201921976113.XU CN210514885U (en) | 2019-11-15 | 2019-11-15 | Array substrate, light control panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115728988A (en) * | 2021-08-27 | 2023-03-03 | 京东方科技集团股份有限公司 | Front light source module and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115728988A (en) * | 2021-08-27 | 2023-03-03 | 京东方科技集团股份有限公司 | Front light source module and display device |
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