CN210376953U

CN210376953U - Array substrate, light control panel and display device

Info

Publication number: CN210376953U
Application number: CN201921378641.5U
Authority: CN
Inventors: 郭远辉; 高玉杰; 郭威; 郭坤; 廖燕平
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2019-08-23
Filing date: 2019-08-23
Publication date: 2020-04-21
Anticipated expiration: 2029-08-23

Abstract

An array substrate, a light control panel and a display device are provided. The array substrate comprises a plurality of grid lines extending along a first direction, a plurality of data lines extending along a second direction intersecting with the first direction and a plurality of light control pixel units. Each grid line comprises a plurality of grid parts which are arranged in parallel along the first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines. The array substrate can improve the display effect of a display device comprising the array substrate.

Description

Array substrate, light control panel and display device

Technical Field

Embodiments of the present disclosure relate to an array substrate, a light control panel and a display device.

Background

The liquid crystal display device comprises a backlight module and a liquid crystal panel, wherein the backlight module is arranged on the non-display side of the liquid crystal panel to provide a light source for the display operation of the display panel. The liquid crystal panel includes a polarizer, an array substrate, a counter substrate, and a liquid crystal molecular layer filled between the two substrates. The liquid crystal display device enables liquid crystal molecules in a liquid crystal molecule layer to deflect by forming an electric field between the array substrate and the opposite substrate, and the deflected liquid crystal molecules can form a liquid crystal light valve by matching with the polarizer. Since the liquid crystal molecule layer does not emit light, the display function needs to be realized by the backlight module. With the continuous development of display technologies, users have made higher and higher requirements on contrast, brightness uniformity, and the like of display devices.

SUMMERY OF THE UTILITY MODEL

At least one embodiment of the present disclosure provides an array substrate. The array substrate comprises a plurality of grid lines extending along a first direction, a plurality of data lines extending along a second direction intersecting with the first direction, and a plurality of light control pixel units. Each grid line comprises a plurality of grid parts which are arranged in parallel along the first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines.

For example, in at least one example of the array substrate, the grid lines of each grid portion include a first fold line trace and a second fold line trace; the starting point of the first fold line is connected with the starting point of the second fold line; the terminal point of the first fold line is connected with the terminal point of the second fold line; and the vertex of the first fold line and the vertex of the second fold line are arranged at intervals in the second direction.

For example, in at least one example of the array substrate, the first folding line includes a first line segment and a second line segment that are sequentially connected, and a connection point of the first line segment and the second line segment is a vertex of the first folding line; the second fold line routing comprises a third line segment and a fourth line segment which are sequentially connected, and the connection point of the third line segment and the fourth line segment is the vertex of the second fold line routing; and the absolute value of the acute angle included angle of the first line segment and the first direction, the absolute value of the acute angle included angle of the second line segment and the first direction, the absolute value of the acute angle included angle of the third line segment and the first direction and the absolute value of the acute angle included angle of the fourth line segment and the first direction are between 38 degrees and 55 degrees.

For example, in at least one example of the array substrate, an absolute value of an acute angle between the first line segment and the first direction, an absolute value of an acute angle between the second line segment and the first direction, an absolute value of an acute angle between the third line segment and the first direction, and an absolute value of an acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

For example, in at least one example of the array substrate, the first folding line and the second folding line are symmetrical with respect to a connection line between a starting point of the first folding line and an end point of the first folding line.

For example, in at least one example of the array substrate, the first line segment and the second line segment are symmetrical with respect to a connection line between a vertex of the first folded line trace and a vertex of the second folded line trace; and the third line segment and the fourth line segment are symmetrical relative to the connection line of the vertex of the first fold line and the vertex of the second fold line.

For example, in at least one example of the array substrate, each of the data lines has two overlapping positions with a grid line of a corresponding grid portion in a direction perpendicular to the array substrate, or a connection with two adjacent grid portions overlaps in a direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, the array substrate further includes a common electrode line extending along the second direction. The connection point of the common electrode line and two adjacent grid parts is overlapped in the direction perpendicular to the array substrate, or the grid line of one corresponding grid part has two overlapped positions in the direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, an opening region surrounded by each of the mesh portions and one or two of the light-controlling pixel units partially overlap in a direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, the boundary trace of each light-controlling pixel unit is formed by the corresponding data line and the first fold line trace of the grid part corresponding to the gate line; and the second fold line routing of the grid part of each grid line passes through the inside of the corresponding light control pixel unit.

For example, in at least one example of the array substrate, the array substrate further includes a common electrode line extending in the second direction. The connection positions of the common electrode wires and the two adjacent grid parts are overlapped in the direction vertical to the array substrate; the boundary routing of each light control pixel unit is formed by the corresponding common electrode wire and the first fold line routing of the grid part corresponding to the grid line; and the second fold line routing of the grid part of each grid line passes through the inside of the corresponding light control pixel unit.

For example, in at least one example of the array substrate, each of the light-controlling pixel units further includes a switching element and a pixel electrode; the switch element comprises a grid electrode, a source electrode and a drain electrode, the grid electrode of the switch element is electrically connected with the corresponding second fold line routing, and one of the source electrode and the drain electrode of the switch element is electrically connected with the pixel electrode; and the number of the switch elements is equal to the number of the second fold lines.

For example, in at least one example of the array substrate, the widths of the first folding line trace and the second folding line trace are both between 9 micrometers and 11 micrometers.

For example, in at least one example of the array substrate, the grid lines of each grid portion include a first fold line trace and a second fold line trace; the starting point of the first folding line is connected with the starting point of the second folding line, and the end point of the first folding line is connected with the end point of the second folding line; the vertex of the first fold line and the vertex of the second fold line are arranged at intervals in the second direction; the first fold line comprises a first line segment and a second line segment which are sequentially connected, and the connection point of the first line segment and the second line segment is the vertex of the first fold line; the second fold line routing comprises a third line segment and a fourth line segment which are sequentially connected, and the connection point of the third line segment and the fourth line segment is the vertex of the second fold line routing; the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 and 48 degrees; the first folding line and the second folding line are symmetrical relative to a connection line of a starting point of the first folding line and an end point of the first folding line; the first line segment and the second line segment are symmetrical relative to a connecting line of a vertex of the first fold line and a vertex of the second fold line; the third line segment and the fourth line segment are symmetrical relative to a connecting line of a vertex of the first folded wire and a vertex of the second folded wire; each data line and the grid line of one corresponding grid part have two overlapping positions in the direction perpendicular to the array substrate; the array substrate further comprises a common electrode line extending along the second direction, and the connection positions of the common electrode line and two adjacent grid parts are overlapped in the direction perpendicular to the array substrate; the opening area surrounded by each grid part and the two light control pixel units are partially overlapped in the direction perpendicular to the array substrate; the boundary routing of the light control pixel unit is formed by the corresponding data line and the first fold routing of the grid part corresponding to the grid line, and the second fold routing of the grid part of each grid line passes through the inside of the corresponding light control pixel unit; each light-control pixel unit further comprises a switching element and a pixel electrode; the switching element comprises a grid electrode, a source electrode and a drain electrode, the grid electrode of the switching element is electrically connected with the corresponding second fold line routing, one of the source electrode and the drain electrode of the switching element is electrically connected with the pixel electrode, and the number of the switching elements is equal to that of the second fold line routing.

At least one embodiment of the present disclosure also provides a light control panel including an opposite substrate, a liquid crystal layer, and any one of the array substrates provided by at least one embodiment of the present disclosure. The array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.

At least one embodiment of the present disclosure also provides a display device including: display panel, backlight unit and any light control panel that at least one embodiment of this disclosure provided. The display panel is located on the light emitting side of the light control panel, and the backlight unit is located on one side, far away from the display panel, of the light control panel.

For example, in at least one example of the display device, the display panel includes a plurality of display pixel units arranged in an array; the size of each grid part in the first direction is equal to twice the size of each display pixel unit in the first direction; and the size of each grid part in the second direction is less than or equal to twice the size of each display pixel unit in the second direction.

For example, in at least one example of the display device, a size of each of the light-controlling pixel cells in the first direction is equal to twice a size of each of the display pixel cells in the first direction; and the size of each light control pixel unit in the second direction is equal to 2.5-3 times the size of each display pixel unit in the first direction.

At least one embodiment of the present disclosure also provides a method for manufacturing an array substrate, including: forming a plurality of gate lines extending in a first direction, respectively; a plurality of data lines are formed to extend in second directions respectively intersecting the first directions. The plurality of grid lines and the plurality of data lines intersect to define a plurality of light control pixel units, each grid line comprises a plurality of grid parts which are arranged in parallel along the first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A shows a schematic cross-sectional view of a liquid crystal display device;

FIG. 1B shows a schematic plan view of a light management panel and a display panel of the liquid crystal display device shown in FIG. 1A;

FIG. 1C illustrates a light-controlling pixel cell of the light-controlling panel shown in FIG. 1A;

FIG. 2A is a schematic diagram illustrating a gate line blocking condition of the LCD device shown in FIG. 1A at a first viewing angle;

FIG. 2B is a schematic diagram illustrating a shielding of the gate lines of the LCD device shown in FIG. 1A at a second viewing angle;

fig. 3 is a schematic plan view of an array substrate provided by at least one embodiment of the present disclosure;

fig. 4 is a schematic plan view illustrating a gate line of the array substrate shown in fig. 3;

fig. 5 is a schematic plan view illustrating switching elements and pixel electrodes of the array substrate shown in fig. 3;

fig. 6A illustrates a schematic plan view of another array substrate provided by at least one embodiment of the present disclosure;

fig. 6B is a schematic plan view illustrating another gate line of an array substrate provided by at least one embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional view of a light management panel provided by at least one embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure;

fig. 9A is a schematic plan view of a display panel of the display device shown in fig. 8;

FIG. 9B is a schematic plan view of the display device shown in FIG. 8;

FIG. 10 is a schematic plan view of a mesh portion of the display device shown in FIG. 9B; and

fig. 11 is a schematic plan view of a pixel unit of the display device shown in fig. 9B.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure provides a liquid crystal display device, which has a low contrast ratio of a display screen, and a method for manufacturing the same, and a liquid crystal display device having the same. The utility model discloses a utility model designer notices in studying, can adopt the liquid crystal display device who has two liquid crystal cells to promote the contrast of display screen, and the following is exemplified in connection with fig. 1.

Fig. 1A shows a schematic cross-sectional view of a liquid crystal display device 500. As shown in fig. 1A, the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502, and a display panel 501, which are sequentially disposed. Fig. 1B shows a schematic plan view of the light control panel 502 and the display panel 501 of the liquid crystal display device 500 shown in fig. 1A. For example, the light control panel 502 is configured to adjust the intensity of light emitted by the backlight unit 503 and incident on the display panel 501.

As shown in fig. 1B, the display panel 501 includes a plurality of first signal lines 541 extending in a first direction D1 and a plurality of second signal lines 542 extending in a second direction D2; the plurality of first signal lines 541 and the plurality of second signal lines 542 intersect to define a plurality of display pixel units 530; each display pixel unit 530 includes a first display sub-pixel unit 531, a second display sub-pixel unit 532, and a third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532 and the third display sub-pixel unit 533 are, for example, a red display sub-pixel unit, a green display sub-pixel unit and a blue display sub-pixel unit, respectively. For example, the first direction D1 is perpendicular to the second direction D2. For example, the first signal lines 541 are gate lines of the display panel 501, and the second signal lines 542 are data lines of the display panel 501.

As shown in fig. 1B, the light control panel 502 includes a plurality of gate lines 510 respectively extending in a first direction D1 and a plurality of data lines 521 respectively extending in a second direction D2 crossing the first direction D1; the plurality of gate lines 510 and the plurality of data lines 521 intersect to define a plurality of light-controlling pixel cells 523. For example, the width of the first signal line 541 is greater than the width of the gate line 510. For example, the sizes of the first, second, and third display

sub-pixel units

531, 532, and 533 in the first direction D1 are the same as each other, and for example, the sizes of the first, second, and third display

sub-pixel units

531, 532, and 533 in the second direction D2 are the same as each other.

As shown in fig. 1B, each gate line 510 is implemented as a meander line trace; each gate line 510 includes a plurality of first line segments 511 and a plurality of second line segments 512, the plurality of first line segments 511 and the plurality of second line segments 512 are alternately arranged, and the adjacent first line segments 511 and second line segments 512 are connected to each other. As shown in fig. 1B, the included angle (acute angle) between the first line segment 511 (or/and the second line segment 512) and the first direction D1 is about 50-70 degrees, so as to reduce the moire problem of the liquid crystal display device 500. For example, the first line segment 511 and the second line segment 512 are both straight line segments.

FIG. 1C shows light-controlling pixel cell 523 of light-controlling panel 502 shown in FIG. 1A. As shown in fig. 1C, the size of the light-controlling pixel unit 523 in the first direction D1 is L1, and the size of the light-controlling pixel unit 523 in the second direction D2 is L2. As shown in fig. 1B and 1C, a size L1 of the light-controlling pixel unit 523 in the first direction D1 is equal to twice a size of the display pixel unit 530 in the first direction D1, and a size L2 of the light-controlling pixel unit 523 in the second direction D2 is equal to four times a size of the display pixel unit 530 in the second direction D2.

The utility model discloses a designer notices in studying, walks the line through making grid line 510 realize being the broken line, can restrain the inhomogeneous problem of luminance of liquid crystal display device 500, for example, this inhomogeneous problem of luminance is that black and white line is bad or horizontal line is bad (for example, black and white line is bad under the angle of looking aside) the problem. The specific analysis is as follows. In the case where the gate lines 510 are implemented as straight lines, if an alignment error occurs when the light control panel 502 and the display panel 501 are attached, an orthographic projection of the gate lines 510 (straight lines) on the display panel 501 overlaps with one row of display pixels of the display panel 501, the gate lines 510 shield light rays from the backlight unit 503, and brightness of a region of the liquid crystal display device 500 corresponding to the gate lines 510 is close to zero (i.e., corresponding to black stripes), and a region of the liquid crystal display device 500 other than the region corresponding to the gate lines 510 corresponds to white stripes; in this case, the liquid crystal display device 500 has black stripes and white stripes alternately arranged in the second direction D2, that is, there may be a problem of poor black and white stripes in the liquid crystal display device 500. In the case where the gate lines 510 are implemented as a meander line, the black-and-white stripe defect or the horizontal stripe defect of the liquid crystal display device 500 can be suppressed.

The utility model designer of the present disclosure also notices in the research that the liquid crystal display device 500 shown in fig. 1A and 1B may have at least one of the problem of color unevenness (rainbow stripes) and the problem of signal delay.

For example, the liquid crystal display device 500 shown in fig. 1A and 1B may have a rainbow streak problem; the rainbow texture problem is a problem of uneven color mixing in different areas of the display device. Specifically, when a predetermined display screen of the display device is a white screen, the user observes that the actual screen has color stripes. The rainbow texture problem is related to the difference in shading of the gate lines 510 to the display sub-pixel units of different colors at different viewing angles. The rainbow texture problem is exemplarily described below with reference to fig. 2A and 2B. Fig. 2A is a schematic diagram illustrating a case where the gate lines 510 of the liquid crystal display device 500 illustrated in fig. 1A are shielded at a first viewing angle (e.g., a front viewing angle), and fig. 2B is a schematic diagram illustrating a case where the gate lines 510 of the liquid crystal display device 500 illustrated in fig. 1A are shielded at a second viewing angle (e.g., a side viewing angle). For convenience of explanation, it is assumed here that: the sizes of the first, second, and third display

sub-pixel units

531, 532, and 533 in the first direction D1 are the same as each other; the first line segment 511 and the second line segment 512 are both straight line segments. As shown in fig. 2A and 2B, since the sizes of the first, second, and third display

sub-pixel units

531, 532, and 533 in the first direction D1 are the same as each other, the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the first display sub-pixel unit 531, the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the second display sub-pixel unit 532, and the length of the portion of the line segment (e.g., the first line segment 511) corresponding to the third display sub-pixel unit 533 are the same as each other. As shown in fig. 2A, in the first viewing angle, since a portion of the line segment (e.g., the first line segment 511) corresponding to the second display sub-pixel unit 532 also overlaps the first signal line 541, an overlapping area of the line segment (e.g., the first line segment 511) and the first display sub-pixel unit 531 and an overlapping area of the line segment (e.g., the first line segment 511) and the third display sub-pixel unit 533 are smaller than an overlapping area of the line segment (e.g., the first line segment 511) and the second display sub-pixel unit 532 in the first viewing angle; in this case, the display frame at the first viewing angle is biased to the color of the second display sub-pixel unit 532. For a similar reason, as shown in fig. 2B, the display screen at the second viewing angle is biased to the color of the first display sub-pixel unit 532 (i.e., the display sub-pixel unit where the line segment overlaps with the first signal line 541). Since the user views the liquid crystal display device 500 in a certain viewing angle range, the actual screen viewed by the user has color stripes. It should be noted that the portion of the line segment corresponding to the display sub-pixel unit refers to a portion of the line segment between two intersections of the line segment and a boundary of the display sub-pixel unit (for example, a column of the display sub-pixel unit in which the display sub-pixel unit is located) in the first direction.

For another example, the liquid crystal display device 500 shown in fig. 1A and 1B may have a signal delay problem because the first line segment 511 (or/and the second line segment 512) has a large angle (acute angle) with the first direction D1, and thus the length of the first line segment 511 (or/and the second line segment 512) is long, and thus, the time required for a signal to be transmitted from one end of the gate line 510 to the other end of the gate line 510 is long.

The embodiment of the disclosure provides an array substrate, a manufacturing method of the array substrate, a light control panel and a display device. The array substrate comprises a plurality of grid lines extending along a first direction, a plurality of data lines extending along a second direction intersecting with the first direction and a plurality of light control pixel units. Each grid line comprises a plurality of grid parts which are arranged in parallel along a first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines. The array substrate can improve the display effect of a display device comprising the array substrate. For example, the array substrate can suppress the problem of unevenness (e.g., luminance unevenness and color unevenness) of a display screen of a display device including the array substrate.

In the following, a non-limiting description of an array substrate provided according to an embodiment of the present disclosure is provided by several examples and embodiments, and as described below, different features of the specific examples and embodiments may be combined with each other without conflicting with each other, so as to obtain new examples and embodiments, which also belong to the protection scope of the present disclosure.

Fig. 3 is a schematic plan view of an array substrate 100 provided in at least one embodiment of the present disclosure. Such as

As shown in fig. 3, the array substrate 100 includes a plurality of gate lines 101 respectively extending in a first direction D1 and a plurality of data lines 102 respectively extending in a second direction D2 intersecting the first direction D1. For example, the first direction D1 is perpendicular to the second direction D2.

As shown in fig. 3, a plurality of gate lines 101 and a plurality of data lines 102 intersect to define a plurality of light-controlling pixel units 103, each gate line 101 includes a plurality of grid portions 110 arranged in parallel and sequentially connected along a first direction D1, and each grid portion 110 includes grid lines 111 and an opening region 112 surrounded by the grid lines 111. For example, the plurality of gate lines 101 are configured to supply a scan signal, and the plurality of data lines 102 are configured to supply a data signal.

For example, as shown in fig. 3, the data line 102 may be a straight line parallel to the first direction D1, but the embodiments of the present disclosure are not limited thereto, and the data line 102 may also be implemented as a meander line, that is, the data line 102 has a meander structure, according to the requirement of practical application.

For example, by making each gate line 101 include a plurality of grid parts 110 arranged in parallel and in series along the first direction D1, the display effect of the display device 01 including the array substrate 100 may be improved. For example, by making each gate line 101 include a plurality of grid parts 110 arranged in parallel and in series along the first direction D1, the size of the grid of the light control panel 10 (see fig. 7) including the array substrate 100 (compared to the size of the grid of the light control panel 10 shown in fig. 1B) can be reduced, in which case, the difference between the size of the grid of the light control panel 10 of the array substrate 100 and the size of the grid of the display panel of the display device 01 including the array substrate 100 can be reduced, thereby the moire of the display device 01 including the array substrate 100 can be suppressed, and the display effect of the display device 01 (see fig. 8) including the array substrate 100 can be improved. For example, the grid of the light control panel 10 of the array substrate 100 shown in fig. 3 refers to a grid formed by the adjacent grid part 110 and the data line 102 and a grid corresponding to the grid part 110.

Fig. 4 shows a schematic plan view of the gate line 101 of the array substrate 100 shown in fig. 3. As shown in fig. 3 and 4, the grid lines 111 of each grid portion 110 include a first fold line trace 120 and a second fold line trace 130; the starting point of the first folding wire 120 is connected with the starting point of the second folding wire 130; the end point of the first folding wire 120 is connected with the end point of the second folding wire 130; the vertex of the first folded trace 120 and the vertex of the second folded trace 130 are spaced apart in the second direction D2.

As shown in fig. 3 and 4, the first folded trace 120 includes a first line segment 121 and a second line segment 122 connected in sequence, and a connection point of the first line segment 121 and the second line segment 122 is a vertex of the first folded trace 120 (in the same grid portion 110); the second folded wire trace 130 includes a third wire segment 131 and a fourth wire segment 134 connected in sequence, and a connection point of the third wire segment 131 and the fourth wire segment 134 is a vertex (in the same grid portion 110) of the second folded wire trace 130.

It should be noted that the extension of the gate lines 101 along the first direction D1 only defines the extending direction of the gate lines 101, and does not mean that the gate lines 101 include traces (the first folding trace 120 and the second folding trace 130) parallel to the first direction D1.

For example, as shown in fig. 3 and 4, the absolute value of the acute angle of the first line segment 121 with the first direction D1, the absolute value of the acute angle of the second line segment 122 with the first direction D1, the absolute value of the acute angle of the third line segment 131 with the first direction D1, and the absolute value of the acute angle of the fourth line segment 134 with the first direction D1 are between 38-55 degrees (e.g., 38-50 degrees).

For example, by reducing the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1, the difference in the shielding of the gate lines 101 of the array substrate 100 by the different color sub-pixels in the display panel 20 of the display device 01 including the array substrate 100 can be reduced, and thus the rainbow fringes (e.g., the rainbow fringes of a solid color picture) can be suppressed.

For example, by decreasing the absolute value of the acute angle of the first line segment 121 with respect to the first direction D1, the absolute value of the acute angle of the second line segment 122 with respect to the first direction D1, the absolute value of the acute angle of the third line segment 131 with respect to the first direction D1, and the absolute value of the acute angle of the fourth line segment 134 with respect to the first direction D1, the lengths of the first line segment 121, the second line segment 122, the third line segment 131, and the fourth line segment 134 may also be decreased, whereby the time required for a signal to be transferred from one end (e.g., left end) of the gate line 101 to the other end (e.g., right end) of the gate line 101 may be decreased, and thus the signal delay may be decreased.

For example, as shown in fig. 3 and 4, the absolute value of the acute angle of the first line segment 121 with the first direction D1, the absolute value of the acute angle of the second line segment 122 with the first direction D1, the absolute value of the acute angle of the third line segment 131 with the first direction D1, and the absolute value of the acute angle of the fourth line segment 134 with the first direction D1 are between 42 degrees and 48 degrees (e.g., 43 degrees and 44 degrees).

For example, by making the absolute value of the acute angle between the first line segment 121 and the first direction D1 α 1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 be 42 degrees to 48 degrees (e.g., 43 degrees to 44 degrees), it is possible to suppress rainbow stripes and reduce signal delay without deteriorating (e.g., not significantly deteriorating) the black-and-white stripe problem.

For example, by making each gate line 101 include a plurality of grid portions 110 arranged in parallel and connected in sequence along the first direction D1, it is possible to ensure that each row of display pixel cells 204 in the display panel 20 of the display device 01 including the array substrate 100 is partially shielded by the gate lines 101 while reducing the absolute value of the acute angle between the first line segment 121 and the first direction D1, the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1, and thus it is possible to avoid the degradation of the black-and-white stripe problem.

For example, by making each gate line 101 include a plurality of grid parts 110 arranged in parallel and sequentially connected along the first direction D1, it is also possible to avoid doubling the number of light-controlling pixel cells 103 of the light-controlling panel 10 while reducing the absolute value of the acute included angle of the first line segment 121-the fourth line segment 134 with respect to the first direction D1, and thus it is possible to avoid an increase in the load (e.g., capacitive load) of the light-controlling panel 10.

For example, as shown in fig. 3 and 4, the first folding line 120 and the second folding line 130 are symmetrical with respect to a connection line between a starting point of the first folding line 120 and an end point of the first folding line 120; in this case, the display effect of the display device 01 including the array substrate 100 may be improved.

For example, as shown in fig. 3 and 4, the first line segment 121 and the second line segment 122 are symmetrical with respect to a connection line between the vertex of the first folded wire trace 120 and the vertex of the second folded wire trace 130; the third line segment 131 and the fourth line segment 134 are symmetrical with respect to a connection line between the vertex of the first folded wire trace 120 and the vertex of the second folded wire trace 130; in this case, the display effect of the display device 01 including the array substrate 100 may be further improved.

For example, as shown in fig. 3 and 4, the boundary trace of the light-controlling pixel unit 103 is formed by the corresponding data line 102 and the first folding line trace 120 of the grid portion 110 corresponding to the gate line 101; the second folded wire trace 130 of the grid part 110 of each gate line 101 passes through the inside of the corresponding light-controlling pixel unit 103. As shown in fig. 3, two adjacent data lines 102 intersect with the first folding line 120 of two adjacent gate lines, and a portion of the two adjacent data lines 102 between the first folding lines 120 of the two adjacent gate lines and a portion of the first folding line 120 of the two adjacent gate lines between the two adjacent data lines 102 form a boundary line of the light-controlling pixel unit 103.

For example, each light-controlling pixel cell 103 further includes a switching element 141 and a pixel electrode 142; fig. 5 illustrates a schematic plan view of the switching element 141 and the pixel electrode 142 of the array substrate 100 illustrated in fig. 3. As shown in fig. 5, the switching element 141 includes a gate, a source and a drain, the gate of the switching element 141 is electrically connected to the corresponding second routing line 130 (i.e., passes through the second routing line 130 of the light-controlling pixel unit 103 including the switching element 141), one of the source and the drain of the switching element 141 is electrically connected to the pixel electrode 142 (e.g., electrically connected through a via), and the other of the source and the drain of the switching element 141 is electrically connected to the data line 102. For example, the number of the switching elements 141 is equal to the number of the second fold lines 130 (i.e., the number of the grid parts 110). For example, as shown in fig. 5, the gate of the switching element 141 is electrically connected to the second folded wire trace 130 at a position close to the vertex of the second folded wire trace 130. For example, the gate line 101 and the data line 102 may be formed using, for example, a metal material (e.g., copper, aluminum, or an aluminum alloy), and the pixel electrode 142 may be formed using, for example, a transparent conductive material. For example, the transparent conductive material is Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

For example, the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same shape. For example, the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same shape, which means that the design shapes of the pixel electrode 142 and the light-controlling pixel unit 103 are the same, and in an actual product, the shapes of the pixel electrode 142 and the light-controlling pixel unit 103 are allowed to have a certain deviation (e.g., less than 5% or 10%).

For example, the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same size. For example, the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same size, which means that the ratio of the difference between the size of the pixel electrode 142 and the size of the light-controlling pixel unit 103 to the average of the size of the pixel electrode 142 and the size of the light-controlling pixel unit 103 is less than 10% (e.g., less than 5%).

For example, as shown in fig. 3 and 4, each data line 102 has two overlapping positions with respect to a grid line of a corresponding grid part 110 (i.e., the grid part 110 overlapping with the orthographic projection of each data line 102 on the gate line) in a direction perpendicular to the array substrate 100. For example, the overlapping positions correspond to the vertex of the first folded trace 120 and the vertex of the second folded trace 130, respectively. For example, as shown in fig. 3 and 4, the array substrate 100 further includes a common electrode line 104 extending along the second direction D2, and the connection point of the common electrode line 104 and the two adjacent grid parts 110 overlaps in a direction perpendicular to the array substrate 100. For example, as shown in fig. 3 and 4, the opening area 112 surrounded by each mesh part 110 and the two light-controlling pixel units 103 partially overlap in a direction perpendicular to the array substrate 100. For example, as shown in fig. 3, a plurality of common electrode lines 104 and a plurality of data lines 102 are alternately arranged in the first direction D1. It should be noted that each data line 102 and the grid line of one corresponding grid part 110 have two overlapping positions in the direction perpendicular to the array substrate 100, which means that each data line 102 and two positions on the grid line of one corresponding grid part 110 overlap in the direction perpendicular to the array substrate 100, or the orthographic projection of each data line 102 on the gate line and the grid line of one corresponding grid part 110 have two overlapping positions.

For example, the widths of the first folded wire trace 120 and the second folded wire trace 130 are both between 9 microns and 11 microns (e.g., 10 microns). For example, the gate line 101 shown in fig. 1B has a width of about 20 μm. For example, by making the first folding line trace 120 and the second folding line trace 130 shown in fig. 3 about half the width of the gate line 510 shown in fig. 1B, the aperture ratio of the display device 01 including the array substrate 100 may not be reduced.

Fig. 6A is a schematic plan view illustrating another array substrate 100 provided in at least one embodiment of the present disclosure, where the array substrate 100 shown in fig. 6A is similar to the array substrate 100 shown in fig. 3; only the differences between them are described here, and the descriptions of the same parts are omitted.

The boundary trace of the light-controlling pixel unit 103 of the array substrate 100 shown in fig. 6A is formed by the corresponding common electrode line 104 and the first folding line 120 of the grid portion 110 corresponding to the gate line 101; the second folded wire trace 130 of the grid part 110 of each gate line 101 passes through the inside of the corresponding light-controlling pixel unit 103. An opening region 112 surrounded by each mesh portion 110 of the array substrate 100 shown in fig. 6A and one light-controlling pixel unit 103 are partially overlapped in a direction perpendicular to the array substrate 100.

As shown in fig. 6A, two adjacent common electrode lines 104 intersect with the first folding lines 120 of two adjacent gate lines, and a portion of the two adjacent common electrode lines 104 between the first folding lines 120 of the two adjacent gate lines and a portion of the first folding lines 120 of the two adjacent gate lines between the two adjacent common electrode lines 104 form a boundary line of the light-controlling pixel unit 103.

It should be noted that the first line segment 121, the second line segment 122, the third line segment 131 and the fourth line segment 134 are not limited to be implemented as straight line segments shown in fig. 3 (correspondingly, the grid part 110 of the gate line 101 is not limited to be diamond-shaped), but may also be implemented as curved line segments. Fig. 6B illustrates a schematic plan view of another gate line 101 of the array substrate 100 according to at least one embodiment of the present disclosure. As shown in fig. 6B, the first line segment 121, the second line segment 122, the third line segment 131, and the fourth line segment 134 are all implemented as curved line segments.

In some examples, the connection point of each data line 102 and two adjacent grid parts 110 is overlapped in a direction perpendicular to the array substrate 100, and the common electrode line 104 and the grid line of one corresponding grid part 110 (i.e., the grid part 110 overlapped with the orthographic projection of the common electrode line 104 on the gate line) have two overlapping positions in the direction perpendicular to the array substrate 100. It should be noted that the two overlapping positions of the grid lines of the common electrode line 104 and the corresponding grid part 110 in the direction perpendicular to the array substrate 100 means that the two overlapping positions of the grid lines of the common electrode line 104 and the corresponding grid part 110 in the direction perpendicular to the array substrate 100 overlap, or the orthographic projection of the common electrode line 104 on the gate line and the grid line of the corresponding grid part 110 have two overlapping positions.

At least one embodiment of the present disclosure also provides a light management panel 10. FIG. 7 is a schematic cross-sectional view of a light management panel 10 provided by at least one embodiment of the present disclosure. As shown in fig. 7, the light control panel 10 includes an opposite substrate 201, a liquid crystal layer 202, and any one of the array substrates 100 provided by at least one embodiment of the present disclosure; the array substrate 100 and the opposite substrate 201 are disposed opposite to each other, and the liquid crystal layer 202 is interposed between the array substrate 100 and the opposite substrate 201. For example, as shown in fig. 7, the opposite substrate 201, the liquid crystal layer 202, and the array substrate 100 are sequentially disposed in the third direction D3. For example, the third direction D3, the first direction D1, and the second direction D2 cross each other (e.g., are perpendicular to each other).

For example, the light control panel 10 may adjust the transmittance of the individual light control pixel units 103 of the light control panel 10 based on the data signals it receives, and the light control panel 10 may be used to provide adjusted backlight to the display panel 20. For example, light-controlling pixel cells 103 of a light-controlling panel are configured to control the intensity of light incident on the display sub-pixel cells corresponding to the light-controlling pixel cells 103.

At least one embodiment of the present disclosure also provides a display device 01. For example. The display device 01 may be implemented as a display device based on ADS (advanced super-dimensional field conversion technology) or a display device based on IPS-ADS (i.e., i-ADS, in-plane conversion-advanced super-dimensional field conversion technology) technology.

Fig. 8 is a schematic cross-sectional view of a display device 01 provided in at least one embodiment of the present disclosure. Such as

As shown in fig. 8, the display device 01 includes a display panel 20, a backlight unit 30, and any one of the light control panels 10 provided in at least one embodiment of the present disclosure. The display panel 20 is located at the light emitting side of the light control panel 10, and the backlight unit 30 is located at the side of the light control panel 10 away from the display panel 20. For example, as shown in fig. 8, the display panel 20, the light control panel 10, and the backlight unit 30 are sequentially disposed in the third direction D3. For example, the array substrate 100 of the light control panel 10 is closer to the backlight unit 30 than the opposite substrate 201 of the light control panel 10. For example, the resolution of the display panel 20 is twice that of the light control panel 10.

Fig. 9A is a schematic plan view of the display panel 20 of the display device 01 shown in fig. 8. As shown in fig. 9A, the display panel 20 includes a plurality of first signal lines 205 extending in a first direction D1 and a plurality of second signal lines 206 extending in a second direction D2; the intersection of the plurality of first signal lines 205 and the plurality of second signal lines 206 defines a plurality of display pixel cells 204. For example, the first signal lines 205 are gate lines of the display panel 20, and the second signal lines 206 are data lines of the display panel 20.

As shown in fig. 9A, each display pixel unit 204 includes a first display sub-pixel unit 2041, a second display sub-pixel unit 2042, and a third display sub-pixel unit 2043; the first display sub-pixel unit 2041, the second display sub-pixel unit 2042 and the third display sub-pixel unit 2043 are, for example, a red display sub-pixel unit, a green display sub-pixel unit and a blue display sub-pixel unit, respectively.

Fig. 9B is a schematic plan view of the display device 01 shown in fig. 8. For example, as shown in fig. 9B, the size of each display pixel cell 204 in the first direction D1 is equal to the size of each display pixel cell 204 in the second direction D2. As shown in fig. 9B, the size of each display sub-pixel cell in the first direction D1 is equal to one third of the size of each display pixel cell 204 in the first direction D1. For example, the width of the first signal line 205 (the width of the first signal line 205 in the second direction) is greater than the width of the first folded wire trace 120 (and the width of the second folded wire trace 130). For example, the width of the first signal line 205 (the width of the first signal line 205 in the second direction) is greater than twice the width of the first folded wire trace 120 (and the width of the second folded wire trace 130).

Fig. 10 is a schematic plan view of the mesh part 110 of the display device 01 shown in fig. 9B. As shown in fig. 9B and 10, the mesh part 110 has a dimension W1 in the first direction D1, and the mesh part 110 has a dimension W2 in the second direction D2. As shown in fig. 9B, a size W1 of the grid part 110 in the first direction D1 is equal to twice a size of the display pixel unit 204 in the first direction D1; the dimension W2 of the grid section 110 in the second direction D2 is less than (slightly less than) twice the dimension of the display pixel cell 204 in the second direction D2 and greater than the dimension of the display pixel cell 204 in the second direction D2. In some examples, the dimension W2 of the grid portion 110 in the second direction D2 may also be equal to twice the dimension of the display pixel unit 204 in the second direction D2, in which case the vertex of the first folding line 120 and the vertex of the second folding line 130 intersect the second direction D2.

Fig. 11 is a schematic plan view of a pixel unit of the display device 01 shown in fig. 9B. As shown in fig. 9B and 11, the size of the light-controlling pixel cell 103 in the first direction D1 is P1, and the size of the light-controlling pixel cell 103 in the second direction D2 is P2. As shown in fig. 1B and 1C, a size P1 of the light-controlling pixel cell 103 in the first direction D1 is equal to twice a size of the display pixel cell 204 in the first direction D1; the size (2) of the light-controlling pixel cell 103 in the second direction D2 is equal to 2.5-3 times the size of the display pixel cell 204 in the first direction D1.

It should be noted that the size of the pixel unit in the second direction D2 is equal to the distance between two parallel lines parallel to the first direction D1 connected to the vertices of the pixel unit on two sides of the second direction D2 in the second direction D2; for example, the size of the pixel cell in the second direction D2 is equal to the pitch in the second direction D2 of parallel lines connected to the vertex of the pixel cell on the upper side of the second direction D2 and parallel to the first direction D1 and parallel lines connected to the vertex of the pixel cell on the lower side of the second direction D2 and parallel to the first direction D1.

For example, the display device 01 further includes an isotropic diffusion film (not shown) disposed between the display panel 20 and the light control panel 10. The isotropic diffusion film may diffuse light emitted from the light control panel 10 within a small angle range, thereby blurring the pattern of the data lines 102 to further eliminate moire, while not significantly affecting the direction of the light emitted from the light control panel 10.

For example, the display device 01 may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. It should be noted that, for other components of the display device (for example, the control device, the image data encoding/decoding device, the row scan driver, the column scan driver, the clock circuit, etc.), suitable components can be adopted, which are understood by those skilled in the art, and are not described herein again, nor should be taken as a limitation to the present disclosure. The display device can achieve the effect of improving display.

For example, at least one embodiment of the present disclosure also provides a method of manufacturing an array substrate. The manufacturing method of the array substrate comprises the following steps: a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersecting the first direction, and a plurality of light-controlling pixel units are formed.

For example, each grid line comprises a plurality of grid parts which are arranged in parallel along the first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines. For example, the specific structure of the array substrate may refer to the array substrate provided in at least one embodiment of the present disclosure, and is not described herein again. For example, a display device including the array substrate manufactured by the manufacturing method may improve display effects.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims

1. An array substrate comprises a plurality of grid lines extending along a first direction respectively, a plurality of data lines extending along a second direction intersecting the first direction respectively, and a plurality of light-control pixel units,

each grid line comprises a plurality of grid parts which are arranged in parallel along the first direction and are sequentially connected, and each grid part comprises grid lines and an opening area defined by the grid lines.

2. The array substrate of claim 1, wherein the grid lines of each grid portion comprise first fold line traces and second fold line traces;

the starting point of the first fold line is connected with the starting point of the second fold line;

the terminal point of the first fold line is connected with the terminal point of the second fold line; and

the vertex of the first fold line and the vertex of the second fold line are arranged at intervals in the second direction.

3. The array substrate according to claim 2, wherein the first folding line comprises a first line segment and a second line segment connected in sequence, and a connection point of the first line segment and the second line segment is a vertex of the first folding line;

the second fold line routing comprises a third line segment and a fourth line segment which are sequentially connected, and the connection point of the third line segment and the fourth line segment is the vertex of the second fold line routing; and

the first line segment with the absolute value of the acute angle contained angle of first direction, the second line segment with the absolute value of the acute angle contained angle of first direction, the third line segment with the absolute value of the acute angle contained angle of first direction and the fourth line segment with the absolute value of the acute angle contained angle of first direction is located between 38 degrees-55 degrees.

4. The array substrate of claim 3, wherein the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

5. The array substrate of claim 3, wherein the first folding trace and the second folding trace are symmetrical with respect to a line connecting a starting point of the first folding trace and an end point of the first folding trace.

6. The array substrate of claim 5, wherein the first line segment and the second line segment are symmetrical with respect to a line connecting a vertex of the first folded wire trace and a vertex of the second folded wire trace; and

the third line segment and the fourth line segment are symmetrical relative to a connecting line of a vertex of the first folded wire and a vertex of the second folded wire.

7. The array substrate of any one of claims 1-6, wherein each data line has two overlapping positions with the grid line of a corresponding grid portion in a direction perpendicular to the array substrate, or overlaps with the connection point of two adjacent grid portions in a direction perpendicular to the array substrate.

8. The array substrate of claim 7, further comprising common electrode lines extending along the second direction,

the connection point of the common electrode line and two adjacent grid parts is overlapped in the direction perpendicular to the array substrate, or the grid line of one corresponding grid part has two overlapped positions in the direction perpendicular to the array substrate.

9. The array substrate of any one of claims 1-6, wherein the open area surrounded by each of the grid portions and one or two of the light-controlling pixel units partially overlap in a direction perpendicular to the array substrate.

10. The array substrate according to any one of claims 2 to 6, wherein the border trace of each light-controlling pixel unit is formed by the corresponding data line and the first folding line trace of the grid portion corresponding to the gate line; and

and a second fold line routing of the grid part of each grid line passes through the inside of the corresponding light control pixel unit.

11. The array substrate of any one of claims 2-6, further comprising common electrode lines extending along the second direction,

wherein the connection points of the common electrode lines and the two adjacent grid parts are overlapped in the direction vertical to the array substrate;

the boundary routing of each light control pixel unit is formed by the corresponding common electrode wire and the first fold line routing of the grid part corresponding to the grid line; and

12. The array substrate of any one of claims 2-6, wherein each of the light-controlling pixel units further comprises a switching element and a pixel electrode;

the switching element includes a gate, a source and a drain,

the grid electrode of the switch element is electrically connected with the corresponding second fold line routing, and one of the source electrode and the drain electrode of the switch element is electrically connected with the pixel electrode; and

the number of the switch elements is equal to the number of the second fold lines.

13. The array substrate of any one of claims 2 to 6, wherein the first folded trace and the second folded trace each have a width between 9 microns and 11 microns.

14. The array substrate of claim 1, wherein the grid lines of each grid portion comprise first fold line traces and second fold line traces;

the starting point of the first folding line is connected with the starting point of the second folding line, and the end point of the first folding line is connected with the end point of the second folding line;

the vertex of the first fold line and the vertex of the second fold line are arranged at intervals in the second direction;

the first fold line comprises a first line segment and a second line segment which are sequentially connected, and the connection point of the first line segment and the second line segment is the vertex of the first fold line;

the second fold line routing comprises a third line segment and a fourth line segment which are sequentially connected, and the connection point of the third line segment and the fourth line segment is the vertex of the second fold line routing;

the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 and 48 degrees;

the first folding line and the second folding line are symmetrical relative to a connection line of a starting point of the first folding line and an end point of the first folding line;

the first line segment and the second line segment are symmetrical relative to a connecting line of a vertex of the first fold line and a vertex of the second fold line;

the third line segment and the fourth line segment are symmetrical relative to a connecting line of a vertex of the first folded wire and a vertex of the second folded wire;

each data line and the grid line of one corresponding grid part have two overlapping positions in the direction perpendicular to the array substrate;

the array substrate further comprises a common electrode line extending along the second direction, and the connection positions of the common electrode line and two adjacent grid parts are overlapped in the direction perpendicular to the array substrate;

the opening area surrounded by each grid part and the two light control pixel units are partially overlapped in the direction perpendicular to the array substrate;

the boundary routing of the light control pixel unit is formed by the corresponding data line and the first fold routing of the grid part corresponding to the grid line, and the second fold routing of the grid part of each grid line passes through the inside of the corresponding light control pixel unit;

each light-control pixel unit further comprises a switching element and a pixel electrode; the switching element comprises a grid electrode, a source electrode and a drain electrode, the grid electrode of the switching element is electrically connected with the corresponding second fold line routing, one of the source electrode and the drain electrode of the switching element is electrically connected with the pixel electrode, and the number of the switching elements is equal to that of the second fold line routing.

15. A light control panel comprising the array substrate of any one of claims 1 to 14, a counter substrate and a liquid crystal layer,

the array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.

16. A display device, comprising:

a display panel;

the light management panel of claim 15; and

a backlight unit for displaying a backlight unit having a plurality of light emitting elements,

the display panel is located on the light emitting side of the light control panel, and the backlight unit is located on one side of the light control panel, which is far away from the display panel.

17. The display device according to claim 16, wherein the display panel includes a plurality of display pixel units arranged in an array;

the size of each grid part in the first direction is equal to twice the size of each display pixel unit in the first direction; and

the size of each grid part in the second direction is smaller than or equal to twice the size of each display pixel unit in the second direction.

18. The display device according to claim 17, wherein the size of each of the light-controlling pixel cells in the first direction is equal to twice the size of each of the display pixel cells in the first direction; and

the size of each light control pixel unit in the second direction is equal to 2.5-3 times the size of each display pixel unit in the first direction.