CN117784483A

CN117784483A - Display panel, manufacturing method thereof and display device

Info

Publication number: CN117784483A
Application number: CN202311824218.4A
Authority: CN
Inventors: 朴哲; 王晨鹏; 翁徐阳; 康佳琪; 陈泓
Original assignee: Xiamen Tianma Optoelectronics Co ltd
Current assignee: Xiamen Tianma Optoelectronics Co ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-29

Abstract

The invention discloses a display panel and a manufacturing method thereof, and a display device, wherein the display panel comprises an array substrate, and the array substrate comprises a first substrate, a second metal layer and a common electrode; the second metal layer comprises data lines which are arranged along the first direction and extend in the second direction, and the data lines at least partially overlap with orthographic projection of the common electrode on the plane of the first substrate; at least the display area also comprises a first wire, the first wire is positioned at one side of the common electrode, and the first wire is in direct contact connection with the common electrode; the first wire comprises a first sub-wire extending along a second direction; alternatively, the first trace includes a second sub-trace extending along the first direction; alternatively, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, the second sub-trace being connected to the first sub-trace. The invention can reduce the resistance of the public electrode, reduce the voltage recovery time of the public electrode and avoid the occurrence of transverse bright lines.

Description

Display panel, manufacturing method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a manufacturing method thereof and a display device.

Background

Currently, display technology permeates all aspects of people's daily lives, and accordingly, more and more materials and technologies are used for display screens. The display panel is used as an important component of the display device to realize the display function of the display device. Nowadays, the main display screen mainly includes a liquid crystal display panel and an Organic Light-Emitting Diode (OLED). The liquid crystal display panel has the advantages of light weight, low power consumption, low radiation and the like, and is widely applied to various fields.

The liquid crystal display panel generally comprises a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are oppositely arranged, the liquid crystal layer is arranged between the color film substrate and the array substrate, a black matrix and a color resistance layer are arranged on one side, close to the array substrate, of the color film substrate, an electric field between a pixel electrode and a common electrode in the display panel can enable liquid crystal molecules to deflect, light rays generated by a backlight assembly after the liquid crystal molecules deflect can penetrate through the display panel, the liquid crystal molecules can deflect to different degrees by adjusting the size of the electric field, and when the liquid crystal molecules deflect to different degrees, the light transmittance of the display panel is different, and the light quantity of the backlight assembly penetrating through the liquid crystal display panel is different, so that the display of images is realized. However, in the prior art, bright lines (cross talk) are generated in the display process of the liquid crystal display panel, which affects the display performance.

Accordingly, there is a need for a display panel, a method of manufacturing the same, and a display device capable of improving bright lines and display performance.

Disclosure of Invention

In view of the above, the present invention provides a display panel, a manufacturing method thereof, and a display device for improving the voltage recovery capability of a common electrode, improving bright lines, and improving display performance.

In one aspect, the present invention provides a display panel, including a color film substrate and an array substrate disposed opposite to each other, where the array substrate includes:

a first substrate base plate;

the first metal layer is positioned on one side of the first substrate base plate, the second metal layer is positioned on one side of the first metal layer far away from the first substrate base plate, and a first insulating layer is arranged between the first metal layer and the second metal layer; the second metal layer comprises data lines, and the plurality of data lines are distributed along the first direction and extend along the second direction;

the common electrode is positioned at one side of the second metal layer far away from the first substrate, a second insulating layer is arranged between the second metal layer and the common electrode, and orthographic projection of the data line on the plane of the first substrate is overlapped with orthographic projection of the common electrode on the plane of the first substrate at least partially;

the display panel also comprises a display area and a non-display area at least partially surrounding the display area, at least the display area also comprises a first wiring, the first wiring is positioned on one side of the common electrode far away from the first substrate base plate, or the first wiring is positioned on one side of the common electrode near the first substrate base plate, and the first wiring is in direct contact connection with the common electrode;

The first wire comprises a first sub-wire extending along a second direction;

alternatively, the first trace includes a second sub-trace extending along the first direction;

alternatively, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, the second sub-trace being connected to the first sub-trace.

On the other hand, the invention also provides a manufacturing method of the display panel, which is used for manufacturing the display panel and comprises the following steps:

providing a color film substrate;

manufacturing an array substrate, comprising:

providing a first substrate base plate;

forming a first metal layer on one side of a first substrate base plate;

forming a first insulating layer on one side of the first metal layer away from the first substrate;

forming a second metal layer on one side of the first insulating layer far away from the first substrate base plate, and etching the second metal layer to form data lines which are distributed along a first direction and extend along a second direction;

forming a second insulating layer on one side of the second metal layer away from the first substrate;

forming a common electrode on one side of the second insulating layer far away from the first substrate, wherein the orthographic projection of the data line on the plane of the first substrate and the orthographic projection of the common electrode on the plane of the first substrate at least partially overlap;

Forming a third metal layer on one side of the common electrode far away from the first substrate base plate in at least a display area of the display panel, and etching the third metal layer to form a first wiring, so that the first wiring is in direct contact with the common electrode, wherein the first wiring comprises a first sub-wiring extending along a second direction; alternatively, the first trace includes a second sub-trace extending along the first direction; or the first wire comprises a first sub-wire extending in the second direction and a second sub-wire extending along the first direction, and the second sub-wire is connected with the first sub-wire;

or at least in a display area of the display panel, forming a third metal layer on one side of the second insulating layer away from the first substrate, and etching the third metal layer to form a first wire, wherein the first wire comprises a first sub-wire extending along the second direction; alternatively, the first trace includes a second sub-trace extending along the first direction; or, the first wire comprises a first sub-wire extending in the second direction and a second sub-wire extending along the first direction, and the second sub-wire is connected with the first sub-wire; and forming a common electrode on one side of the first wiring far away from the first substrate, wherein the orthographic projection of the data line on the plane of the first substrate is overlapped with the orthographic projection of the common electrode on the plane of the first substrate at least partially, and the first wiring is in direct contact with the common electrode.

On the other hand, the invention also provides a display device which comprises the display panel.

Compared with the prior art, the display panel, the manufacturing method thereof and the display device provided by the invention have the advantages that at least the following beneficial effects are realized:

according to the invention, the first wiring is arranged on one side of the public electrode far away from the first substrate, or the first wiring is positioned on one side of the public electrode close to the first substrate, and the first wiring is in direct contact connection with the public electrode, so that the first wiring and the public electrode are in parallel connection, the first wiring can adopt metal or other conductors with lower impedance, and the total resistance after parallel connection is smaller than two resistances after parallel connection according to the resistance principle, so that the total resistance after parallel connection of the public electrode and the first wiring is reduced, and when the data voltage changes, the public voltage can be quickly restored to the standard, and the horizontal crosstalk bright line is improved. In the invention, the first wiring is in direct contact with the public electrode, and one side insulating layer is not required to be arranged above the public electrode, and then the first wiring is manufactured and then connected through the via hole, so that the manufacturing process is complex, and the thickness of the display panel is increased. The first wiring is in direct contact with the common electrode, so that the process is simple, and the thickness of the display panel is reduced. The first wiring comprises a first sub-wiring extending along the second direction, the first sub-wiring is directly connected with the common electrode to form parallel connection, the total resistance of the first sub-wiring and the common electrode after being connected in parallel is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, so that the horizontal crosstalk bright line is improved. Or, the first wiring comprises a second sub-wiring extending along the first direction, the second sub-wiring is directly connected with the common electrode to form parallel connection, the total resistance of the second sub-wiring and the common electrode after parallel connection is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, so that the horizontal crosstalk bright line is improved. Or, the first wire comprises a first sub-wire extending along the second direction and a second sub-wire extending along the first direction, the second sub-wire is connected with the first sub-wire, the first sub-wire and the second sub-wire are connected with the common electrode directly, the total resistance after parallel connection can be further reduced, the total resistance is reduced, when the data voltage changes, the common voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is improved.

Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to the present invention;

FIG. 2 is a cross-sectional view taken along the direction A-A' in FIG. 1;

FIG. 3 is a schematic plan view of a display panel according to the present invention;

FIG. 4 is a cross-sectional view taken in the direction K-K' of FIG. 3;

FIG. 5 is a schematic plan view of another display panel according to the present invention;

FIG. 6 is a schematic plan view of another display panel according to the present invention;

FIG. 7 is a schematic plan view of another display panel according to the present invention;

FIG. 8 is a schematic plan view of another display panel according to the present invention;

FIG. 9 is a schematic plan view of another display panel according to the present invention;

FIG. 10 is a cross-sectional view taken in the direction B-B' of FIG. 7;

FIG. 11 is a schematic plan view of another display panel according to the present invention;

FIG. 12 is a cross-sectional view taken along the direction C-C' in FIG. 11;

FIG. 13 is a schematic plan view of another display panel according to the present invention;

FIG. 14 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 15 is a schematic plan view of another display panel according to the present invention;

FIG. 16 is a schematic plan view of another display panel according to the present invention;

FIG. 17 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 18 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 19 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 20 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 21 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 22 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 23 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 24 is a cross-sectional view taken along the direction D-D' in FIG. 23;

fig. 25 is a schematic plan view of a display panel according to still another embodiment of the present invention;

FIG. 26 is a cross-sectional view taken along the direction E-E' in FIG. 25;

FIG. 27 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 28 is a schematic plan view of a display panel according to another embodiment of the present invention;

fig. 29 is a schematic plan view of a display panel according to still another embodiment of the present invention;

FIG. 30 is a cross-sectional view taken in the direction F-F' of FIG. 29;

FIG. 31 is a flowchart of a method for fabricating a display panel according to the present invention;

fig. 32 is a schematic plan view of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Referring to fig. 1, 2, 3, 4, 5 and 6, fig. 1 is a schematic plan view of a display panel according to the present invention, fig. 2 is a cross-sectional view of A-A 'in fig. 1, fig. 3 is a schematic plan view of a display panel according to the present invention, fig. 4 is a cross-sectional view of K-K' in fig. 3, fig. 5 is a schematic plan view of another display panel according to the present invention, and fig. 6 is a schematic plan view of another display panel according to the present invention. The present embodiment provides a display panel 100, including a color film substrate 1 and an array substrate 2 that are disposed oppositely, the array substrate 2 includes: a first substrate base 201; a first metal layer 202 located on one side of the first substrate 201, a second metal layer 204 located on one side of the first metal layer 202 away from the first substrate 201, and a first insulating layer 203 between the first metal layer 202 and the second metal layer 204; the second metal layer 204 includes data lines 3, and the plurality of data lines 3 are arranged along a first direction X and extend along a second direction Y; the common electrode 206 is positioned on one side of the second metal layer 204 away from the first substrate 201, a second insulating layer 205 is arranged between the second metal layer 204 and the common electrode 206, and the orthographic projection of the data line 3 on the plane of the first substrate 201 and the orthographic projection of the common electrode 206 on the plane of the first substrate 201 at least partially overlap; the display panel 100 further includes a display area AA and a non-display area BB at least partially surrounding the display area AA, at least the display area AA further includes a first trace 4, where the first trace 4 is located on a side of the common electrode 206 away from the first substrate 201, or the first trace 4 is located on a side of the common electrode 206 near the first substrate 201, and the first trace 4 is in direct contact connection with the common electrode 206;

As shown in fig. 1, the first trace 4 includes a first sub-trace 41 extending in the second direction Y;

alternatively, as shown in fig. 5, the first trace 4 includes a second sub-trace 42 extending along the first direction X;

alternatively, as shown in fig. 6, the first trace 4 includes a first sub-trace 41 extending in the second direction Y and a second sub-trace 42 extending in the first direction X, the second sub-trace 42 being connected to the first sub-trace 41.

Specifically, referring to fig. 2, the liquid crystal molecules 6 are disposed between the color film substrate 1 and the array substrate 2, the array substrate 2 includes a first substrate 201, and a first metal layer 202, a first insulating layer 203, a second metal layer 204, and a common electrode 206 stacked on the first substrate 201, and of course, the array substrate 2 further includes a pixel electrode 207, and in a direction perpendicular to a plane of the first substrate 201, a third insulating layer 208 is further disposed between the pixel electrode 207 and the common electrode 206, and after voltages are applied to the pixel electrode 207 and the common electrode 206, respectively, deflection of the liquid crystal molecules 6 in a corresponding region can be controlled to display. In fig. 2, only the pixel electrode 207 is shown on the side of the common electrode 206 away from the first substrate 201, it is understood that the common electrode 206 is disposed as a whole, and when the pixel electrode 207 is connected to the drain electrode T3 of the transistor TFT, it is necessary to dig a hole of the common electrode 206 to remove a portion corresponding to the position of the via hole, as shown in fig. 2, so as to prevent crosstalk between the driving signal of the pixel electrode 207 and the signal of the common electrode 206. Of course, the pixel electrode 207 may also be located at a side of the common electrode 206 near the second metal layer 204, which is not shown here. In fig. 2, the common electrode 206, the first insulating layer 203, the second insulating layer 205, the third insulating layer 208, the first substrate 201, and the color film substrate 1 are not pattern-filled. Alternatively, the materials of the pixel electrode 207 and the common electrode 206 may be Indium Tin Oxide (ITO), but may be other materials, which are not particularly limited herein. In fig. 1, 5 and 6, only the pixel electrode 207 is illustrated as a dual domain structure, and it is understood that the viewing angle of the liquid crystal display panel has a weak point of anisotropy, because the liquid crystal molecules 6 are approximately cylindrical, have a long axis and a short axis, the deflection directions of the liquid crystal molecules 6 are different, and the optical path differences of the light rays passing through the liquid crystal display panel are different, so that the viewing angle of the liquid crystal display panel has a phenomenon of anisotropy. The pixel electrode 207 is configured as a dual domain structure, two portions of the pixel electrode 207 form two adjacent domains in the same sub-pixel P, the rotation directions of the liquid crystal molecules 6 of the two adjacent domains are opposite, and the viewing angles of the two adjacent domains can be complemented in different viewing angle directions, so that the viewing angle problem in the horizontal or vertical direction can be solved. The dual domain structure can increase the viewing angle of the liquid crystal display panel and improve the color cast problem of the display panel 100. Of course, the pixel electrode 207 may be single domain or pseudo-double domain, and is not particularly limited herein.

Of course, fig. 2 also shows a transistor T for driving the pixel electrode 207, where the transistor T includes a gate T1, a source T2, and a drain T3, the drain T3 is electrically connected to the pixel electrode 207 by a via, and the source T2 and the drain T3 are electrically connected to the semiconductor T4 by vias, and it is understood that, for the semiconductor T4, the gate T1, the source T2, and the drain T3 further include an interlayer insulating layer, the gate T1 is located on the first metal layer 202, the source T2 and the drain T3 are located on the second metal layer 204, and the first insulating layer 203 may specifically refer to an interlayer insulating layer between the semiconductor T4 and the second metal layer 204, and between the gate T1 and the semiconductor T4, where no pattern filling is performed on the interlayer insulating layer in fig. 2. Only the transistor T is shown in fig. 2 as a bottom gate structure.

The orthographic projection of the data line 3 on the plane of the first substrate 201 and the orthographic projection of the common electrode 206 on the plane of the first substrate 201 at least partially overlap, and fig. 1, 5 and 6 show the situation that the orthographic projection of the data line 3 on the plane of the first substrate 201 is located within the orthographic projection of the common electrode 206 on the plane of the first substrate 201, the data line 3 will generate a coupling capacitance with the common electrode 206, and when the data voltage transmitted on the data line 3 changes, the common voltage of the common electrode 206 will be disturbed, and in the related art, the common electrode 206 is usually made of Indium Tin Oxide (ITO), and the common electrode 206 has a larger resistance, so that the voltage of the common electrode 206 cannot be quickly restored to the alignment after the voltage of the common electrode 206 changes, and thus the horizontal Crosstalk bright line cross talk occurs.

The third metal layer 209 is provided for providing the first wiring 4, and the third metal layer 209 may be located on a side of the common electrode 206 close to the first substrate 201 or on a side of the common electrode 206 far from the first substrate 201. Fig. 1 and 2 show that the first trace 4 is disposed on a side, away from the first substrate 201, of the common electrode 206, and fig. 3 and 4 show that the first trace 4 is disposed on a side, close to the first substrate 201, of the common electrode 206, and the first trace 4 is in direct contact connection with the common electrode 206, so that the first trace 4 and the common electrode 206 are in parallel connection, the first trace 4 can adopt a metal or other conductor with lower impedance, and the total resistance after parallel connection is smaller than two resistances after parallel connection according to the resistance principle, so that the total resistance after parallel connection of the common electrode 206 and the first trace 4 is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is improved. It should be noted that, in the following embodiments of the present invention, only the side of the common electrode 206 away from the first substrate 201 is taken as an example for illustration, and in any of the following embodiments, the first wiring 4 may be located on the side of the common electrode 206 close to the first substrate 201, and will not be described herein.

In the present invention, the first trace 4 is directly contacted with the common electrode 206, and there is no need to provide an insulating layer on one side above the common electrode 206, and then make the first trace 4 and connect the first trace with the common electrode through a via hole, so that the manufacturing process is complex and the thickness of the display panel 100 is increased. The first trace 4 is in direct contact with the common electrode 206, which is simple in process and is also beneficial to reducing the thickness of the display panel 100.

As shown in fig. 1, the first trace 4 includes a first sub-trace 41 extending along the second direction Y, the first sub-trace 41 is directly connected with the common electrode 206 to form a parallel connection, the total resistance of the first sub-trace 41 and the common electrode 206 after being connected in parallel is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, so as to improve the horizontal crosstalk bright line.

As shown in fig. 5, the first trace 4 includes a second sub-trace 42 extending along the first direction X, the second sub-trace 42 is directly connected to the common electrode 206 to form a parallel connection, the total resistance of the second sub-trace 42 after being connected in parallel to the common electrode 206 is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, thereby improving the horizontal crosstalk bright line.

As shown in fig. 6, the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, the second sub-trace 42 is connected with the first sub-trace 41, the first sub-trace 41 and the second sub-trace 42 form a net shape, and are directly connected with the common electrode 206, so that the total resistance after parallel connection can be further reduced, the total resistance is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is improved. In addition, after the first sub-wiring 41 and the second sub-wiring 42 form a mesh structure, the common voltage uniformity is also improved.

It can be appreciated that, because the wiring space of the third metal layer 209 is larger, the first wires 4 can be disposed in the first direction X and/or the second direction Y, and the first sub-wires 41 or the second sub-wires 42 can be set according to the actual requirement of the product, which is more flexible in structure and wider in practicality.

In some alternative embodiments, referring to fig. 7, fig. 8, fig. 9, and fig. 10, fig. 7 is a schematic plan view of another display panel provided by the present invention, fig. 8 is a schematic plan view of another display panel provided by the present invention, fig. 9 is a schematic plan view of another display panel provided by the present invention, fig. 10 is a cross-sectional view of a direction B-B' in fig. 7, the color film substrate 1 includes a second substrate 101 and a black matrix BM located on one side of the second substrate 101, and an orthographic projection of the first trace 4 on a plane of the first substrate 201 is located in an orthographic projection of the black matrix BM on a plane of the first substrate 201.

Specifically, the color film substrate 1 includes a second substrate 101, a black matrix BM and a color resist 102 that are located on a side of the second substrate 101 near the array substrate 2, and in fig. 10, the color resist 102 is not filled with a pattern. The black matrix BM is used for shielding light leakage of the backlight source outside the pixel opening, and is an existing film layer in the color film substrate 1.

It can be understood that, since the material of the first wire 4 is metal, the metal material has a light shielding property, and the first wire 4 is covered by the projection of the black matrix BM, the first wire 4 does not occupy an open space, and the aperture ratio of the pixel is not affected; in addition, the metal material reflects light, and the first trace 4 is shielded by the black matrix BM, so that the metal reflection problem of the first trace 4 can be reduced as much as possible. In this embodiment, the orthographic projection of the first trace 4 on the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM on the plane of the first substrate 201, so that the aperture ratio of the pixel is not affected, and the metal reflection problem of the first trace 4 can be reduced as much as possible.

When the first wiring 4 includes the first sub-wiring 41 extending along the second direction Y, the orthographic projection of the first sub-wiring 41 on the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM on the plane of the first substrate 201, so as to reduce the influence on the pixel aperture ratio, and simultaneously reduce the metal reflection problem of the first sub-wiring 41 as much as possible; when the first sub-trace 41 includes the second sub-trace 42 extending along the first direction X, the orthographic projection of the second sub-trace 42 on the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM on the plane of the first substrate 201, so as to reduce the influence on the pixel aperture ratio, and simultaneously reduce the metal reflection problem of the second sub-trace 42 as much as possible; when the first trace 4 includes the first sub-trace 41 extending along the second direction Y and the second sub-trace 42 extending along the first direction X, the second sub-trace 42 is connected to the first sub-trace 41, and the first sub-trace 41 and the second sub-trace 42 form a net shape, the orthographic projection of the first sub-trace 41 and the second sub-trace 42 on the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM on the plane of the first substrate 201, so as to reduce the influence on the pixel aperture ratio, and simultaneously reduce the metal reflection problem of the first sub-trace 41 and the second sub-trace 42 as much as possible.

In some alternative embodiments, referring to fig. 11, 12, 13, 14, 15, 16, 18, 19 and 20, fig. 11 is a schematic plan view of another display panel provided by the present invention, fig. 12 is a cross-sectional view in the direction C-C' in fig. 11, fig. 13 is a schematic plan view of another display panel provided by the present invention, fig. 14 is a schematic plan view of another display panel provided by the present invention, fig. 15 is a schematic plan view of another display panel provided by the present invention, fig. 16 is a schematic plan view of another display panel provided by the present invention, fig. 17 is a schematic plan view of another display panel provided by the present invention, fig. 18 is a schematic plan view of another display panel provided by the present invention, fig. 19 is a schematic plan view of another display panel provided by the present invention, and fig. 20 is a schematic plan view of another display panel provided by the present invention.

The color film substrate 1 includes a second substrate 101; the display panel 100 further includes a support column 7, the support column 7 being located between the first substrate base 201 and the second substrate base 101;

the first trace 4 at least partially overlaps the support column 7 in a direction perpendicular to the plane of the first substrate 201; alternatively, at least part of the first trace 4 semi-surrounds the support column 7 in a direction perpendicular to the plane of the first substrate 201; alternatively, the first trace 4 includes a notch 8, and the notch 8 overlaps the support post 7 in a direction perpendicular to a plane of the first substrate 201.

The liquid crystal display panel is a liquid crystal box formed by oppositely arranging the array substrate 2 and the color film substrate 1 in a butt joint way, and when the array substrate 2 and the color film substrate 1 are in butt joint, a supporting column 7 with supporting function is needed to be adopted between the array substrate 2 and the color film substrate 1 so as to keep the box thickness of the liquid crystal box. The support column 7 includes a main support column 71 and an auxiliary support column 72, which together function to support the thickness of the liquid crystal cell, a certain height difference exists between the main support column 71 and the auxiliary support column 72, and the main support column 71 mainly plays a decisive role in supporting the thickness of the liquid crystal cell of the display panel 100, and the auxiliary support column 72 plays a role in improving elasticity when the liquid crystal display panel receives an external force.

The first trace 4 in fig. 11 includes a first sub-trace 41 extending in the second direction Y, the first trace 4 in fig. 13 includes a second sub-trace 42 extending in the first direction X, the first trace 4 in fig. 14 includes the first sub-trace 41 extending in the second direction Y and the second sub-trace 42 extending in the first direction X, and the first sub-trace 41 and the second sub-trace 42 are connected. Of course, the color film substrate 1 may include a black matrix BM within which the support columns 7 are also located in a direction perpendicular to the plane of the first substrate 201, which is not shown in fig. 12. In the direction perpendicular to the plane of the first substrate 201, the first trace 4 at least partially overlaps the support column 7, and the support column 7 may be in contact with the color film substrate 1 and the array substrate 2, respectively, as shown in fig. 12, although the third metal layer 209 is disposed in the array substrate 2 for making the first trace 4, the main support column 71 is in contact with the array substrate 2, and when the display panel 100 is pressed by an external force, the support column 7 may be prevented from being displaced.

The first trace 4 in fig. 15 includes a first sub-trace 41 extending in the second direction Y, the first trace 4 in fig. 16 includes a second sub-trace 42 extending in the first direction X, the first trace 4 in fig. 17 includes the first sub-trace 41 extending in the second direction Y and the second sub-trace 42 extending in the first direction X, and the first sub-trace 41 and the second sub-trace 42 are connected. In fig. 15 to 17, at least part of the first trace 4 semi-surrounds the support column 7 in a direction perpendicular to the plane of the first substrate 201, i.e. the first trace 4 is routed at the position of the support column 7, and at least part of the first trace 4 and the support column 7 do not overlap or overlap in a direction perpendicular to the plane of the first substrate 201. In this embodiment, in the direction perpendicular to the plane of the first substrate 201, at least a portion of the first trace 4 partly surrounds the support column 7, so that the position contacted by the end of the support column 7 near the array substrate has better flatness, which can improve the flatness of the position of the support column 7 and improve the extrusion light leakage performance.

The first trace 4 in fig. 18 includes a first sub-trace 41 extending in the second direction Y, the first trace 4 in fig. 19 includes a second sub-trace 42 extending in the first direction X, the first trace 4 in fig. 20 includes the first sub-trace 41 extending in the second direction Y and the second sub-trace 42 extending in the first direction X, and the first sub-trace 41 and the second sub-trace 42 are connected. In fig. 18 to 20, the first trace 4 includes a notch 8, and in a direction perpendicular to a plane of the first substrate 201, the notch 8 overlaps the support post 7, i.e. the first trace 4 is disconnected at a position of the support post 7, for example, a portion of the first sub-trace 41 in fig. 18 to 20 has the notch 8, i.e. is disconnected at a position of the support post 7. In this embodiment, in the direction perpendicular to the plane of the first substrate 201, the notch 8 overlaps the support column 7, so that the position contacted by the end of the support column 7 near the array substrate has better flatness, and the flattening performance of the position of the support column 7 can be improved, and the extrusion light leakage performance can be improved. Optionally, in order to keep the thickness of the liquid crystal cell, the main supporting post 71 needs to be in contact with the array substrate 2, which is more likely to affect planarization, and light leakage occurs when external force is applied, and the first sub-trace 41 and/or the second sub-trace 42 have the notch 8 at the position of the main supporting post 71, so that planarization can be improved more effectively, and extrusion light leakage performance can be improved. In fig. 20, a part of the first sub-wires have a notch 8, and a part of the second sub-wires 42 have a notch 8, but it is ensured that other parts of the first sub-wires 41 and the second sub-wires 42 are connected together to form a net structure.

In some alternative embodiments, referring to fig. 21, fig. 21 is a schematic plan view of a display panel according to another embodiment of the present invention, in a direction perpendicular to a plane of the first substrate 201, at least part of the first trace 4 semi-surrounds the support column 7;

the first trace 4 includes a winding portion 9, and the winding portion 9 semi-surrounds the support column 7 in a direction perpendicular to a plane of the first substrate 201;

in a direction perpendicular to the plane of the first substrate 201, there is a first space 10 between the wire-wound portion 9 and the support column 7.

In fig. 21, only the first trace 4 includes the second sub-trace 42 extending along the first direction X is schematically illustrated, but the first trace 4 may also include the first sub-trace 41 extending along the second direction Y, or the first trace 4 may also include the second sub-trace 42 extending along the first direction X and the first sub-trace 42 extending along the second direction Y, where the first sub-trace 41 and the second sub-trace 42 are connected, which is not illustrated in the drawing.

In fig. 21, the first sub-trace 41 includes a winding portion 9, and the winding portion 9 semi-surrounds the support column 7 in a direction perpendicular to a plane of the first substrate 201; there is a first space 10 between the wire-wound portion 9 and the support column 7 in a direction perpendicular to the plane of the first substrate 201, i.e., there is no overlap between the wire-wound portion 9 and the support column 7 in a direction perpendicular to the plane of the first substrate 201. In this embodiment, the winding portion 9 of the first trace 4 partly surrounds the support column 7, and in the direction perpendicular to the plane of the first substrate 201, a first space 10 is provided between the winding portion 9 and the support column 7, so that the flatness of the position where one end of the support column 7 near the array substrate contacts is better, the flatness of the position of the support column 7 can be improved, the extrusion light leakage performance is improved, and in addition, due to the first space 10, the flatness of the position corresponding to the support column 7 can be ensured even if a certain degree of alignment deviation exists, and the extrusion light leakage problem is improved.

In some alternative embodiments, with continued reference to FIG. 21, the first spacing 10 is 3 μm or greater.

It can be understood that the larger the distance of the first space 10, the better the planarization performance of the support column 7 position can be improved, and the better the extrusion light leakage performance can be improved. The smaller the first space 10, i.e., the more easily overlapping between the wire-wound portion 9 and the support column 7 in the direction perpendicular to the plane in which the first substrate 201 is located, the more easily the extrusion light leakage is generated. In this embodiment, the first intervals 10 are all 3 μm or more, so that the planarization performance of the support column 7 can be ensured to be good, and the extrusion light leakage performance can be improved.

In some alternative embodiments, with continued reference to fig. 18-20, the first trace 4 includes a notch 8, the notch 8 overlapping the support post 7 in a direction perpendicular to the plane of the first substrate base 201;

in the direction perpendicular to the plane of the first substrate 201, a second space 11 is provided between the edge of the notch 8 and the support column 7, and the second space 11 is 3.5 μm or more.

It is understood that after the first trace 4 is formed, a planarization layer is further required to be formed on a side of the first trace 4 away from the first substrate 201, and for the position of the support column 7, the planarization is poor, and when the display panel 100 is pressed against the support column 7, light leakage may occur. In this embodiment, in the direction perpendicular to the plane of the first substrate 201, the notch 8 overlaps the support pillar 7, so that the planarization performance of the support pillar 7 can be improved, and the extrusion light leakage performance can be improved. The larger the second space 11 between the edge of the notch 8 and the support column 7 in the direction perpendicular to the plane in which the first substrate 201 is located, the more the planarization at the position of the support column 7 can be improved, and the better the effect of improving the squeeze light leakage performance is. The smaller the second space 11, i.e., the more easily overlapping between the first trace 4 and the support column 7 in a direction perpendicular to the plane of the first substrate 201, the more easily the extrusion light leakage is generated. In this embodiment, the second space 11 is 3.5 μm or more, which can ensure good planarization of the support column 7, and improve extrusion light leakage performance.

In some alternative embodiments, referring to fig. 22, fig. 22 is a schematic plan view of a display panel according to still another embodiment of the present invention, the non-display area BB further includes a common electrode signal line 12, the common electrode signal line 12 at least partially surrounds the display area AA, the common electrode signal line 12 is electrically connected to the driving chip, and the common electrode signal line 12 is electrically connected to the common electrode 206, and the common electrode signal line 12 is located on the second metal layer 204.

Referring to fig. 22, a part of the film structure in the display area AA is not shown, only the first trace 4 with a mesh structure is schematically shown, the film structure in the display area AA can be referred to fig. 1 to 21, and the structure of the display area AA in this embodiment is applicable to any of the above embodiments and will not be repeated here.

In fig. 22, only the driving chip is bound to the array substrate 2 (COG) for illustration, and of course, COF may also be used, that is, the driving chip is bound to a flexible circuit board and bent to the back of the display panel 100, and the flexible circuit board is bound to the array substrate 2, so as to reduce the width of the non-display area BB. The common electrode 206 is electrically connected to input pads on the driving chip through output pads on the array substrate 2, which are not shown in the drawing.

The non-display area BB of fig. 22 has a plurality of common electrode signal lines 12, and of course, fig. 22 is only a possible connection manner of the common electrode signal lines 12, which is not the only limitation of the actual product. The common electrode signal line 12 is electrically connected to the driving chip and the common electrode 206, the common electrode signal line 12 transmits a common voltage of the driving chip to the common electrode 206, the common electrode signal line 12 is located on the second metal layer 204, and the common electrode signal line 12 may be electrically connected to the common electrode 206 through a via hole.

Specifically, the common electrode signal line 12 may be classified into three types, one type is an outer common electrode signal line 121, one type is a feedback common electrode signal line 122, one type is an inner common electrode signal line 123, in fig. 22, the inner common electrode signal line 123 entirely surrounds the display area AA, and the outer common electrode signal line 121 and the feedback common electrode signal line 122 partially surround the display area AA. In fig. 22, the outer common electrode signal line 121 and the feedback common electrode signal line 122 are electrically connected to the inner common electrode signal line 123 at the distal end (the side far from the driving chip) while being electrically connected to the common electrode 206, and the inner common electrode signal line 123 is also electrically connected to the common electrode 206 at the proximal end (the side near to the driving chip), so that voltage drop of the common voltage signal can be prevented and uniformity of the signal can be improved.

In some alternative embodiments, referring to fig. 23 and 24, fig. 23 is a schematic plan view of a further display panel provided by the present invention, and fig. 24 is a cross-sectional view of D-D' in fig. 23, where the non-display area BB includes a first non-display area BB1 and a second non-display area BB2 disposed opposite to each other along a second direction Y, and a third non-display area BB3 and a fourth non-display area BB4 disposed opposite to each other along the first direction X, and the first non-display area BB1 includes a driving chip;

the second non-display area BB2, the third non-display area BB3 and/or the fourth non-display area BB4 further include a second trace 13, the second trace 13 is in the same layer as the first trace 4, and the second trace 13 is electrically connected to the common electrode 206.

Specifically, the driving chip is located in the first non-display area, and in fig. 23, only the second non-display area BB2, the third non-display area BB3, and the fourth non-display area BB4 each further include the second trace 13, and of course, only the second trace 13 may be included in the second non-display area BB2, or only the third non-display area BB3 includes the second trace 13, or only the fourth non-display area BB4 includes the second trace 13, or the second non-display area BB2 and the third non-display area BB3 include the second trace 13, or the second non-display area BB2 and the fourth non-display area BB4 include the second trace 13, or the third non-display area BB3 and the fourth non-display area BB4 include the second trace 13. The second trace 13 may be located on the third metal layer 209, where the second trace 13 and the first trace 4 are disposed on the same layer, the third metal layer 209 disposed in the display area AA is disposed on the third metal layer 209 in the non-display area BB, and the second trace 13 is electrically connected to the common electrode 206, and optionally, the second trace 13 is directly connected to the common electrode 206, without via connection, which can reduce the process manufacturing difficulty, and meanwhile, the thickness of the display panel 100 is not increased. The second wire 13 and the first wire 4 can be manufactured in the same process, and the process is simplified without being separated.

It should be noted that, when the second trace 13 and the first trace 4 are located on the same side, that is, when the first trace 4 is located on the side of the common electrode 206 close to the first substrate 201, the second trace 13 is also located on the side of the common electrode 206 close to the first substrate 201, and when the first trace 4 is located on the side of the common electrode 206 far from the first substrate 201, the second trace 13 is also located on the side of the common electrode 206 far from the first substrate 201, and at this time, the second trace 13 is in direct contact with the common electrode trace 12.

The first wire 4 is parallel connected with the common electrode 206 in the display area AA, the total resistance after the common electrode 206 is parallel connected with the first wire 4 is reduced, meanwhile, in the embodiment, the second wire 13 is directly and electrically connected with the common electrode 206, so that the space of the non-display area BB can be fully utilized, the second wire 13 is parallel connected with the common electrode 206, the total resistance after the common electrode 206 is parallel connected with the second wire 13 and the first wire 4 is further reduced, and when the data voltage changes, the common voltage can be recovered to the reference more quickly, so that the horizontal crosstalk bright line is further improved.

Optionally, in the non-display area BB, in fig. 24, the second trace 13 is directly contacted with the common electrode 206, and the common electrode trace 12 is also directly contacted with the common electrode 206 (or the common electrode trace 12 is connected with the common electrode 206 through a via hole), so as to form a stacked structure of the second trace 13, the common electrode 206 and the common electrode trace 12, thereby further reducing the total resistance, and when the data voltage changes, the common voltage can be recovered to the reference more quickly, and further improving the horizontal crosstalk bright line.

In some alternative embodiments, with continued reference to fig. 23, the second trace 13 at least partially overlaps the common electrode signal line 12 in a direction perpendicular to the plane of the first substrate 201.

Fig. 23 schematically shows only a case where the common electrode signal line 12 is located within the second wiring 13 in a direction perpendicular to the plane of the first substrate 201, but of course, the second wiring 13 may partially overlap the common electrode signal line 12 in a direction perpendicular to the plane of the first substrate 201, which is not shown here.

It should be noted that, the second trace 13 is made of a metal material, and the metal material has light reflection, so that the second trace 13 is disposed behind the non-display area BB, and the non-display area BB reflects light, which is not beneficial for the display panel 100 to realize integral black. In this embodiment, the second trace 13 at least partially overlaps the common electrode signal line 12 in a direction perpendicular to the plane of the first substrate 201, so that the occupied space of the second trace 13 can be reduced as much as possible, and the reflection of light caused by the second trace 13 is reduced, which is beneficial to realizing the integral black of the display panel.

In some alternative embodiments, referring to fig. 25 and 26, fig. 25 is a schematic plan view of a display panel according to still another embodiment of the present invention, and fig. 26 is a cross-sectional view of a direction E-E' in fig. 25, wherein the non-display area BB includes a first non-display area BB1 and a second non-display area BB2 disposed opposite to each other along a second direction Y, and a third non-display area BB3 and a fourth non-display area BB4 disposed opposite to each other along the first direction X, and the first non-display area BB1 includes a driving chip;

The first non-display area BB1 further includes a third trace 14, where the third trace 14 is located on a side of the common electrode signal line 12 near the common electrode 206 in a direction perpendicular to the plane of the first substrate 201, and the third trace 14 is directly connected to the common electrode signal line 12 in contact.

Optionally, the second non-display area BB2, the third non-display area BB3 and/or the fourth non-display area BB4 further include a second trace 13, where the second trace 13 is in the same layer as the first trace 4, and the second trace 13 is directly connected to the common electrode 206, so as to further reduce the total resistance after being connected in parallel to the common electrode 206, and referring to fig. 23 and fig. 24, the specific limitation is not limited herein.

It can be appreciated that the common electrode 206 is generally in the first non-display area BB1 and does not entirely cover the first non-display area BB1 in the second direction Y. A portion of the common electrode signal line 12 connected to the driving chip is not covered with the common electrode 206. Optionally, the third trace 14 may be made of the same material and in the same process as the first trace 4, which is beneficial to simplifying the process.

The first non-display area BB1 further includes a third trace 14 on the film layer, and the third trace 14 is located on a side of the common electrode signal line 12 near the common electrode 206 in a direction perpendicular to the plane of the first substrate 201, and since the common electrode 206 does not completely cover the first non-display area BB1 in the first non-display area BB1, the third trace 14 is directly connected in contact with the common electrode signal line 12, the third trace 14 is connected in parallel with the common electrode signal line 12, and the total resistance after the third trace 14 is connected in parallel with the common electrode signal line 12 can be reduced, thereby reducing the voltage drop of the common voltage, improving the uniformity of the common voltage, and also utilizing the space of the third metal layer 209.

In some alternative embodiments, with continued reference to fig. 25 and 26, the third trace 14 has a linewidth m, and the first trace 4 has a linewidth n, m > n.

It will be appreciated that, in the display area AA, in order to avoid that the width of the first trace 4 is too large to affect the pixel aperture ratio, the width of the first trace 4 is as small as possible, but the third metal layer 209 disposed in the first non-display area BB1 is used to dispose the third trace 14, so that the width of the third trace 14 may be increased without considering the aperture ratio, and for the same metal material, the larger the cross-sectional area, the smaller the resistance, the larger the cross-sectional area of the third trace 14 is after the width of the third trace 14 is increased, and the smaller the resistance, the smaller the total resistance after being connected in parallel with the common electrode signal line 12 is, so that the voltage drop of the common voltage can be prevented, and the uniformity of the common voltage can be improved.

In some alternative embodiments, with continued reference to fig. 1, the first metal layer 202 includes scan lines 5 arranged along the second direction Y and extending in the first direction X, where the scan lines 5 and the data lines 3 intersect to define a region of the sub-pixels P, and the first trace 4 is located between at least some of the sub-pixels P.

In fig. 1, the scan lines 5 are located on the first metal layer 202, and are arranged along the second direction Y and extend in the first direction X, and the scan lines 5 and the data lines 3 intersect to define a region where the sub-pixels P are located.

The first wirings 4 are disposed between the sub-pixels P in the middle of fig. 1, and only the first wirings 4 including the first sub-wirings 41 extending along the second direction Y are schematically illustrated in fig. 1, and only one first sub-wiring 41 is disposed every two sub-pixels P in fig. 1, which is of course only schematically illustrated.

The first wiring 4 is combined with the sub-pixels P, the arrangement is more reasonable according to the arrangement mode of the sub-pixels P, the first wiring 4 is arranged between the sub-pixels P, the scanning lines 5 and the data lines 3 are arranged between the sub-pixels P, the black matrix BM (refer to figure 7) is arranged between the adjacent sub-pixels P for shading, the first wiring 4 is arranged on different metal layers with different layers of the scanning lines 5 and the data lines 3, the first wiring 4 is arranged on at least part of the sub-pixels P, and the distance between the first wiring 4 and the scanning lines 5 and the data lines 3 is as small as possible in the direction perpendicular to the first substrate 201, or the first wiring 4 overlaps with the scanning lines 5 and the data lines 3 as much as possible, so that the pixel aperture ratio is not reduced. The sub-pixels P are arranged in a plurality of rows and columns, and the first wires 4 are arranged among the sub-pixels P, so that the first wires 4 have sufficient arrangement space and arrangement quantity, the positions and quantity of the first wires 4 can be flexibly arranged according to the recovery time requirement on a public voltage signal by combining different degrees of generating bright wires, the first wires 4 can be arranged in different specification partitions of a display panel, the display panel is suitable for not only regular display panels, but also irregular display panels, such as special-shaped display panels with an under-screen camera, an R angle and the like, and the first wires 4 are arranged among the sub-pixels P, so that the first wires 4 have sufficient arrangement space and arrangement quantity, the special positions can be avoided, the areas with more wires can be avoided, and the first wires 4 are arranged in the areas with fewer wires and sufficient space.

In some alternative embodiments, referring to fig. 1, 5 and 6, in a first direction X, the sub-pixels P constitute a pixel row, and in a second direction Y, the sub-pixels P constitute a pixel column;

the first sub-wiring 41 is located between at least part of the pixel columns;

alternatively, the second sub-trace 42 is located between at least some of the rows of pixels;

alternatively, the first sub-trace 41 is located between at least some of the columns of pixels, and the second sub-trace 42 is located between at least some of the rows of pixels.

Specifically, a plurality of sub-pixels P along the first direction X constitute a pixel row, and a plurality of sub-pixels P along the second direction Y constitute a pixel column. In fig. 1, the first sub-trace 41 is located between at least some pixel columns, in fig. 5, the second sub-trace 42 is located between at least some pixel rows, in fig. 6, the first sub-trace 41 is located between at least some pixel columns, the second sub-trace 42 is located between at least some pixel rows, and the first sub-trace 41 is connected to the second sub-trace 42.

In this embodiment, the first sub-trace 41 extending along the second direction Y is combined with the pixel columns, and is located between at least some pixel columns, and the second sub-trace 42 extending along the first direction X is combined with the pixel rows, and is arranged according to the arrangement manner of the pixel rows and the pixel columns, so that the arrangement is more reasonable, the structure is more diversified, and the application range is wider. The first wiring 4 is combined with the sub-pixels P, the arrangement is more reasonable according to the arrangement mode of the sub-pixels P, the first wiring 4 is arranged between the sub-pixels P, the scanning lines 5 and the data lines 3 are arranged between the sub-pixels P, the black matrix BM (refer to figure 7) is arranged between the adjacent sub-pixels P for shading, the first wiring 4 is arranged on different metal layers with different layers of the scanning lines 5 and the data lines 3, the first wiring 4 is arranged on at least part of the sub-pixels P, and the distance between the first wiring 4 and the scanning lines 5 and the data lines 3 is as small as possible in the direction perpendicular to the first substrate 201, or the first wiring 4 overlaps with the scanning lines 5 and the data lines 3 as much as possible, so that the pixel aperture ratio is not reduced. The sub-pixels P are arranged in a plurality of rows and columns, and the first wires 4 are arranged among the sub-pixels P, so that the first wires 4 have sufficient arrangement space and arrangement quantity, the positions and quantity of the first wires 4 can be flexibly arranged according to the recovery time requirement on a public voltage signal by combining different degrees of generating bright wires, the first wires 4 can be arranged in different specification partitions of a display panel, the display panel is suitable for not only regular display panels, but also irregular display panels, such as special-shaped display panels with an under-screen camera, an R angle and the like, and the first wires 4 are arranged among the sub-pixels P, so that the first wires 4 have sufficient arrangement space and arrangement quantity, the special positions can be avoided, the areas with more wires can be avoided, and the first wires 4 are arranged in the areas with fewer wires and sufficient space.

In some alternative embodiments, reference is continued to fig. 7, 8, 9, 11, 13, 14, 15, 16, 17, 18, 19, 20, and 21.

The first sub-wiring 41 is located between any adjacent two pixel columns;

alternatively, the second sub-trace 42 is located between any two adjacent rows of pixels;

alternatively, the first sub-trace 41 is located between any two adjacent pixel columns, and the second sub-trace 42 is located between any two adjacent pixel rows.

Specifically, in fig. 7, 11, 13 and 18, the first trace 4 includes a first sub-trace 41 extending along the second direction Y, where the first sub-trace 41 is located between any two adjacent pixel columns, i.e. in the first direction X, the first trace 4 is disposed between any two adjacent sub-pixels, the more the first sub-trace 41 is connected to the common electrode 206, the more stable the connection is, the lower the resistance is after the parallel connection with the common electrode 206, when the data voltage changes, the more the common voltage can be quickly restored to the reference, so that the horizontal crosstalk bright line is further improved, and since the sub-pixels P are disposed in multiple rows and columns, the first trace 4 is disposed between the sub-pixels P, so that the first trace has a sufficient disposition space and disposition number.

In fig. 8, 15, 16, 19 and 21, the first trace 4 includes a second sub-trace 42 extending in the first direction X, where the second sub-trace 42 is located between any two adjacent pixel rows, i.e. along the second direction Y, and the second sub-trace 42 is located between any two sub-pixels, where the more the number of the second sub-traces 42 is, the more stable the connection between the second sub-trace 42 and the common electrode 206 is, the lower the resistance after the second sub-trace is connected in parallel with the common electrode 206, and when the data voltage changes, the more the common voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is further improved.

Fig. 9, 14, 17 and 20 show that the first trace 4 includes a first sub-trace 41 and a second sub-trace 42 that are connected to each other, the first sub-trace 41 is located between any two adjacent pixel columns, the second sub-trace 42 is located between any two adjacent pixel rows, that is, the first trace 4 is disposed between any two sub-pixels along the first direction X and between any two sub-pixels along the second direction Y, the more the number of the first sub-trace 41 and the second sub-trace 42 is, the more stable the connection with the common electrode 206 is, the lower the resistance after the parallel connection with the common electrode 206 is, and when the data voltage changes, the more the common voltage can be quickly restored to the reference, thereby further improving the horizontal crosstalk.

The first wiring 4 is combined with the sub-pixels, and is arranged in a sub-pixel arrangement mode, so that the arrangement is more reasonable.

In some alternative embodiments, referring to fig. 27 and 28, fig. 27 is a schematic plan view of a further display panel provided by the present invention, and fig. 28 is a schematic plan view of a further display panel provided by the present invention.

The first trace 4 in fig. 27 and 28 includes a second sub-trace 42 extending along the first direction X, the second sub-trace 42 including at least a first segment 15 and a second segment 16, the first segment 15 being connected to a portion of the first sub-trace 41 thereof, the second segment 16 being connected to another portion of the first sub-trace 41;

in the first direction X, the extension line of the first segment 15 and the extension line of the second segment 16 are located on the same straight line, or the extension line of the first segment 15 and the extension line of the second segment 16 do not coincide.

As shown in fig. 27, the first segment 15 is connected to the 1 st to 9 th first sub-wirings 41, the second segment 16 is connected to the 10 th to 18 th first sub-wirings 41, and the extension lines of the first segment 15 and the extension lines of the second segment 16 are positioned on the same line along the first direction X, so that the first segment 15 and the second segment 16 can be etched at the same time and the etching is more convenient during the manufacturing.

As shown in fig. 28, in the first direction X, the extension line of the first segment 15 and the extension line of the second segment 16 are located on the same line, or the extension line of the first segment 15 and the extension line of the second segment 16 are not overlapped, the first segment 15 is connected with the 1 st to 8 th first sub-wirings 41, the second segment 16 is connected with the 8 th to 10 th first sub-wirings 41, and the first segment 15 and the second segment 16 are not located on the same line, that is, the first segment 15 and the second segment 16 are arranged in a dislocation manner. Of course, fig. 28 also shows that the second sub-trace 42 further includes a third section, which is on the same extension line as the first section 15, and is also offset from the second section 16.

The second sub-wirings 42 in this embodiment may be arranged in a partitioned manner. For the special-shaped display panel 100, for example, a water drop screen, or a special position with an under-screen camera, an R angle, etc., only the under-screen camera is taken as an example for illustration in fig. 28, and in order not to affect the display function or the image capturing function of the special-shaped display panel 100, the special positions need to reduce the second sub-trace 42 as much as possible, so as not to cause the second sub-trace 42 to be visible, and affect the display function or the image capturing function thereof. In the embodiment, the special positions of the under-screen cameras are avoided in a dislocation mode, and the under-screen camera is more flexible in arrangement and higher in practicability.

Of course, according to the actual requirements and the special functions of the display panel 100, the second sub-wirings 42 can be arranged in different areas, so as to change the density of the second sub-wirings 42, thereby having stronger pertinence and wider application range.

In some alternative embodiments, with continued reference to fig. 1, 2, and 29 and 30, fig. 29 is a schematic plan view of yet another display panel provided by the present invention, and fig. 30 is a cross-sectional view taken along the direction F-F' in fig. 29. The first metal layer 202 includes scan lines 5 arranged along the second direction Y and extending in the first direction X, and the scan lines 5 and the data lines 3 cross to define a region of the sub-pixel P;

the display panel 100 further includes an active layer 207, the active layer 207 being located between the first substrate 201 and the first metal layer 202, or the active layer 207 being located between the first metal layer 202 and the second metal layer 204; the display panel 100 further includes a transistor T, the semiconductor T4 layer of which is located at the active layer 207.

The active layer 207 is shown in fig. 1 and 2 as being located between the first metal layer 202 and the second metal layer 204, and the transistor T is a bottom gate structure, and the active layer 207 is shown in fig. 29 and 30 as being located between the first substrate base 201 and the first metal layer 202, and the transistor T is a top gate structure. The top gate structure further includes a light shielding layer 2010, where the light shielding layer 2010 is located on a side of the semiconductor T4 close to the first substrate 201, for preventing leakage current of the semiconductor T4.

The structure of the invention is suitable for both top gate structures and bottom gate structures, and has wide application.

Based on the same inventive concept, the present invention further provides a method for manufacturing a display panel 100, referring to fig. 31, fig. 31 is a flowchart of a method for manufacturing a display panel provided by the present invention, for manufacturing the display panel 100 of any embodiment in fig. 1 to 30, and the structure of the display panel 100 specifically refers to fig. 1 to 30, where the display panel 100 includes a color film substrate 1 and an array substrate 2 that are disposed opposite to each other, and the array substrate 2 includes: a first substrate base 201; a first metal layer 202 located on one side of the first substrate 201, a second metal layer 204 located on one side of the first metal layer 202 away from the first substrate 201, and a first insulating layer 203 between the first metal layer 202 and the second metal layer 204; the second metal layer 204 includes data lines 3, and the plurality of data lines 3 are arranged along a first direction X and extend along a second direction Y; the common electrode 206 is positioned on one side of the second metal layer 204 away from the first substrate 201, a second insulating layer 205 is arranged between the second metal layer 204 and the common electrode 206, and the orthographic projection of the data line 3 on the plane of the first substrate 201 and the orthographic projection of the common electrode 206 on the plane of the first substrate 201 at least partially overlap; the display panel 100 further includes a display area AA and a non-display area BB at least partially surrounding the display area AA, at least the display area AA further includes a first trace 4, where the first trace 4 is located on a side of the common electrode 206 away from the first substrate 201, or the first trace 4 is located on a side of the common electrode 206 near the first substrate 201, and the first trace 4 is in direct contact connection with the common electrode 206;

The first trace 4 includes a first sub-trace 41 extending along the second direction Y;

alternatively, the first trace 4 includes a second sub-trace 42 extending along the first direction X;

alternatively, the first trace 4 includes a first sub-trace 41 extending in the second direction Y and a second sub-trace 42 extending in the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41;

the manufacturing method comprises the following steps:

s1: providing a color film substrate 1;

s2: manufacturing an array substrate 2, comprising:

s201: providing a first substrate base 201;

s202: forming a first metal layer 202 on one side of a first substrate base 201;

s203: forming a first insulating layer 203 on a side of the first metal layer 202 remote from the first substrate base 201;

s204: forming a second metal layer 204 on one side of the first insulating layer 203 far away from the first substrate 201, and etching the second metal layer 204 to form data lines 3 arranged along a first direction X and extending along a second direction Y;

s205: forming a second insulating layer 205 on a side of the second metal layer 204 remote from the first substrate 201;

s206: forming a common electrode 206 on a side of the second insulating layer 205 away from the first substrate 201, wherein the orthographic projection of the data line 3 on the plane of the first substrate 201 at least partially overlaps with the orthographic projection of the common electrode 206 on the plane of the first substrate 201;

S207: at least in the display area AA of the display panel 100, a third metal layer 209 is formed on a side of the common electrode 206 away from the first substrate 201, and the third metal layer 209 is etched to form a first trace 4, so that the first trace 4 is in direct contact with the common electrode 206, wherein the first trace 4 includes a first sub-trace 41 extending along the second direction Y; alternatively, the first trace 4 includes a second sub-trace 42 extending along the first direction X; alternatively, the first trace 4 includes a first sub-trace 41 extending in the second direction Y and a second sub-trace 42 extending in the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41.

Alternatively, S206: at least in the display area AA of the display panel 100, a third metal layer 209 is formed on a side of the second insulating layer 205 away from the first substrate 201, and the third metal layer 209 is etched to form a first trace 4, where the first trace 4 includes a first sub-trace 41 extending along the second direction Y; alternatively, the first trace 4 includes a second sub-trace 42 extending along the first direction X; alternatively, the first trace 4 includes a first sub-trace 41 extending in the second direction Y and a second sub-trace 42 extending in the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41;

S207: the common electrode 206 is formed on a side of the first trace 4 away from the first substrate 201, where the orthographic projection of the data line 3 on the plane of the first substrate 201 at least partially overlaps with the orthographic projection of the common electrode 206 on the plane of the first substrate 201, and the first trace 4 is in direct contact with the common electrode 206.

Fig. 31 is a schematic illustration only, taking the manufactured first trace 4 as an example, where the common electrode 206 is located at a side far from the first substrate 201.

Alternatively, the scan line 5 may be obtained by etching the first metal layer 202 by wet etching, the data line 3 may be obtained by etching the second metal layer 204 by wet etching, and the first trace 4 may be obtained by etching the third metal layer 209 by wet etching.

In the present invention, the first trace 4 is directly contacted with the common electrode 206, and no insulating layer is required to be formed between the common electrode 206 and the first trace 4 for re-punching, and the first trace is connected through the via hole, so that the manufacturing process is complex and the thickness of the display panel 100 is increased. The first trace 4 is in direct contact with the common electrode 206, which is simple in process and is also beneficial to reducing the thickness of the display panel 100.

Referring to fig. 32, fig. 32 is a schematic plan view of a display device according to an embodiment of the present invention, and a display device 1000 according to the present embodiment includes a display panel 100 according to the above embodiment of the present invention. The embodiment of fig. 32 is only an example of a mobile phone, and the display device 1000 is described, but it is to be understood that the display device 1000 provided in the embodiment of the present invention may be any other display device 1000 having a display function, such as a computer, a television, a vehicle-mounted display device, etc., which is not particularly limited in the present invention. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and the specific description of the display panel in each of the above embodiments may be referred to specifically, and this embodiment is not repeated here.

According to the embodiment, the display panel, the manufacturing method thereof and the display device provided by the invention have the following beneficial effects:

according to the invention, the first wiring is arranged on one side of the public electrode far away from the first substrate, and the first wiring is in direct contact connection with the public electrode, so that the first wiring and the public electrode are in parallel connection, the first wiring can adopt metal or other conductors with lower impedance, and according to the resistance principle, the total resistance after parallel connection is smaller than that of the two parallel connection resistors, so that the total resistance after parallel connection of the public electrode and the first wiring is reduced, and when the data voltage changes, the public voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is improved. In the invention, the first wiring is in direct contact with the public electrode, and one side insulating layer is not required to be arranged above the public electrode, and then the first wiring is manufactured and then connected through the via hole, so that the manufacturing process is complex, and the thickness of the display panel is increased. The first wiring is in direct contact with the common electrode, so that the process is simple, and the thickness of the display panel is reduced. The first wiring comprises a first sub-wiring extending along the second direction, the first sub-wiring is directly connected with the common electrode to form parallel connection, the total resistance of the first sub-wiring and the common electrode after being connected in parallel is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, so that the horizontal crosstalk bright line is improved. Or, the first wiring comprises a second sub-wiring extending along the first direction, the second sub-wiring is directly connected with the common electrode to form parallel connection, the total resistance of the second sub-wiring and the common electrode after parallel connection is reduced, and when the data voltage changes, the common voltage can be quickly restored to the reference, so that the horizontal crosstalk bright line is improved. Or, the first wire comprises a first sub-wire extending along the second direction and a second sub-wire extending along the first direction, the second sub-wire is connected with the first sub-wire, the first sub-wire and the second sub-wire are connected with the common electrode directly, the total resistance after parallel connection can be further reduced, the total resistance is reduced, when the data voltage changes, the common voltage can be quickly restored to the reference, and the horizontal crosstalk bright line is improved.

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. The utility model provides a display panel which characterized in that includes color film base plate and the array substrate of relative setting, the array substrate includes:

a first substrate base plate;

the first metal layer is positioned on one side of the first substrate base plate, the second metal layer is positioned on one side of the first metal layer away from the first substrate base plate, and a first insulating layer is arranged between the first metal layer and the second metal layer; the second metal layer comprises data lines, and a plurality of the data lines are distributed along a first direction and extend along a second direction;

the common electrode is positioned at one side of the second metal layer far away from the first substrate, a second insulating layer is arranged between the second metal layer and the common electrode, and the orthographic projection of the data line on the plane of the first substrate and the orthographic projection of the common electrode on the plane of the first substrate at least partially overlap;

The display panel further comprises a display area and a non-display area at least partially surrounding the display area, at least the display area further comprises a first wiring, the first wiring is positioned on one side of the common electrode far away from the first substrate base plate, or the first wiring is positioned on one side of the common electrode close to the first substrate base plate, and the first wiring is in direct contact connection with the common electrode;

the first wiring comprises a first sub-wiring extending along the second direction;

alternatively, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, and the second sub-trace is connected to the first sub-trace.

2. The display panel according to claim 1, wherein the color film substrate comprises a second substrate and a black matrix located at one side of the second substrate, and an orthographic projection of the first trace on a plane of the first substrate is located in an orthographic projection of the black matrix on the plane of the first substrate.

3. The display panel of claim 1, wherein the color film substrate comprises a second substrate;

the display panel further comprises a support column, wherein the support column is positioned between the first substrate base plate and the second substrate base plate;

the first wiring is at least partially overlapped with the support column in a direction perpendicular to the plane of the first substrate;

or, in a direction perpendicular to a plane of the first substrate, at least part of the first trace semi-surrounds the support column;

or, the first trace includes a notch, and in a direction perpendicular to a plane of the first substrate, the notch overlaps the support column.

4. A display panel according to claim 3, wherein at least part of the first trace partly surrounds the support column in a direction perpendicular to the plane of the first substrate;

the first wiring comprises a winding part, and the winding part semi-surrounds the support column in the direction perpendicular to the plane of the first substrate;

in the direction perpendicular to the plane of the first substrate base plate, a first interval is arranged between the winding part and the support column.

5. The display panel according to claim 4, wherein the first interval is 3 μm or more.

6. The display panel of claim 3, wherein the first trace includes a notch overlapping the support post in a direction perpendicular to a plane of the first substrate;

in the direction perpendicular to the plane of the first substrate, a second interval is arranged between the edge of the notch and the support column, and the second interval is more than or equal to 3.5 mu m.

7. The display panel of claim 1, wherein the display panel comprises,

the non-display area further comprises a common electrode signal line, the common electrode signal line at least partially surrounds the display area, the common electrode signal line is electrically connected with the driving chip, the common electrode signal line is electrically connected with the common electrode, and the common electrode signal line is located on the second metal layer.

8. The display panel according to claim 7, wherein the non-display region includes a first non-display region and a second non-display region disposed opposite to each other in the second direction, and a third non-display region and a fourth non-display region disposed opposite to each other in the first direction, the first non-display region including the driving chip;

The second non-display area, the third non-display area and/or the fourth non-display area further comprise a second wiring, the second wiring is in the same layer as the first wiring, and the second wiring is electrically connected with the common electrode.

9. The display panel according to claim 8, wherein the second wiring is at least partially overlapped with the common electrode signal line in a direction perpendicular to a plane in which the first substrate is located.

10. The display panel of claim 7, wherein the non-display region includes a first non-display region and a second non-display region disposed opposite along the second direction, and a third non-display region and a fourth non-display region disposed opposite along the first direction, the first non-display region including a driving chip;

the first non-display area further comprises a third wiring, the third wiring is located on one side, close to the common electrode, of the common electrode signal line in the direction perpendicular to the plane where the first substrate is located, and the third wiring is in direct contact connection with the common electrode signal line.

11. The display panel of claim 10, wherein the third trace has a line width of m, and the first trace has a line width of n, m > n.

12. The display panel of claim 1, wherein the first metal layer includes scan lines arranged along the second direction and extending in the first direction, the scan lines and the data lines intersecting to define a region of sub-pixels, the first trace being located between at least a portion of the sub-pixels.

13. The display panel of claim 12, wherein in the first direction, the subpixels constitute rows of pixels and in the second direction, the subpixels constitute columns of pixels;

the first sub-wiring is positioned between at least part of the pixel columns;

or, the second sub-wiring is located between at least part of the pixel rows;

alternatively, the first sub-trace is located between at least part of the pixel columns, and the second sub-trace is located between at least part of the pixel rows.

14. The display panel of claim 13, wherein the first sub-trace is located between any adjacent two of the columns of pixels;

or the second sub-wiring is positioned between any two adjacent pixel rows;

or the first sub-wiring is located between any two adjacent pixel columns, and the second sub-wiring is located between any two adjacent pixel rows.

15. The display panel of claim 1, wherein when the first trace includes a second sub-trace extending in the first direction, the second sub-trace includes at least a first segment and a second segment, the first segment connection being connected to a portion of the first sub-trace therein, the second segment being connected to another portion of the first sub-trace;

and along the first direction, the extension line of the first section and the extension line of the second section are positioned on the same straight line, or the extension line of the first section and the extension line of the second section are not overlapped.

16. The display panel of claim 1, wherein the first metal layer includes scan lines arranged along the second direction and extending in the first direction, the scan lines and the data lines intersecting to define a region of sub-pixels;

the display panel further includes an active layer between the first substrate base plate and the first metal layer, or between the first metal layer and the second metal layer; the display panel further includes a transistor, and a semiconductor layer of the transistor is located at the active layer.

17. The manufacturing method of the display panel is characterized in that the display panel comprises a color film substrate and an array substrate which are oppositely arranged, and the array substrate comprises:

a first substrate base plate;

or, the first wire comprises a first sub-wire extending in the second direction and a second sub-wire extending along the first direction, and the second sub-wire is connected with the first sub-wire;

the manufacturing method comprises the following steps:

providing a color film substrate;

manufacturing an array substrate, comprising:

providing a first substrate base plate;

forming a first metal layer on one side of the first substrate base plate;

forming a first insulating layer on one side of the first metal layer away from the first substrate base plate;

forming a second insulating layer on one side of the second metal layer away from the first substrate base plate;

forming a common electrode on one side of the second insulating layer far away from the first substrate, wherein the orthographic projection of the data line on the plane of the first substrate at least partially overlaps with the orthographic projection of the common electrode on the plane of the first substrate; forming a third metal layer on one side of the common electrode far away from the first substrate base plate in at least a display area of the display panel, and etching the third metal layer to form a first wiring, so that the first wiring is in direct contact with the common electrode, wherein the first wiring comprises a first sub-wiring extending along the second direction; alternatively, the first trace includes a second sub-trace extending along the first direction; or, the first wire comprises a first sub-wire extending in the second direction and a second sub-wire extending along the first direction, and the second sub-wire is connected with the first sub-wire;

18. A display device comprising the display panel of any one of claims 1 to 16.