CN114531124A

CN114531124A - Time sequence control circuit for common mode feedback of switched capacitor

Info

Publication number: CN114531124A
Application number: CN202210035470.6A
Authority: CN
Inventors: 李强; 赵晨曦; 周雄
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-05-24

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a time sequence applied to common-mode feedback of a switched capacitor, which can better avoid differential mode output signal disturbance caused by the switching activity of a common-mode feedback circuit. In a typical switched capacitor common mode feedback circuit, at rising/falling edges of two clock phases, a capacitor is connected with a differential output signal, a load of an output end of an operational amplifier changes, the capacitor starts to be charged/discharged, and a waveform established by differential output voltage is disturbed due to non-ideal characteristics of switches such as charge injection and clock feed-through. This disturbance can affect the accuracy of the final established waveform in the cycle. The patent provides a sequential control circuit working of switch capacitor common mode feedback, when an operational amplifier effectively outputs differential mode signals voutp and voutn, the connection mode of the operational amplifier output and a sampling capacitor Cs is kept unchanged, and no switch activity exists; and in the next phase, when the output of the operational amplifier is reset, the common mode feedback circuit is activated. At this time, the disturbance caused by the common mode feedback only exists at the reset moment, and the establishment of the effective output signal of the operational amplifier is not influenced. Therefore, the scheme can be helpful for improving the building precision of the switched capacitor amplifying circuit. Meanwhile, the output of the common mode feedback is not influenced by the size of the output signal of the operational amplifier, and the common mode feedback output voltage cmfb is more stable.

Description

Time sequence control circuit for common mode feedback of switched capacitor

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to a time sequence applied to common-mode feedback of a switched capacitor, which can better avoid differential mode output signal disturbance caused by the switching activity of a common-mode feedback circuit.

Background

The invention belongs to the technical field of integrated circuits, and a differential amplifier is one of the most important modules in the field of integrated circuits and can trace back to the era of vacuum tubes. Because of its excellent various performances, the fully differential operational amplifier has become an important component of modern high-performance analog circuits and mixed-signal circuits. The disadvantage of the fully differential operational amplifier is that the common mode loop gain of the external feedback loop is very small, the output common mode level may be unstable, and an additional common mode feedback loop is usually required to stabilize the dc operating point. And the common-mode feedback structure directly influences the performances of the fully differential operational amplifier. The common mode feedback structure can be divided into a continuous time common mode feedback structure and a switch capacitor common mode feedback structure. The continuous-time common-mode feedback structure is mainly applied to a continuous-time circuit. The switched capacitor technology adopts a clock signal to control the on and off of a switch so as to control the flow of charges stored on a capacitor and output a static working point of a common-mode voltage stable fully-differential amplifier. Compared with a continuous time common mode feedback circuit, the switched capacitor common mode feedback circuit does not increase extra power consumption and does not limit the differential output swing of the fully differential amplifier.

A typical switched capacitor common mode feedback circuit consists of two common mode sampling capacitors Cs, two integrating capacitors Cint, and two non-overlapping clock phase controlled CMOS transistor pass gate switches S1, S2, as shown in fig. 1. By utilizing the cmfb signal, the fully differential operational amplifier can stabilize the output common mode of the operational amplifier at vcm after a plurality of periods. The disadvantages of this common mode feedback circuit are: as shown in the timing waveform of fig. 2, at the rising/falling edges of two clock phases S1/S2, the Cs capacitor starts to be connected to the differential output signals voutp, voutn, the load at the output end of the operational amplifier changes, and the Cs starts to be charged/discharged, which causes the differential output voltage voutp, voutn to create a disturbance in the waveform due to the non-ideal characteristics of the switches such as charge injection and clock turn-on. The disturbance can affect the accuracy of the finally established waveform in the period, and particularly under the condition of high-speed sampling, the establishment time is short, and the operational amplifier needs more establishment time to recover from the disturbance; similarly, a similar effect occurs when the phase is reset.

Disclosure of Invention

The patent provides a novel switched capacitor common mode feedback's sequential control circuit, can avoid the differential mode output signal disturbance that common mode feedback circuit switch activity caused more thoroughly.

The patent is realized through the following technical route:

a time sequence control circuit of common mode feedback of a switched capacitor is characterized in that differential mode output signal disturbance caused by the switching activity of a common mode feedback circuit can be better avoided.

The time sequence control circuit comprises the following parts: the D flip-flop, Delay unit, inverter and NOR gate. Clkin is the switching frequency of the main amplifying circuit, a two-phase frequency division clock which is formed by drawing a D trigger is comfortable, then the two-phase frequency division clock passes through a td Delay phase generated by a Delay unit, and finally two-phase non-overlapping clocks S1 and S2 are generated by an inverter and an OR gate.

When the time sequence control circuit of the common mode feedback of the switched capacitor works, when the operational amplifier effectively outputs differential mode signals voutp and voutn, the connection mode of the operational amplifier output and the sampling capacitor Cs is kept unchanged, and no switching activity exists; and in the next phase, when the output of the operational amplifier is reset, the common mode feedback circuit is activated again. At this time, the disturbance caused by the common mode feedback only exists at the reset moment, and the establishment of the effective output signal of the operational amplifier is not influenced. Therefore, the scheme can be helpful for improving the building precision of the switched capacitor amplifying circuit. Meanwhile, the output of the common mode feedback is not influenced by the size of the output signal of the operational amplifier, and the common mode feedback output voltage cmfb is more stable.

The technical scheme of the design of the switch capacitor common mode feedback sequential control circuit only needs a plurality of logic gates, and the area and power consumption overhead are small. However, since the frequency of the control clocks S1, S2 is half of the Clkin, the bandwidth of the common mode feedback is half of that of the conventional scheme. Nevertheless, since the bandwidth is not critical, the impact is small.

Drawings

FIG. 1 shows a conventional switched capacitor common mode feedback circuit

FIG. 2 shows timing waveforms of a conventional switched capacitor common mode feedback circuit

Fig. 3 a novel switched capacitor common mode feedback sequential control circuit proposed by this patent

FIG. 4 shows timing waveforms after the novel timing control circuit is adopted

Detailed Description

The following specifically introduces the technical scheme of the patent with reference to the figure:

as shown in fig. 1, a typical switched capacitor common mode feedback circuit is composed of two common mode sampling capacitors Cs, two integrating capacitors Cint, and two non-overlapping clock phase-controlled switches S1, S2. For turn-on performance, CMOS passgate switches are commonly used here. The working principle of the common mode feedback circuit is as follows: at the S1 phase, the upper and lower polar plates of the Cs capacitor are respectively connected with the vcm and the bias signal for sampling; and in the S2 phase, the Cs capacitor and the Cint capacitor are interconnected and conducted. The two Cs capacitors respectively sample the differential output signals voutp and voutn of the operational amplifier. Through two phases of S1 and S2, one end of the Cs capacitor is switched from vcm to voutp or voutn, and the charge stored on the Cs capacitor is changed; then the other end shares charge with Cint, and the integration operation is performed on the voltage domain, so that the comparison between the operational amplifier output common mode (voutp + voutn)/2 and vcm is completed, and the comparison result is output as a cmfb signal. By utilizing the cmfb signal, the main circuit can stabilize the output common mode of the operational amplifier at vcm after a plurality of periods.

This common mode feedback has the following advantages: the common mode feedback circuit only adopts a capacitor and a switch, and has no static current overhead, so that the power consumption is low; secondly, the capacitor and the transmission gate switch are passive devices, are not easily influenced by the size of an output signal, can ensure good linearity of common-mode feedback, and are more suitable for high-linearity switch amplification circuits; then, because the amplifier does not have active amplification, the gain is less than 1V/V, the bandwidth is higher, and when the amplifier is connected with a main amplifying circuit to form a closed loop, the natural stability is better.

But this common mode feedback also has disadvantages. As shown in fig. 2, at the rising/falling edges of the two clock phases of S1/S2, the Cs capacitor starts to be connected to the differential output signals voutp and voutn, the load at the output end of the operational amplifier changes, and the Cs capacitor starts to be charged/discharged, which causes the differential output voltage voutp and voutn to create a disturbance in the waveform established by the differential output voltages voutp and voutn along with the non-ideal characteristics of the switches such as charge injection and clock turn-on. The disturbance can affect the accuracy of the finally established waveform in the period, and particularly under the condition of high-speed sampling, the establishment time is short, and the operational amplifier needs more establishment time to recover from the disturbance; similarly, a similar effect occurs when the phase is reset.

The patent provides a novel switched capacitor common mode feedback's sequential control circuit, can avoid the differential mode output signal disturbance that common mode feedback circuit switch activity caused well. As shown in fig. 3, the timing control circuit is composed of the following parts: the D flip-flop, Delay unit, inverter and NOR gate. Clkin is the switching frequency of the main amplifying circuit, a 2-frequency division clock composed of a D trigger is input, then a td delay phase is generated through a delay unit, and finally two-phase non-overlapping clocks S1 and S2 generated by inverters and an OR-NOT gate are generated.

By using this timing control circuit, the timing waveforms as shown in fig. 3 can be realized: when the operational amplifier effectively outputs the differential mode signals voutp and voutn, the connection mode of the operational amplifier output and the sampling capacitor Cs is kept unchanged, and no switching activity exists; and in the next phase, when the output of the operational amplifier is reset, the common mode feedback circuit is activated again. At this time, the disturbance caused by the common mode feedback only exists at the reset moment, and the establishment of the effective output signal of the operational amplifier is not influenced. Therefore, the scheme can be helpful for improving the building precision of the switched capacitor amplifying circuit. Meanwhile, the output of the common mode feedback is not influenced by the size of the output signal of the operational amplifier, and the common mode feedback output voltage cmfb is more stable. The technical scheme only needs a few logic gates, and the area and the power consumption cost are small. There is a disadvantage that the bandwidth of the common mode feedback is half of that of the conventional scheme because the control clocks S1, S2 have a frequency of 1/2 of Clkin. In many designs, however, this bandwidth is not critical and is of less impact.

Claims

1. A time sequence control circuit of common mode feedback of a switched capacitor is characterized in that differential mode output signal disturbance caused by the switching activity of a common mode feedback circuit can be better avoided.

2. The time sequence control circuit comprises the following parts: d flip-flop, Delay sheetAn element, an inverter and an nor gate. The Clkin is the switching frequency of the main amplifying circuit, comfortable two-frequency division clock which is formed by drawing a D trigger is used, and then t is generated by a Delay unit_dThe phases are delayed and two-phase non-overlapping clocks S1 and S2 are finally generated by inverters and or not gates.

3. When the time sequence control circuit of the common mode feedback of the switched capacitor works, when the operational amplifier effectively outputs differential mode signals voutp and voutn, the connection mode of the operational amplifier output and the sampling capacitor Cs is kept unchanged, and no switch activity exists; and in the next phase, when the output of the operational amplifier is reset, the common mode feedback circuit is activated again. At this time, the disturbance caused by the common mode feedback only exists at the reset moment, and the establishment of the effective output signal of the operational amplifier is not influenced. Therefore, the scheme can be helpful for improving the building precision of the switched capacitor amplifying circuit. Meanwhile, the output of the common mode feedback is not influenced by the size of the output signal of the operational amplifier, and the common mode feedback output voltage cmfb is more stable.

4. The technical scheme of the design of the switch capacitor common mode feedback sequential control circuit only needs a plurality of logic gates, and the area and power consumption overhead are small. But since the control clocks S1, S2 have half the frequency of Clkin, the bandwidth of the common mode feedback is half that of the conventional scheme. Nevertheless, since the bandwidth is not critical, the impact is small.