CN114501967B

CN114501967B - Display panel and electronic device

Info

Publication number: CN114501967B
Application number: CN202210083653.5A
Authority: CN
Inventors: 秦福宏; 郑浩旋
Original assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2023-03-24
Anticipated expiration: 2042-01-20
Also published as: CN114501967A

Abstract

The application provides a display panel and electronic equipment, display panel includes first circuit board, second circuit board and glass panels, first circuit board is connected with glass panels, be provided with the chip circuit on the glass panels, the second circuit board includes signal input part, the chip circuit is connected with signal input part electricity through first signal line, be used for receiving first signal, the chip circuit still is connected with signal input part electricity through the second signal line, be used for receiving the second signal, be provided with first public ground wire around first signal line and the second signal line, be provided with the public ground wire of second on the second circuit board, display panel still includes connector circuit, first public ground wire passes through connector circuit and is connected with the public ground wire of second on the second circuit board electricity. Because the first common ground wire is arranged around the first signal wire and the second signal wire, static electricity can be transmitted to the second common ground wire through the first common ground wire through the connecting sub-circuit to be released, and signal fluctuation and even damage to the wires are avoided.

Description

Display panel and electronic device

Technical Field

The present application relates to the field of display circuit technology, and in particular, to a display panel and an electronic device.

Background

Display technology has been one of the important research directions in electronic devices. At present, a driving Chip in a Display panel is developing towards a highly integrated single Chip technology, such as a Touch Embedded Display (TED) Chip scheme or a single Chip scheme (on Chip Solution, OCS), which are both development structures of the highly integrated Chip.

No matter the TED Chip scheme or the single Chip scheme, the package is small, the antistatic capability is weak, and the Chip is integrated inside a Chip On Glass (COG) Chip, the working position of the COG Chip is positioned at the edge of the display panel Glass, the positions do not have too strong electrostatic protection conditions, but the electrostatic protection is also a necessary condition for maintaining the normal work of the Chip, so how to solve the electrostatic protection is very important for the high integrated Chip.

Disclosure of Invention

The application discloses display panel can solve the technical problem of high integrated chip's electrostatic protection.

In a first aspect, the present application provides a display panel, the display panel includes a first circuit board, a second circuit board and a glass panel, the first circuit board is connected to the glass panel, one side of the glass panel adjacent to the first circuit board is provided with a chip circuit, the second circuit board includes a signal input end, the chip circuit is electrically connected to the signal input end through a first signal line for receiving a first signal, the chip circuit is further electrically connected to the signal input end through a second signal line for receiving a second signal, a first common ground wire is provided around the first signal line and the second signal line, a second common ground wire is provided on the second circuit board, the display panel further includes a connector circuit, and the first common ground wire is electrically connected to the second common ground wire through the connector circuit on the second circuit board.

Optionally, the connection sub-circuit includes at least one connection resistor, one end of the connection resistor is electrically connected to the first common ground line, the other end of the connection resistor is electrically connected to the second common ground line, and a resistance value of the connection resistor is 0 Ω.

Optionally, a plurality of conductive vias are further disposed on the first circuit board or the second circuit board, and at least two conductive vias located on the first circuit board or at least two conductive vias located on the second circuit board are used for receiving a same power supply voltage signal.

Optionally, the conductive through holes include a first through hole and a second through hole, a first conductive region is disposed around the first through hole, a second conductive region is disposed around the second through hole, and the first conductive region and the second conductive region are provided with a metal conductive material.

Optionally, the first conductive region and the second conductive region are at least partially disposed overlapping.

Optionally, the first circuit board includes a multi-layer sub circuit board, and the sub circuit board adjacent to the sub circuit board provided with the first signal line is further provided with the first common ground line.

Optionally, the display panel has a display area and a non-display area, the non-display area is surrounded by the display area, the first circuit board and the second circuit board are disposed in the non-display area, and the first circuit board is closer to the display area than the second circuit board.

Optionally, the chip circuit includes a first sub-circuit and a second sub-circuit, the first sub-circuit is a timing control chip, and the second sub-circuit is a data signal driving chip.

Optionally, the first signal is a display signal, and the second signal is an interactive communication signal.

In a second aspect, the present application further provides an electronic device, which includes a housing and the display panel as described in the first aspect, where the housing is used for bearing and mounting the display panel.

When the first signal line or the second signal line is interfered by static electricity, the first public ground wire is arranged around the first signal line and the second signal line, so that the static electricity can be transmitted to the second public ground wire through the first public ground wire via the connecting sub-circuit to be released, signal fluctuation and even damage to the lines are avoided, the technical problem of static protection of a high-integrated chip is solved, and the risk of poor display is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a partially enlarged schematic view of a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a connection sub-circuit according to an embodiment of the present disclosure.

Fig. 4 is a partially enlarged schematic view of a display panel according to another embodiment of the present application.

Fig. 5 is a partially enlarged schematic view of a display panel according to another embodiment of the present application.

Fig. 6 is a schematic diagram of a chip circuit framework according to an embodiment of the present disclosure.

Fig. 7 is a schematic top view of an electronic device according to an embodiment of the application.

The reference numbers illustrate: the display panel comprises a display panel-1, a first circuit board-11, a first signal line-111, a second signal line-112, a first common ground line-113, a second circuit board-12, a signal input end-121, a second common ground line-122, a glass panel-13, a chip circuit-131, a first sub-circuit-1311, a second sub-circuit-1312, a connecting sub-circuit-14, a connecting resistor-141, a conductive through hole-15, a first through hole-151, a second through hole-152, a first conductive area-153, a second conductive area-154, a display area-16, a non-display area-17, an electronic device-2 and a shell-21.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Fig. 1 and 2 are combined, and fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure; fig. 2 is a partially enlarged schematic view of a display panel according to an embodiment of the present disclosure. The display panel 1 comprises a first circuit board 11, a second circuit board 12 and a glass panel 13, the first circuit board 11 is connected with a chip circuit 131 through the glass panel 13, the glass panel 13 is provided with the chip circuit 131, the second circuit board 12 comprises a signal input end 121, the chip circuit 131 is electrically connected with the signal input end 121 through a first signal line 111 and used for receiving a first signal, the chip circuit 131 is further electrically connected with the signal input end 121 through a second signal line 112 and used for receiving a second signal, a first common ground line 113 is arranged around the first signal line 111 and the second signal line 112, a second common ground line 122 is arranged on the second circuit board 12, the display panel 1 further comprises a connector circuit 14, and the first common ground line 113 is electrically connected with the second common ground line 122 on the second circuit board 12 through the connector circuit 14.

The display panel 1 is used for displaying a picture, and in general, the display panel 1 includes a plurality of circuit boards electrically connected to each other to implement a function of displaying a picture. It should be understood that the first circuit board 11 and the second circuit board 12 are mainly related to the technical solution of the present application, and do not represent that the present application limits the number or the structure of the circuit boards. Next, in the present embodiment, the first Circuit Board 11 is used as a Flexible Printed Circuit (FPC) in the display panel 1, the second Circuit Board 12 is used as a main Circuit Board (PCB) in the display panel 1, and the glass panel 13 is used as a substrate on which display pixels are provided in the display panel 1.

Specifically, the chip circuit 131 may be a TED high-integration chip, and in the display panel 1, the TED chip is formed by integrally disposing a Timing Control (TCON) chip and a data signal driving (Source) chip in the same chip. The chip circuit 131 drives the pixels of the display panel 1 to operate according to the first signal and the second signal transmitted by the first signal line 111 and the second signal line 112, so as to realize the function of displaying the image. In other possible embodiments, when the size of the display panel 1 is larger, the number of pixels on the display panel 1 is increased accordingly. The number of the chip circuits 131 may be plural in order to drive a larger number of pixels on the display panel 1.

It can be understood that, because the chip circuit 131 integrates two signal processing chips, namely, a TCON chip and a Source chip, and the pin of the signal processing chip itself has a weak antistatic capability, the chip circuit 131 itself has a weak antistatic capability; meanwhile, the chip circuit 131 has high integration level and small package, so that the antistatic capability is weak; in addition, in general, the working environment of the chip circuit 131 is located at the edge of the glass panel 13, and the glass edge has less common ground, so the capability of discharging static electricity by common ground is weak.

It should be noted that, because the second circuit board 12 is used as the PCB of the display panel 1, a large-area common ground, that is, the second common ground 122, is usually disposed on the second circuit board 12, and the second common ground 122 is usually directly connected to the back plate of the display panel 1, and the back plate has a strong conductive capability, that is, the second common ground 122 has a strong capability of releasing static electricity.

Specifically, referring to fig. 2, in the present embodiment, the first common ground line 113 is disposed on upper and lower sides of the first signal line 111 or the second signal line 112 along an extending direction of the first signal line 111 or the second signal line 112. It is understood that, in other possible embodiments, the first common ground line 113 may also be disposed at other positions around the first signal line 111 or the second signal line 112, as long as the first common ground line 113 does not at least partially surround the first signal line 111 or the second signal line 112, which is not limited in this application.

It can be understood that, in this embodiment, when the first signal line 111 or the second signal line 112 is interfered by static electricity, since the first common ground line 113 is disposed around the first signal line 111 and the second signal line 112, the static electricity can be discharged through the first common ground line 113 and transmitted to the second common ground line 122 via the connection sub-circuit 14, thereby avoiding signal fluctuation and even damage to the lines, and thus solving the technical problem of electrostatic protection of high integrated chips and reducing the risk of poor display.

In one possible implementation, please refer to fig. 3, and fig. 3 is a schematic diagram of a connection sub-circuit according to an embodiment of the present disclosure. The connection sub-circuit 14 includes at least one connection resistor 141, one end of the connection resistor 141 is electrically connected to the first common ground line 113, and the other end is electrically connected to the second common ground line 122, and a resistance value of the connection resistor 141 is 0 Ω.

It should be noted that, since the second circuit board 12 is used as the PCB of the display panel 1, in the present embodiment, the second common ground line 122 is electrically connected to the ground directly, or the second common ground line 122 is used as a reference ground of 0 potential, static electricity is more easily introduced into and discharged from the second common ground line 122 relative to the first common ground line 113, and therefore, the first common ground line 113 and the second common ground line 122 need to be independently connected electrically.

It can be understood that, in the present embodiment, since the first common ground line 113 is electrically connected to the second common ground line 122 only through the connection sub-circuit 14, an electrical contact area between the first common ground line 113 and the second common ground line 122 is small, so that static electricity discharged from the second common ground line 122 is prevented or reduced from entering the first common ground line 113, and an influence of the static electricity on signal transmission of the first signal line 111 and the second signal line 112 is further reduced.

Specifically, as shown in fig. 3, the connection sub-circuit 14 may be the connection resistor 141, the first common ground line 113 is electrically connected to the second common ground line 122 through the connection resistor 141, and a resistance value of the connection resistor 141 is 0 Ω, so as to prevent the first common ground line 113 from becoming an island ground. By islanded is meant a ground that is not electrically connected to earth or a reference ground. When the first common ground line 113 becomes an island, there is a problem that static electricity cannot be discharged.

It is understood that, in other possible embodiments, the connection sub-circuit 14 may further include other electronic components, which is not limited in this application.

In one possible implementation manner, please refer to fig. 4, wherein fig. 4 is a partially enlarged schematic view of a display panel according to another implementation manner of the present application. The first circuit board 11 or the second circuit board 12 is further provided with a plurality of conductive through holes 15, and at least two conductive through holes 15 located on the first circuit board 11 or at least two conductive through holes 15 located on the second circuit board 12 are used for receiving the same power supply voltage signal.

It should be noted that the first circuit board 11 and the second circuit board 12 both include a plurality of circuits, and can normally operate only when a power voltage is supplied from the outside or from the inside. Typically, the number of conductive vias 15 for receiving the same supply voltage signal is one.

In the present embodiment, at least two of the conductive vias 15 are used for receiving the same power supply voltage signal, in other words, the present application increases the number of the conductive vias 15 used for receiving the power supply voltage signal. It can be understood that, increasing the number of the conductive vias 15 for receiving the same power voltage signal is equivalent to increasing the current flowing capability of the conductive vias 15, that is, the conductive vias 15 can bear larger current when the same power voltage signal is applied to the conductive vias 15.

Because the circuit is directly and electrically connected with the conductive through holes 15, the number of the conductive through holes 15 used for receiving the same power supply voltage signal is increased, the bearing capacity of the whole circuit can be effectively improved, meanwhile, the circulation capacity when static is led into the circuit is enhanced, and the circuit is prevented from being damaged by static current.

It is understood that in other possible embodiments, the number of the conductive vias 15 for receiving the same power voltage signal may also be 3, 4, 5, etc., which is not limited in this application.

In one possible embodiment, referring to fig. 4 again, the conductive via 15 includes a first via 151 and a second via 152, a first conductive region 153 is disposed around the first via 151, a second conductive region 154 is disposed around the second via 152, and the first conductive region 153 and the second conductive region 154 are disposed with a metal conductive material.

Specifically, the metal conductive material has a property of storing charges, and when affected by static electricity, since the first conductive region 153 and the second conductive region 154 are provided with the metal conductive material, static charges can be temporarily stored in the metal conductive material of the first conductive region 153 and the second conductive region 154, thereby further enhancing the antistatic capability.

As shown in fig. 4, the first conductive area 153 and the second conductive area 154 are circular, and it is understood that in other possible embodiments, the first conductive area 153 and the second conductive area 154 may also be other shapes or irregular shapes, as long as the metal conductive material is not laid in the empty area around the first through hole 151 and the second through hole 152, which is not limited in this application.

In this embodiment, a metal conductive material is formed by copper and is disposed on the first conductive region 153 and the second conductive region 154. It is understood that in other possible embodiments, other metal conductive materials may be used, and the present application is not limited thereto.

In one possible embodiment, referring again to fig. 4, the first conductive region 153 is at least partially overlapped with the second conductive region 154.

Specifically, when the first conductive area 153 and the second conductive area 154 are provided with a metal conductive material, the first conductive area 153 and the second conductive area 154 are at least partially overlapped, so that the first through hole 151 and the second through hole 152 are electrically connected together, thereby further enhancing the carrying capacity of the conductive through hole 15.

It can be understood that, in the present embodiment, when affected by static electricity, charges stored in the metal conductive material of the first conductive region 153 and the metal conductive material of the second conductive region 154 can be transferred and balanced with each other, so as to improve the antistatic capability of the conductive via 15. It is understood that, in other possible embodiments, the first conductive area 153 and the second conductive area 154 may not be overlapped, and the application is not limited thereto.

In a possible implementation manner, please refer to fig. 5, wherein fig. 5 is a partially enlarged schematic view of a display panel according to another implementation manner of the present application. The first circuit board 11 includes a plurality of sub circuit boards, and the first common ground line 113 is further disposed on a sub circuit board adjacent to the sub circuit board on which the first signal line 111 is disposed.

Specifically, for a clearer view, the first signal line 111 is shown in fig. 5 in a dotted line form. In addition to disposing the first common ground line 113 around the first signal line 111 and the second signal line 112, the first common ground line 113 may be disposed on a sub-circuit board adjacent to the sub-circuit board on which the first signal line 111 is disposed, thereby increasing a coverage area of the first common ground line 113, so that the first common ground line 113 has a stronger ability to discharge static electricity.

Meanwhile, the first common ground line 113 is disposed on the sub circuit board adjacent to the sub circuit board on which the first signal line 111 is disposed, so that static electricity is transmitted to the second common ground line 122 through the adjacent sub circuit board and is discharged, thereby avoiding interference or damage to the first signal line 111 during the static electricity discharging process.

It is understood that, in other possible embodiments, the first common ground line 113 is also disposed on a sub circuit board adjacent to the sub circuit board on which the second signal line 112 is disposed, and the application is not limited thereto.

In one possible implementation, please refer to fig. 1 again, the display panel 1 has a display area 16 and a non-display area 17, the non-display area 17 is surrounded on the display area 16, the first circuit board 11 and the second circuit board 12 are disposed on the non-display area 17, and the first circuit board 11 is closer to the display area 16 than the second circuit board 12.

Specifically, the display area 16 refers to an area of the display panel 1 for displaying images, videos, and the like, pixels of the display panel 1 are usually disposed in the display area 16, and the first circuit board 11 and the second circuit board 12 are disposed in the non-display area 17 in order to avoid the first circuit board 11 and the second circuit board 12 from affecting a display screen.

In the prior art, in consideration of the beauty and the practicability, the requirement for reducing the occupation ratio of the non-display area 17 is increasing, and because the first circuit board 11 is disposed at a position adjacent to the display area 16 and clamped between the display area 16 and the second circuit board 12, the public ground resources on the first circuit board 11 are less, and the antistatic capability is weaker.

It can be understood that, in the present embodiment, since the first common ground line 113 is disposed around the first signal line 111 and the second signal line 112, static electricity can be discharged through the first common ground line 113 and transmitted to the second common ground line 122 via the connection sub-circuit 14, thereby avoiding signal fluctuation and even damage to the lines.

In one possible implementation, please refer to fig. 6, in which fig. 6 is a schematic diagram of a chip circuit framework according to an embodiment of the present disclosure. The chip circuit 131 includes a first sub-circuit 1311 and a second sub-circuit 1312, the first sub-circuit 1311 is a timing control chip, and the second sub-circuit 1312 is a data signal driving chip.

Specifically, when the chip circuit 131 is applied to the display panel 1, the chip circuit includes the first sub-circuit 1311 and the second sub-circuit 1312, that is, the chip circuit 131 is a TED high integrated chip. For the related description of the high-integration chip, please refer to the above description, which is not repeated herein.

In this embodiment, the first sub-circuit 1311 controls the second sub-circuit 1312 to generate a data signal according to the first signal and the second signal, thereby driving the pixels on the display panel 1 to operate and displaying a screen. Because the first common ground line 113 is disposed around the first signal line 111 and the second signal line 112, static electricity can be transmitted to the second common ground line 122 through the first common ground line 113 via the connection sub-circuit 14 and released, thereby preventing signal fluctuation and even damage to the lines, so that the signal quality of the first signal and the second signal received by the first sub-circuit 1311 is improved, and the second sub-circuit 1312 can better drive the pixels on the display panel 1 to normally operate, thereby avoiding problems such as stroboscopic display, errors and the like.

It is understood that, in other possible embodiments, the chip circuit 131 may further include other sub-circuits, which is not limited in this application, for example, the chip circuit 131 may further include a scan signal driving (Gate) chip, that is, a TCON chip, a Source chip, and a Gate chip are integrated in the same chip, in this case, the chip circuit 131 is an OCS chip.

It can be understood that when the chip circuit 131 is a high-integration chip, compared to the chip-separated scheme, the amount of chip usage and peripheral circuits can be greatly reduced, the cost can be reduced, and the management difficulty of the chip supply chain can be simplified.

In one possible embodiment, the first signal is an indication signal (EDP Main Link) and the second signal is an interactive communication signal (AUX).

Specifically, the display signal refers to a signal carrying various types of video data information and audio data information; by interactive communication signals are meant signals carrying data with low bandwidth requirements as well as link management and device control. It can be understood that the first signal and the second signal are important signals for the display panel 1 to realize a function of displaying an image, and when the first signal line 111 or the second signal line 112 is subjected to electrostatic interference, the first signal or the second signal may be distorted, so that problems such as stroboflash and errors of the displayed image may occur.

Therefore, in this embodiment, by disposing the first common ground line 113 around the first signal line 111 and the second signal line 112, static electricity can be discharged through the first common ground line 113 and transmitted to the second common ground line 122 via the connection sub-circuit 14, thereby avoiding causing signal fluctuation or even damaging the lines, and improving the signal quality of the first signal and the second signal received by the first sub-circuit 1311.

It is understood that, in other possible embodiments, the first common ground may also be disposed around a signal line for transmitting other types of signals, such as a hot plug detect line (HDP) or the like, which is not limited in this application.

It is understood that, in other possible embodiments, the application may also improve the antistatic capability of the first signal line 111 and the second signal line 112 by reasonably designing the electrical connection relationship of a diode, a resistor or a capacitor around the first signal line 111 and the second signal line 112, which is not limited in this application.

Fig. 7 is a schematic top view of an electronic device 2 according to an embodiment of the present disclosure, and fig. 7 is a schematic top view of the electronic device 2. The electronic device 2 comprises a housing 21 and the display panel 1 as described above, wherein the housing 21 is used for bearing and mounting the display panel 1. Specifically, please refer to the above description for the display panel 1, which is not described herein again.

It should be noted that, in the embodiment of the present invention, the electronic device 2 may be a mobile phone, a smart phone, a tablet computer, an electronic reader, a wearable portable device, a notebook computer, and the like, and may communicate with a data transfer server through the internet, and the data transfer server may be an instant messaging server, an SNS (Social Networking Services) server, and the like, which is not limited in this embodiment of the present invention.

The principle and the embodiment of the present application are explained herein by applying specific examples, and the above description of the embodiment is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A display panel is characterized by comprising a first circuit board, a second circuit board and a glass panel, wherein the first circuit board is connected with the glass panel, a chip circuit is arranged on one side, close to the first circuit board, of the glass panel, the working environment of the chip circuit is located on the edge of the glass panel, the second circuit board comprises a signal input end, the chip circuit is electrically connected with the signal input end through a first signal line and used for receiving a first signal, the chip circuit is further electrically connected with the signal input end through a second signal line and used for receiving a second signal, a first public ground wire is arranged around the first signal line and the second signal line, a second public ground wire is arranged on the second circuit board, the display panel further comprises a connector circuit, the first public ground wire is electrically connected with the second public ground wire on the second circuit board through the connector circuit, and the capacity of the second public ground wire for releasing static electricity is stronger than the capacity of the first public ground wire for releasing static electricity.

2. The display panel according to claim 1, wherein the connection sub-circuit includes at least one connection resistor having one end electrically connected to the first common ground line and the other end electrically connected to the second common ground line, and a resistance value of the connection resistor is 0 Ω.

3. The display panel of claim 1, wherein the first circuit board or the second circuit board further has a plurality of conductive vias, at least two of the conductive vias on the first circuit board or at least two of the conductive vias on the second circuit board being configured to receive a same supply voltage signal.

4. The display panel according to claim 3, wherein the conductive via holes include a first via hole and a second via hole, a first conductive region is disposed around the first via hole, a second conductive region is disposed around the second via hole, and a metal conductive material is disposed on the first conductive region and the second conductive region.

5. The display panel of claim 4, wherein the first conductive region and the second conductive region are at least partially disposed to overlap.

6. The display panel of claim 1, wherein the first circuit board comprises a multi-layer sub circuit board, and the first common ground line is further disposed on a sub circuit board adjacent to the sub circuit board on which the first signal line is disposed.

7. The display panel according to claim 1, wherein the display panel has a display area and a non-display area, the non-display area is surrounded by the display area, the first circuit board and the second circuit board are disposed in the non-display area, and the first circuit board is closer to the display area than the second circuit board.

8. The display panel of claim 1, wherein the chip circuit comprises a first sub-circuit and a second sub-circuit, the first sub-circuit is a timing control chip, and the second sub-circuit is a data signal driving chip.

9. The display panel of claim 1, wherein the first signal is a display signal and the second signal is an interactive communication signal.

10. An electronic device, comprising a housing and a display panel according to any one of claims 1-9, wherein the housing is configured to carry and mount the display panel.