CN108983520B - Display panel with anti-electrostatic discharge - Google Patents
Display panel with anti-electrostatic discharge Download PDFInfo
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- CN108983520B CN108983520B CN201811146394.6A CN201811146394A CN108983520B CN 108983520 B CN108983520 B CN 108983520B CN 201811146394 A CN201811146394 A CN 201811146394A CN 108983520 B CN108983520 B CN 108983520B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
Abstract
The invention provides an anti-static discharge display panel which has the advantages that a first grounding wire avoids a large-area fan-out area of a first metal layer, the generation of static discharge when the static electricity generated in a product is large in a reliability test is avoided, the first grounding wire is further prevented from being in short circuit with the fan-out line group of the first metal layer, and the anti-static discharge capacity of the display panel can be improved.
Description
Technical Field
The invention relates to the field of liquid crystal display, in particular to an anti-static discharge display panel.
Background
The generation of static electricity is inevitable in industrial production and causes serious damage. For example, in the electronic industry, static electricity mainly causes failures or malfunctions of electronic devices in the form of electrostatic discharge (ESD), which causes electromagnetic interference and unstable operation of electronic products, breaks down integrated circuits and precise electronic components, or promotes aging of electronic components, thereby reducing production yield.
In the product design of Liquid Crystal Display (LCD), the protection design for electrostatic discharge is often used in which the outermost periphery of the display panel is connected to the Ground (GND) of the driver chip (IC) through the ground of the flexible printed circuit board, which serves to shield external charges and protect the internal structure of the display panel. Specifically, fig. 1 is a schematic top view of a conventional LCD panel electrostatic discharge protection design, and fig. 2 is an enlarged schematic view of a portion a in fig. 1. Referring to fig. 1 and 2, the lcd panel includes a Thin Film Transistor (TFT) substrate 10 and a color filter substrate (CF)20 disposed above the TFT substrate 10. The structure of the thin film transistor substrate 10 shielded by the color film substrate 20 is schematically illustrated by a dotted line. In the liquid crystal display panel, a circle of second grounding wire 11 is designed on the periphery of the thin film transistor substrate 10, and is connected to a grounding bonding Pad (FPC GND Pad)12 after the SD process is finished, wherein the grounding bonding Pad is connected with the grounding bonding Pad of the flexible circuit board and is used for blocking or conducting away static electricity on the thin film transistor substrate 10 side; the side of the color film substrate 20 is not provided with a metal circuit, so that grounding wiring cannot be performed, in order to conduct away static electricity on the side of the color film substrate during subsequent manufacturing processes or product ESD tests, a silver paste conductive point 21 is formed on the side of the thin film transistor substrate 10, the side of the color film substrate 20 is connected to a first grounding wire 13 on the side of the thin film transistor substrate 10 through the silver paste conductive point 21, and the first grounding wire 13 is connected to the grounding bonding pad 12, so that the static electricity on the side of the color film substrate 20 is conducted away.
The disadvantage of the above method is that, referring to fig. 2, on the tft substrate 10, fan-out lines 14 (shown by dotted lines in the drawing because the fan-out line group 14 of the first metal layer is shielded by the passivation layer) of a first metal layer of the tft substrate 10 are concentrated to form a fan-out region C and connected to a first metal layer pad 15, and the first metal layer pad 15 is connected to a signal line pad of the flexible circuit board. The first ground line 13 belongs to a second metal layer, and it needs to cross the fan-out region C to be connected to the ground pad 12. The bottom of the first ground line 13 has a large area of the fan-out line 14 of the first metal layer, and the fan-out line 14 of the first metal layer and the first ground line 13 are isolated only by a passivation layer (ILD) (not shown in the drawing), so that ESD is likely to occur when a product is subjected to a reliability test and generates a large static electricity, which results in a short circuit between the first ground line 13 and the fan-out line 14 of the first metal layer. Since the fan-out lines 14 of the first metal layer are respectively connected to signal lines such as TP/CT/DMUX/CK/GAS/VGL of the flexible circuit board, ESD may cause short-circuit of the signal lines, thereby causing abnormal display of the display panel.
Disclosure of Invention
The present invention is directed to an anti-esd display panel, which can reduce esd.
In order to solve the above problems, the present invention provides a display panel for reducing electrostatic discharge, including a first substrate and a second substrate, where the first substrate and the second substrate are disposed opposite to each other, the first substrate includes at least one first metal layer fan-out line group, at least one first metal layer bonding pad group, at least one conductive bump, at least one first ground line and at least one first ground pad, the first metal layer fan-out line group is connected to the first metal layer bonding pad group, the conductive bump is connected to a metal wire of the second substrate, one end of the first ground line is connected to the conductive bump, and the other end of the first ground line is connected to the first ground pad by bypassing one side of the first metal layer bonding pad group not connected to the first metal layer fan-out line group.
In one embodiment, the first metal layer pad set is disposed between the conductive bump and the first ground pad.
In an embodiment, the first substrate includes two fan-out line sets of the first metal layer, two bonding pads of the first metal layer, two conductive bumps, two first ground lines, and two first ground pads, which are symmetrically disposed.
In an embodiment, an edge of the first substrate protrudes out of an edge of the second substrate to form a frame region, and the first metal layer fan-out line group, the first metal layer pad group, the conductive bump, the first ground line and the first ground pad are disposed in the frame region.
In one embodiment, the first substrate further includes a substrate ground line disposed at a periphery of the first substrate, at least one second ground line, and at least one second ground pad, the substrate ground line being connected to the second ground pad through the second ground line.
In an embodiment, the first substrate includes two second ground lines and two second ground pads, the two second ground lines are symmetrically disposed around the first substrate, and two ends of the substrate ground line are respectively connected to one of the second ground lines.
In one embodiment, one end of the second ground line is connected to the substrate ground line, and the other end of the second ground line is connected to the second ground pad by bypassing the side of the first metal layer pad set not connected to the first metal layer fan-out line set.
In one embodiment, one end of the second ground line is connected to the substrate ground line, the other end of the second ground line passes through the connection point of the first metal layer fan-out line group and the first metal layer bonding pad group to be connected to the second ground bonding pad, and an insulating isolation layer is arranged between the second ground line and the first metal layer fan-out line group.
In an embodiment, the first substrate further includes at least one second metal layer fan-out line set, and an insulating isolation layer is disposed between the second metal layer fan-out line set and the first metal layer fan-out line set.
In an embodiment, the first substrate is a thin film transistor substrate, and the second substrate is a color filter substrate.
The invention has the advantages that the first grounding wire avoids the fan-out area of the first metal layer with large area, thereby avoiding the generation of electrostatic discharge when the product is subjected to reliability test to generate larger static electricity, further avoiding the short circuit of the first grounding wire and the fan-out line group of the first metal layer, and improving the antistatic discharge capability of the display panel.
Drawings
FIG. 1 is a schematic top view of a prior art LCD panel ESD design;
FIG. 2 is an enlarged schematic view of portion A of FIG. 1;
FIG. 3 is a schematic top view of a display panel with reduced ESD according to the present invention;
fig. 4 is an enlarged schematic view of a portion B in fig. 3.
Detailed Description
The following describes in detail a specific embodiment of the display panel with reduced electrostatic discharge according to the present invention with reference to the accompanying drawings.
Fig. 3 is a schematic top view of the display panel with anti-electrostatic discharge function according to the present invention, and fig. 4 is an enlarged schematic view of a portion B in fig. 3. Referring to fig. 3 and 4, the display panel for reducing electrostatic discharge according to the present invention includes a first substrate 30 and a second substrate 40. In this embodiment, the first substrate 30 is a thin film transistor substrate, i.e., a TFT substrate, and the second substrate 40 is a color filter substrate, i.e., a CF substrate. The first substrate 30 is disposed opposite to the second substrate 40, and the first substrate 30 is disposed below the second substrate 40 in fig. 3. In order to clearly illustrate the technical solution of the present invention, in the drawings, a portion of the structure related to the present invention, which is shielded by the second substrate 40, is illustrated by a dotted line, for example, a portion of the substrate ground line 36 of the second substrate 30, which is shielded by the second substrate 40, is illustrated by a dotted line, and the size of each component is exaggerated appropriately. In this embodiment, the first substrate 30 is a thin film transistor substrate (TFT substrate), and the second substrate 40 is a color filter substrate (CF substrate).
The first substrate 30 includes at least one first metal layer fan-out line group 31, at least one first metal layer pad group 32, at least one conductive bump 33, at least one first ground line 34, and at least one first ground pad 35, and the first metal layer fan-out line group 31 is shielded by an insulating isolation layer, so the dashed line is shown in the drawing). An edge of the first substrate 30 protrudes out of the second substrate 40 to form a frame region S, and the first metal layer fan-out line group 31, the first metal layer pad group 32, the conductive bump 33, the first ground line 34, and the first ground pad 35 are disposed in the frame region S. For example, in the present embodiment, the lower edge of the first substrate 30 protrudes from the lower edge of the second substrate 40 to form a frame region S, i.e., a lower frame region, and the first metal layer fan-out line group 31, the first metal layer pad group 32, the conductive bump 33, the first ground line 34, and the first ground pad 35 are disposed in the lower frame region. In other embodiments, the side edge of the first substrate 30 protrudes out of the side edge of the second substrate 40 to form a frame region S, i.e. a side frame region, and the first metal layer fan-out line group 31, the first metal layer pad group 32, the conductive bump 33, the first ground line 34, and the first ground pad 35 are disposed in the frame region.
The first metal layer fan-out line group 31 is used for fanning out metal lines belonging to a first metal layer, such as scan lines (not shown in the drawings) of the first substrate 30, one end of the first metal layer fan-out line group 31 is connected with the metal lines of the first metal layer, and the other end of the first metal layer fan-out line group 31 is connected with the first metal layer pad group 32. In the manufacturing process of the display panel, the first metal layer fan-out line group 31 and the metal lines of the first metal layer are manufactured at the same time, and belong to the first metal layer. The first metal layer fan-out line set 31 includes a plurality of first metal layer fan-out lines 311, and fig. 4 only schematically illustrates five first metal layer fan-out lines 311, in an actual structure of the display panel, the number of the first metal layer fan-out lines 311 included in the first metal layer fan-out line set 31 is not limited to five, and it needs to be determined according to actual requirements of the first substrate 30. The area where the first metal layer fan-out line group 31 is located is defined as a fan-out area C.
The first metal layer pad group 32 is located at one side of the fan-out region C. Specifically, the first metal layer pad group 32 is located on a side of the fan-out region C facing away from the center of the first substrate 30. For example, in this embodiment, the frame region S is a lower frame region, and the first metal layer pad group 32 is located below the fan-out region C. The first metal layer pad set 32 includes a plurality of first metal layer pads 321, and only five first metal layer pads 321 are schematically illustrated in fig. 4. The first metal layer pads 321 of the first metal layer pad set 32 include but are not limited to providing signals such as TP/CT/DMUX/CK/GAS/VGL. In the display panel, a flexible wiring board having an IC chip may be soldered to the first metal layer pad group 32 to connect the first metal layer to the IC chip.
The conductive bumps 33 are connected to the metal traces of the second substrate 40. Specifically, the conductive bump 33 extends to the second substrate 40, and a metal trace of the second substrate 40 that needs to be grounded is connected to the conductive bump 33. The conductive bumps 33 include, but are not limited to, silver paste conductive bumps.
One end of the first ground line 34 is connected to the conductive bump 33, and the other end of the first ground line 34 is connected to the first ground pad 35 by bypassing the side of the first metal layer pad group 321 not connected to the first metal layer fan-out line group 31. Specifically, on the surface of the first substrate 30, one end of the first ground line 34 is connected to the bottom of the conductive bump 33, and the other end of the first ground line 34 extends around the side of the first metal layer pad group 321 not connected to the first metal layer fan-out line group 31 and then is connected to the first ground pad 35. For example, in this embodiment, one end of the first ground line 34 is connected to the bottom of the conductive bump 33, and the other end of the first ground line 34 extends around the lower end of the first metal layer pad group 321 and then is connected to the first ground pad 35.
The static electricity of the second substrate 40 can be conducted to the first ground pad 35 through the conductive bump 33 and the first ground line 34, and the first ground pad 35 is soldered to the ground terminal of the flexible printed circuit board, so as to conduct the static electricity of the second substrate 40. The other end of the first grounding wire 34 extends to bypass the first metal layer pad group 321 and the first grounding pad 35 after the side where the first metal layer fan-out line group 31 is not connected, so that the advantage that the first grounding wire 34 avoids the fan-out area C of the large-area first metal layer is avoided, the occurrence of electrostatic discharge when the product is subjected to reliability test to generate static electricity is large is avoided, the first grounding wire 34 is further avoided from being short-circuited with the first metal layer fan-out line group 31, and the antistatic discharge capability of the display panel can be improved.
In this embodiment, the first metal layer pad group 32 is disposed between the conductive bump 33 and the first ground pad 35. Specifically, the conductive bump 33 is disposed at an edge of the frame region S, the first ground pad 35 may be disposed at a middle portion of the frame region S, and the first metal layer pad group 32 is disposed therebetween. The first ground line 34 needs to bypass the first metal layer pad group 32 if it is connected to the first ground pad 35. Further, the first substrate 30 includes two first metal layer fan-out line groups 31, two first metal layer pad groups 32, two conductive bumps 33, two first ground lines 34, and two first ground pads 35, which are symmetrically disposed. For example, in the present embodiment, two first metal layer fan-out line groups 31, two first metal layer pad groups 32, two conductive bumps 33, two first ground lines 34, and two first ground pads 35 are symmetrically distributed along a center line of the first substrate 30.
The first substrate 30 further includes a substrate ground line 36 disposed at the periphery of the first substrate 30, at least one second ground line 37, and at least one second ground pad 38. The substrate ground line 36 is connected to the second ground pad 38 through the second ground line 37. The substrate ground line 36 is used for conducting the static electricity of the first substrate 30 to the second ground pad 38 through the second ground line 37, and the second ground pad 38 is welded to the ground terminal of the flexible printed circuit board, so as to conduct the static electricity of the first substrate 30.
Alternatively, one end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 is connected to the second ground pad 38 after bypassing one side of the first metal layer pad group 32 that is not connected to the first metal layer fan-out line group 31. For example, one end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 is connected to the second ground pad 38 after bypassing the lower end of the first metal layer pad group 32. The advantage is that the second ground line 37 avoids the fan-out region C of the first metal layer with a large area, thereby avoiding the occurrence of electrostatic discharge when the product is subjected to reliability test and generates large static electricity, further avoiding the short circuit between the second ground line 37 and the fan-out line group 31 of the first metal layer, and improving the capability of the display panel for resisting ESD.
Optionally, in this embodiment, the first substrate 30 includes two second ground lines 37 and two second ground pads 38, which are symmetrically disposed. The substrate ground line 36 is disposed around the first substrate 30, and both ends of the substrate ground line 36 are connected to one of the second ground lines 37, respectively. One end of the second ground line 37 is connected to the substrate ground line 36, and the other end of the second ground line 37 passes through the connection point (i.e., the fan-out region C) between the first metal layer pad group 32 and the first metal layer fan-out line group 31 and then is connected to the second ground pad 38. In the present embodiment, since the substrate ground line 36 is disposed around the first substrate 30 so that the first substrate 30 has a stronger ESD resistance than the second substrate 40, the second ground line 37 may not cause electrostatic discharge even if the other end thereof passes through the fan-out region C. An insulating isolation layer (not shown in the drawings) is disposed between the second ground line 37 and the first metal layer fan-out line set 31, and the insulating isolation layer can prevent the second ground line 37 from being conducted with the first metal layer fan-out line set 31.
Further, the first substrate 30 further includes at least one second metal layer fan-out line group 39. One end of the second metal layer fan-out line group 39 is connected to a metal line (not shown) of a second metal layer, such as a data line of the first substrate 30, and the other end is connected to a second metal layer pad group 50 of the frame region S. In the display panel, a flexible wiring board having an IC chip may be soldered to the second metal layer pad set 50 to connect the second metal layer to the IC chip. The second metal layer fan-out line group 39 includes a plurality of second metal layer fanout lines 391, and only two second metal layer fanout lines 391 are schematically illustrated in fig. 4. The first substrate 30 may include two symmetrically arranged second metal layer fan-out line groups 39, and correspondingly, the first substrate 30 includes two symmetrically arranged second metal layer pad groups 50.
An insulating isolation layer (not shown in the drawings) is also arranged between the second metal layer fan-out line group 39 and the first metal layer fan-out line group 31, and the insulating isolation layer can prevent the second metal layer fan-out line group 39 from being conducted with the first metal layer fan-out line group 31.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. The display panel is characterized by comprising a first substrate and a second substrate, wherein the first substrate and the second substrate are arranged oppositely, the first substrate comprises at least one first metal layer fan-out line group, at least one first metal layer welding pad group, at least one conductive bump, at least one first grounding wire and at least one first grounding welding pad, the first metal layer fan-out line group is connected with the first metal layer welding pad group, the conductive bump is connected with a metal wire of the second substrate, one end of the first grounding wire is connected with the conductive bump, and the other end of the first grounding wire bypasses the side, which is not connected with the first metal layer fan-out line group, of the first metal layer welding pad group and is connected with the first grounding welding pad; the first substrate further comprises a substrate grounding wire arranged on the periphery of the first substrate, at least one second grounding wire and at least one second grounding welding pad, the substrate grounding wire is connected to the second grounding welding pad through the second grounding wire, and one end of the second grounding wire is connected with the substrate grounding wire; the other end of the second grounding wire bypasses the side, which is not connected with the first metal layer fan-out wire group, of the first metal layer welding pad group and is connected with the second grounding welding pad; or the other end of the second grounding wire penetrates through the joint of the first metal layer fan-out line group and the first metal layer welding pad group to be connected with the second grounding welding pad, and an insulating isolation layer is arranged between the second grounding wire and the first metal layer fan-out line group.
2. The anti-electrostatic discharge display panel of claim 1, wherein the first metal layer pad set is disposed between the conductive bump and the first ground pad.
3. The anti-electrostatic discharge display panel of claim 1, wherein the first substrate comprises two fan-out line sets of the first metal layer, two bonding pads of the first metal layer, two conductive bumps, two first ground lines, and two first ground pads, which are symmetrically disposed.
4. The anti-ESD display panel according to claim 1, wherein an edge of the first substrate protrudes out of an edge of the second substrate to form a frame region, and the first metal layer fan-out line set, the first metal layer pad set, the conductive bump, the first ground line and the first ground pad are disposed in the frame region.
5. The anti-electrostatic discharge display panel according to claim 4, wherein the first substrate includes two second ground lines and two second ground pads, the two second ground lines are symmetrically disposed around the first substrate, and two ends of the two second ground lines are respectively connected to one second ground line.
6. The anti-electrostatic discharge display panel of claim 1, wherein the first substrate further comprises at least a second metal layer fan-out line set, and an insulating isolation layer is arranged between the second metal layer fan-out line set and the first metal layer fan-out line set.
7. The antistatic display panel of claim 1, wherein the first substrate is a thin film transistor substrate and the second substrate is a color film substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811146394.6A CN108983520B (en) | 2018-09-29 | 2018-09-29 | Display panel with anti-electrostatic discharge |
| PCT/CN2018/117896 WO2020062535A1 (en) | 2018-09-29 | 2018-11-28 | Electrostatic discharge resistant display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811146394.6A CN108983520B (en) | 2018-09-29 | 2018-09-29 | Display panel with anti-electrostatic discharge |
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| CN108983520A CN108983520A (en) | 2018-12-11 |
| CN108983520B true CN108983520B (en) | 2021-04-02 |
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| CN201811146394.6A Active CN108983520B (en) | 2018-09-29 | 2018-09-29 | Display panel with anti-electrostatic discharge |
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| WO (1) | WO2020062535A1 (en) |
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| CN114501967B (en) * | 2022-01-20 | 2023-03-24 | 绵阳惠科光电科技有限公司 | Display panel and electronic device |
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| JP2006030627A (en) * | 2004-07-16 | 2006-02-02 | Sharp Corp | Substrate for display device, and liquid crystal display device using the same |
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| KR101577667B1 (en) * | 2014-05-27 | 2015-12-16 | 엘지디스플레이 주식회사 | Liquid crystal display panel and liquid crystal display device |
| CN104216165A (en) * | 2014-09-09 | 2014-12-17 | 合肥京东方光电科技有限公司 | Color film base plate and liquid crystal display device |
| CN205665677U (en) * | 2016-05-12 | 2016-10-26 | 厦门天马微电子有限公司 | Display panel |
| CN107219660B (en) * | 2017-07-12 | 2020-09-25 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
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| CN101630078A (en) * | 2008-07-17 | 2010-01-20 | 胜华科技股份有限公司 | Liquid crystal display panel |
| CN103296021A (en) * | 2012-06-29 | 2013-09-11 | 上海天马微电子有限公司 | TFT array substrate |
| CN104035217A (en) * | 2014-05-21 | 2014-09-10 | 深圳市华星光电技术有限公司 | Peripheral test circuit of displayer array substrate and LCD panel |
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| Publication number | Publication date |
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| WO2020062535A1 (en) | 2020-04-02 |
| CN108983520A (en) | 2018-12-11 |
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