WO2020107734A1

WO2020107734A1 - Display panel and display device

Info

Publication number: WO2020107734A1
Application number: PCT/CN2019/076909
Authority: WO
Inventors: 柴立
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2018-11-29
Filing date: 2019-03-05
Publication date: 2020-06-04

Abstract

The present invention provides a display panel and a display device thereof. The display panel comprises a display region and a sealant region, the sealant region being surrounded by two sealant edge lines. Common signal lines of a color filter substrate are provided on the sealant region and a panel cutting line; a plurality of clock signal lines are further provided in the sealant region, the clock signal lines being distributed in parallel to the sealant region surrounded by the sealant lines, and being used to connect signal lines in the display region; the signal lines are perpendicular to the clock signal lines, and are distributed in parallel, and each signal line is connected to a corresponding clock signal line. The present invention shields electric arc during an ESD test, preventing electrostatic arc from damaging the clock signal lines in the inner sealant region.

Description

Display panel and display device

Technical field

The invention relates to the field of liquid crystal display, in particular to a method for preparing a black matrix and a display device.

Background technique

With the development of the information society, people's demand for display devices has increased, which has also promoted the rapid development of the LCD panel industry. Customers' requirements and tastes for LCD TVs are getting higher and higher, and the methods of panel reliability testing are becoming more and more demanding.

It is known that as shown in Fig. 1, the array substrate or the LCD panel module will perform ESD (Electro-Static discharge) before shipment. test) test, that is, electrostatic discharge test, to evaluate its anti-static performance. As shown in FIG. 1, it is an electrostatic strike point 13 on the test panel frame 11 that is discharged by a high-voltage electrostatic gun discharge, and the electrostatic resistance of the test panel is evaluated according to the breakdown result.

Further, because of cost considerations, the current GOA (chip on array) products are becoming more and more extensive, and GOA products are relatively weak against static electricity. Therefore, most of the frames will use metal materials to guide the static electricity away, and will not damage the panel. If the frame 11 uses a non-conductive plastic frame, static electricity will be conducted into the display panel, resulting in damage to the GOA area of the display panel and abnormal screen appearance. Especially for GOA display panels with narrow bezels, the frame glue will overlap with the GOA clock signal line. When an ESD test is performed with a high-voltage electrostatic gun to hit the test point on the frame, an electrostatic arc will be induced into the panel. The probability is very high, resulting in an abnormal display on the panel.

As shown in Figure 2, it illustrates a GOA-type display panel common in the industry. Among them, 21 is the edge of the panel (cutting line), 22 is the edge of the frame glue, 23~28 are the GOA CK signal lines, 29 are the common signal lines of the color film substrate, and 30 is the via ITO that is easily damaged by electrostatic arcs during ESD testing.

Among them, the GOA type display panel currently common in the industry, the order of the GOA side peripheral traces from in-plane to out-of-plane is: VSSG-VSSQ-LC1-LC2 -CK1-CK2-CK3-CK4-CK5-CK6-CF COM, except that CF COM does not need to lead into the surface on the GOA side (no hole lead is required), other signal lines need hole lead to the surface, via The upper surface is covered with ITO conductive film, and the upper CF substrate is the entire surface of the ITO conductive film, so during the ESD test, the electrostatic arc will be directly directed to the ITO of the upper CF substrate, because the thickness of the liquid crystal cell is generally 3.0um~3.8um Left and right, so the arc can easily damage the ITO from the upper plate ITO across the intermediate medium to the array substrate side, which will lead to abnormal conduction of the vias on the array substrate, so the clock signal cannot be transmitted normally in the surface, resulting in abnormal screen .

For example, as shown in FIGS. 3-4, it illustrates a schematic diagram of the state of the display panel to be tested when performing ESD testing. 31 is the array substrate, 32 is the ITO film on the GOA clock signal trace, 33 is the CF substrate, 34 is the ITO film, 35 is the frame glue, 36 is the module frame, 37 is the ESD electrostatic gun discharge, which will cause the release The current is conducted through the upper plate ITO and then damages the ITO film on the CK signal line of the array substrate.

Therefore, it is indeed necessary to develop a new type of display panel to overcome the defects in the prior art.

technical problem

An object of the present invention is to provide a display panel, which can effectively solve the problem that the static arc damages the clock signal wiring during the ESD process.

Technical solution

The object of the present invention is to provide a method for preparing a black matrix, which can remove the steps of the dry etching process of the intermediate layer.

In order to solve the above technical problems, the present invention provides a display panel including a display area, a plastic frame area and an edge area connected in sequence, wherein a common signal line of a color filter substrate is provided on the edge area, wherein the color filter substrate is common The signal line includes a first metal trace, an insulating layer, a second metal trace, a passivation layer, a flat layer and an ITO layer arranged in sequence; wherein the flat layer is recessed downward through the passivation layer and the insulating layer until A first via is formed on the surface of the first metal, and the ITO layer is electrically connected to the first metal trace through the first via. The flat layer is also recessed downward through the passivation layer until a second via is formed on the surface of the second metal layer, and the ITO layer is electrically connected to the second metal trace through the second via Sexual connection.

Further, the first metal trace is electrically connected to the second metal trace through the ITO layer.

Further, wherein the second metal trace is located on one side of the first via hole, and the passivation layer and the planarization layer are provided between the second metal trace and the first via hole.

Further, the material selected for the ITO layer is indium tin oxide material.

Further, the material used for the first metal trace is copper.

Further, wherein the thickness of the second metal trace is 400-450 nm.

Further, the material used for the second metal trace is copper.

Further, wherein the insulating layer wraps the first metal trace inside, wherein the passivation layer wraps the second metal trace inside.

Further, there are two or more clock signal lines provided in the plastic frame area for electrically connecting with the scanning lines provided in the display area of the display panel.

Another object of the present invention is to provide a display device including the display panel according to the present invention.

Beneficial effect

The present invention provides a display panel and a display device, which are provided with a peripheral color film substrate common trace on the edge area of the panel, and a second metal trace on its first metal trace. Covered with ITO to electrically connect the second metal trace to the first metal trace, so that when the display panel is subjected to an electrostatic test or in actual use, the static electricity generated on it will be introduced into its periphery The color film substrate common traces at the edges can shield the arc and prevent the electrostatic arc from damaging the internal clock signal line, thereby enabling the display area of the display panel to work normally.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.

Figure 1 is a schematic diagram of the structure of an ESD electrostatic strike point in the prior art;

2 is a schematic structural diagram of a display panel in the prior art;

3 is a schematic diagram of a longitudinal cross-sectional structure of a GOA display panel in the prior art;

4 is a schematic diagram of a state in which the GOA display panel in the prior art is damaged by electrostatic arc when performing ESD test;

5 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

6 is a schematic cross-sectional structural view of a common wiring of a peripheral color filter substrate provided on the display panel shown in FIG. 5;

7 is a schematic diagram of a longitudinal cross-sectional structure of the display panel according to the present invention;

FIG. 8 is a schematic view of the arc damage received by the display panel shown in FIG. 7 during ESD testing.

Embodiments of the invention

The following is a description of each embodiment with reference to the attached drawings to illustrate specific embodiments of the invention that can be implemented. Directional terms mentioned in the present invention, such as up, down, front, back, left, right, inside, outside, side, etc., are only directions referring to the drawings. The names of elements mentioned in the present invention, such as first and second, are only to distinguish different meta-components, which can be better expressed. In the figure, units with similar structures are denoted by the same reference numerals.

Herein, embodiments of the present invention will be described in detail with reference to the drawings. The present invention can be embodied in many different forms, and the present invention should not be interpreted merely as the specific embodiments set forth herein. The embodiments of the present invention are provided to explain the actual application of the present invention, so that those skilled in the art can understand various embodiments of the present invention and various modifications suitable for specific intended applications.

Referring to FIG. 5, an embodiment of the present invention provides a display panel including a display area, a plastic frame area and an edge area connected in sequence, wherein the plastic frame area is surrounded by two plastic frame edge lines 42 As a result, the edge area is the area between the edge line 42 of the plastic frame and the panel cutting line 41.

Wherein the edge area is provided with a color film substrate common signal line 49; there are also multiple clock signal lines 43 in the plastic frame area, the clock signal lines 43 are distributed in parallel in the plastic frame area, and It is connected to the signal line 410 extending from the display area to the plastic frame area. The signal line 410 is perpendicular to the clock signal line 43, and each signal line 410 is correspondingly connected to the clock signal line 43.

Please refer to FIG. 6, wherein the color signal substrate common signal line 49 includes a first metal trace 62, an insulating layer 63, a second metal trace 64, a passivation layer 65, and a flat layer 66 disposed on the substrate 61 ITO layer 67.

The first metal trace 62 is disposed on the substrate 61, and the insulating layer 63 is also provided on the substrate 61 and wraps the first metal trace 62 in it. The second metal trace 64 is provided on the insulating layer 63, the passivation layer 65 is provided on the second metal trace 64, and is wrapped inside, the flat layer 66 is provided on the Said on the passivation layer 66.

The flat layer 66 is further recessed to form a first via 68 and a second via 69, wherein the first via 68 passes through the passivation layer 65 and the insulating layer 63 to the first metal The surface of the trace 62, and the second via is recessed downward through the passivation layer 65 to the surface of the second metal trace 64, wherein the second via 68 is located in the first via On one side of the hole 69, there is also a passivation layer 65 portion and a flat layer 66 portion between the two.

Further, an ITO layer is further provided on the planarization layer 66, which is electrically connected to the first metal trace 62 and the second metal trace 64 through the first via 68 and the second via 69, respectively Connection, thereby achieving electrical connection between the first metal trace 62 and the second metal trace 64. The selected material of the ITO layer 67 is preferably indium tin oxide material, and the selected material of the first metal trace 62 and the second metal trace 64 is preferably metallic copper, but it is not limited thereto.

Please refer to FIG. 7, which shows that the vertical cross-sectional structure of the display panel of the present invention includes an ITO layer 52, a sealant 55, a color film substrate ITO layer 54 and a color film substrate disposed on a clock trace on the array substrate 51 53.

The ITO layer 52 on the clock trace is provided on the array substrate 51, the sealant 55 is provided on the ITO layer 52 on the clock trace, and the ITO layer 54 on the color filter substrate is provided on the frame On glue 55, the color filter substrate 53 is disposed on the ITO layer 54 of the color filter substrate. The ITO layer 54 is the ITO layer on the common line 49 of the color filter substrate in FIG. 5, and the breakdown position in FIG. 5 is the ITO layer 67 between the first via 68 and the second via 69 in FIG. 7. .

Further, the display panel further includes a U-shaped module frame 56, a lower frame is disposed below the array substrate 51, and an upper frame is disposed above the color film substrate 53.

Compared with the prior art, a second via hole is provided on the common line of the color filter substrate, and a second metal trace is connected through the ITO layer. The ITO layer is a conductive material, mainly indium tin oxide material, which can effectively guide the arc and avoid the influence on the clock signal line in the plastic frame area during the test.

Please refer to FIG. 8, which is a schematic diagram of the display panel of the present invention damaged during ESD testing. The damaged area is the ITO layer between the first via and the second via in FIG. 6, so that The effect of shielding arc on the clock signal line in the rubber frame area.

During the ESD test of the display panel, the ESD electrostatic gun 57 conducts to the ITO layer of the color film substrate by striking the module frame 56, and then conducts through the ITO layer 54 of the color film substrate to damage the common line of the array-based color film substrate On the ITO film. In this way, the arc can be shielded to protect the array substrate and avoid screen abnormalities during the ESD test.

The present invention also provides a display device including the above-mentioned display panel, which mainly uses the common wiring of the color film substrate between the plastic frame area and the cutting line, and the second metal wiring is placed on the first metal wiring The hole design and ITO coverage electrically connect the second metal trace to the first metal trace to shield the arc, avoid the electrostatic arc damage to the clock signal line, and enable the display area to work normally.

The technical scope of the present invention is not limited to the content in the description, and those skilled in the art can make various variations and modifications to the embodiments without departing from the technical idea of the present invention, and these variations and modifications are all It should fall within the scope of the present invention.

Claims

A display panel includes a display area, a plastic frame area and an edge area connected in sequence. A common signal line of a color filter substrate is provided between the plastic frame area and a cutting line. The common signal line of the color filter substrate includes sequentially provided A first metal trace, an insulating layer, a passivation layer, a flat layer, and an ITO layer; wherein the flat layer is recessed downward through the passivation layer and the insulating layer until a first transition is formed on the surface of the first metal Hole, the ITO layer is electrically connected to the first metal trace through the first via; wherein,

A second metal trace is also provided on the insulating layer, the flat layer is recessed downward through the passivation layer until a second via is formed on the surface of the second metal layer, and the ITO layer passes through the The second via is electrically connected to the second metal trace.
The display panel according to claim 1, wherein:

The first metal trace is electrically connected to the second metal trace through the ITO layer.
The display panel according to claim 1, wherein:

The second metal trace is located on one side of the first via, and the passivation layer and the planarization layer are provided between the first via and the first via.
The display panel according to claim 1, wherein:

The material of the ITO layer is indium tin oxide material.
The display panel according to claim 1, wherein:

The first metal wiring material is copper.
The display panel according to claim 1, wherein:

The thickness of the second metal trace is 400-450 nm.
The display panel according to claim 1, wherein:

The second metal wiring material is copper.
The display panel according to claim 1, wherein:

The insulating layer wraps the first metal trace inside, wherein the passivation layer wraps the second metal trace inside.
The display panel according to claim 1, wherein:

Two or more clock signal lines are provided in the plastic frame area for electrically connecting with the scanning lines provided in the display area of the display panel.
A display device comprising the display panel as claimed in claim 1.