CN106918970A - Array base palte, liquid crystal display panel and liquid crystal display device - Google Patents
Array base palte, liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN106918970A CN106918970A CN201710311729.4A CN201710311729A CN106918970A CN 106918970 A CN106918970 A CN 106918970A CN 201710311729 A CN201710311729 A CN 201710311729A CN 106918970 A CN106918970 A CN 106918970A
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- lead
- data
- metal layer
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- base palte
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention discloses a kind of array base palte, liquid crystal display panel and liquid crystal display device.Array base palte includes the data lead a plurality of parallel to each other in non-display area.Include the lead of multistage first and the lead of multistage second per data lead.First lead is arranged at the first metal layer and is spaced.Second lead is arranged at second metal layer and is spaced.The first insulating barrier with the first via is provided between the first metal layer and second metal layer.The first lead and the second lead for being under the jurisdiction of same data lead are connected into the data lead by the first via.For the plane parallel to the data lead, the first lead/the second lead of adjacent two datas lead is alternately arranged in the projection of the plane.Therefore, spacing of the data lead belonging to adjacent two first lead/the second leads in same metal level can be increased on the premise of wiring region and non-change data lead line width is not increased using the present invention, substantially reduces the probability that wiring region Electro-static Driven Comb occurs.
Description
Technical field
The present invention relates to technical field of liquid crystal display, more particularly to a kind of array base palte, liquid crystal display panel and liquid crystal
Showing device.
Background technology
In recent years, low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) technology is continued to develop.Using
Low-temperature polysilicon silicon technology produces liquid crystal panel, is conducive to improving panel aperture opening ratio, lifts display brightness, power consumption reduction.
Thus low-temperature polysilicon silicon technology is applied to the more frivolous, low power consumption of production, high-resolution product.Because product resolution ratio is constantly carried
Rise, the pixel quantity in unit panel is continuously increased, therefore the bar number of the data wire in unit panel is also continuously increased therewith.
In the prior art, in the case where penetrance is not changed, designer only has by constantly reducing the spacing between each data wire
To increase the quantity of data wire.As a example by display panel with resolution ratio as 1920*1080, in extremely narrow and small peripheral wiring area
Domestic demand is while 1080 data lines of arranging.And the continuous reduction of data wire spacing considerably increase Electro-static Driven Comb (ESD,
Electro-Static discharge) occur probability, function and quality to product cause to have a strong impact on.
In the prior art, the first scheme for improving peripheral wiring area Electro-static Driven Comb is the peripheral wiring area of increase,
It is possible thereby to somewhat expand the spacing between each data wire.However, the program can increase the typesetting distribution of pattern distribution.Second
The scheme for improving peripheral wiring area Electro-static Driven Comb is the overall line width for reducing each data wire, it is possible thereby to widen each data wire
Between spacing.However, the program can influence the impedance of data-signal, so as to be impacted to properties of product.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of array base palte, liquid crystal display panel and liquid crystal display
Device.
According to the first aspect of the invention, there is provided a kind of array base palte, it is including a plurality of in non-display area
Data lead parallel to each other；Wherein, include per data lead：
It is arranged on the first metal layer, the lead of spaced multistage first；And
It is arranged on second metal layer, the lead of spaced multistage second；
Wherein, the first insulation with the first via is provided between the first metal layer and the second metal layer
Layer；
The first lead and the second lead for being under the jurisdiction of same data lead are connected into the data by first via
Lead；Also, for the plane parallel to the data lead, the throwing of the first lead of adjacent two datas lead in the plane
Shadow is alternately arranged, and the second lead of adjacent two datas lead is alternately arranged in the projection of the plane.
In one embodiment, first lead is identical with the line width of second lead.
In one embodiment, also including connecting one to one positioned at viewing area and described a plurality of data lead
A plurality of data lines.
In one embodiment, first lead is respectively positioned on the first metal layer, second lead with scan line
The second metal layer is respectively positioned on the data wire.
In one embodiment, first lead is respectively positioned on the second metal layer, second lead with scan line
The first metal layer is respectively positioned on the data wire.
In one embodiment, first lead is with the material of second lead：
Copper, aluminium, molybdenum；Or
The alloy being made up of two or three in copper, aluminium and molybdenum.
In one embodiment, also include：
It is formed at the second insulating barrier in the second metal layer, with the second via；And
It is formed at the pixel electrode layer on second insulating barrier；
The data lead is connected by second via with the pixel electrode layer.
In one embodiment, the material of the pixel electrode layer is following any material：Tin indium oxide, indium zinc oxide and
Tin oxide.
According to the second aspect of the invention, there is provided a kind of liquid crystal display panel, including：
Above-mentioned array base palte；
Color membrane substrates；And
It is formed at the liquid crystal layer between the array base palte and the color membrane substrates.
According to the third aspect of the present invention, there is provided a kind of liquid crystal display device, including above-mentioned liquid crystal display panel.
Compared with prior art, one or more embodiments in such scheme can have the following advantages that or beneficial effect
Really：
Using array base palte provided in an embodiment of the present invention, every data lead of its wiring area is by the lead of multistage first
It is electrically connected with the lead of multistage second and is formed.The lead of multistage first is located at the first metal layer, and is spaced.The lead of multistage second
Positioned at second metal layer, and it is spaced.Arranged in row mode per data lead, every section of first lead and the second lead are with row
Mode is arranged.The lead of multistage first in the first metal layer, odd column data lead is distributed in the data lead belonging to it
Odd-numbered line, the lead of multistage first in even column data lead is distributed in the even number line of the data lead belonging to it.In the second gold medal
Category layer, the lead of multistage second in odd column data lead is distributed in the even number line of the data lead belonging to it, even number column data
The lead of multistage second in lead is distributed in the odd-numbered line of the data lead belonging to it.So that belonging to adjacent two first leads
Data lead is doubled in the lead spacing of the first metal layer, and the data lead belonging to adjacent two second leads is in the second gold medal
The lead spacing for belonging to layer is doubled.Therefore, the present invention can not increase wiring area and non-change data lead line width
Under the premise of increase spacing of the data lead belonging to adjacent two first lead/the second leads in same metal level.
Other features and advantages of the present invention will illustrate in the following description, and partly become from specification
It is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be wanted by specification, right
Specifically noted structure in book and accompanying drawing is asked to realize and obtain.
Brief description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and constitutes a part for specification, with reality of the invention
Apply example to be provided commonly for explaining the present invention, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 shows the schematic top plan view of the data lead of embodiment of the present invention array base palte；
Fig. 2 shows the schematic top plan view of the first lead of embodiment of the present invention array base palte；
Fig. 3 shows the schematic top plan view of the second lead of embodiment of the present invention array base palte；
Fig. 4 shows the schematic top plan view of the first via of embodiment of the present invention array base palte；
Fig. 5 shows the generalized section of the data lead of embodiment of the present invention array base palte；
Fig. 6 shows the fabrication processing schematic diagram of the data lead of embodiment of the present invention array base palte.
Specific embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, how the present invention is applied whereby
Technological means solves technical problem, and reaches the implementation process of technique effect and can fully understand and implement according to this.Need explanation
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
The technical scheme for being formed is within protection scope of the present invention.
Embodiment of the present invention technical problem to be solved is：Due to the continuous reduction of data wire spacing considerably increase it is quiet
The probability that electricity release occurs, according to the scheme of the peripheral wiring area of increase of prior art, although can somewhat expand each number
According to the spacing between line, but the program can increase the typesetting distribution of pattern distribution；According to each number of reduction of prior art
According to the scheme of the overall line width of line, although the spacing that can widen between each data wire, but the program can influence data-signal
Impedance.In order to solve the above technical problems, the embodiment of the invention provides a kind of array base palte, liquid crystal display panel and liquid crystal
Showing device.
First embodiment
As shown in figure 1, being the schematic top plan view of the data lead of embodiment of the present invention array base palte.The array of the present embodiment
Substrate mainly includes the data lead a plurality of parallel to each other in non-display area.In the present embodiment, data lead is equal
Arranged using row mode order.Specifically, the data lead is located at the wiring area in non-display area.Per data lead bag
Include the first lead of multistage 101 and the second lead of multistage 102.The first lead of multistage 101 is arranged at the first metal layer, and interval row
Row.The second lead of multistage 102 is arranged at second metal layer, and is spaced.Set between the first metal layer and second metal layer
There is the first insulating barrier (not shown in figure 1) with the first via 103.It is under the jurisdiction of the first lead 101 of same data lead
The data lead is connected into by the first via 103 with the second lead 102.Also, for the plane parallel to data lead, phase
First lead 101 of adjacent two data leads is alternately arranged in the projection of the plane, the second lead of adjacent two datas lead
102 are alternately arranged in the projection of the plane.
It should be noted that the every data lead in the present embodiment is arranged in row mode, every section of first lead 101 and
Two leads 102 are arranged with line mode.Odd column data lead structure is identical, and even column data lead structure is identical.
Fig. 2 shows the schematic top plan view of the first lead 101 shown in Fig. 1.As shown in Fig. 2 the first lead 101 is located at
The first metal layer, and be spaced.First lead 101 includes the first lead of odd column 101 and the first lead of even column 101.Very
The first lead of multistage 101 in ordered series of numbers data lead is distributed in the odd-numbered line of the data lead belonging to it, even column data lead
In the first lead of multistage 101 be distributed in the even number line of the data lead belonging to it.Specifically, it is many in odd column data lead
The first lead 101 of section is sequentially distributed the first row in the data lead belonging to it, the third line, fifth line and the 7th row.Even column
The first lead of multistage 101 in data lead be sequentially distributed the second row in the data lead belonging to it, fourth line, the 6th row and
8th row.
That is, the first lead of odd column 101 specifically includes the first lead of odd column the first row 1011, odd column the third line
One lead 1012, the first lead of odd column fifth line 1013 and the first lead of row 1014 of odd column the 7th.The lead of even column first
101 specifically include the first lead of the second row of even column 1015, the first lead of even column fourth line 1016, the row first of even column the 6th
Lead 1017 and the first lead of row 1018 of even column the 8th.
Fig. 3 shows the schematic top plan view of the second lead 102 shown in Fig. 1.As shown in figure 3, the second lead 102 is located at
Second metal layer, and be spaced.Second lead 102 includes the second lead of odd column 102 and the second lead of even column 102.Very
The lead of multistage second in ordered series of numbers data lead is distributed in the even number line of the data lead belonging to it, in even column data lead
The lead of multistage second is distributed in the odd-numbered line of the data lead belonging to it.Specifically, the multistage second in odd column data lead
Lead is distributed in two rows, fourth line, the 6th row and the 8th row of the data lead belonging to it.Multistage in even column data lead
Second lead is distributed in the first row, the third line, fifth line and the 7th row of the data lead belonging to it.
That is, the second lead of odd column 102 specifically includes the second row of odd column the second lead 1021, odd column fourth line
Two leads 1022, the second lead of row 1023 of odd column the 6th and the second lead of row 1024 of odd column the 8th.The lead of even column second
102 specifically include the second lead of even column the first row 1025, the second lead of even column the third line 1026, even column fifth line second
Lead 1027 and the second lead of row 1028 of even column the 7th.
Fig. 4 shows the schematic top plan view of the first via 103 shown in Fig. 1.As shown in figure 4, the first via 103 is formed
In the discontinuities of data lead.Specifically, the first insulating barrier between the first metal layer and second metal layer (does not show in Fig. 1
Go out) open up the first via 103.
In the present embodiment, the first lead 101 and the second lead 102 for being under the jurisdiction of same odd column data lead pass through
First via 103 is connected into the data lead.Specifically, it is under the jurisdiction of the odd column the first row of same odd column data lead
One lead 1011 is electrically connected with the second lead of the second row of odd column 1021 by the first via 103, the row of odd column second
Second lead 1021 is electrically connected with the first lead of odd column the third line 1012 by the first via 103, odd column the 3rd
The first lead of row 1012 is electrically connected with the second lead of odd column fourth line 1022 by the first via 103, odd column
Four the second leads of row 1022 are electrically connected with the first lead of odd column fifth line 1013 by the first via 103, odd column
The first lead of fifth line 1013 is electrically connected with the second lead of row 1023 of odd column the 6th by the first via 103, odd number
Arrange the 6th the second lead of row 1023 to be electrically connected with by the first via 103 with the first lead of row 1014 of odd column the 7th, very
The first lead of row 1014 of ordered series of numbers the 7th is electrically connected with the second lead of row 1024 of odd column the 8th by the first via 103,
So as to form a complete odd column data lead.
The first lead 101 and the second lead 102 for being under the jurisdiction of same even column data lead are gone here and there by the first via 103
It is unified into the data lead.Specifically, be under the jurisdiction of second lead of even column the first row 1025 of same even column data lead with
The first lead of the second row of even column 1015 is electrically connected with by the first via 103, the first lead of the second row of even column 1015
It is electrically connected with by the first via 103 with the second lead of even column the third line 1026, the lead of even column the third line second
1026 are electrically connected with the first lead of even column fourth line 1016 by the first via 103, and even column fourth line first is drawn
Line 1016 is electrically connected with the second lead of even column fifth line 1027 by the first via 103, even column fifth line second
Lead 1027 is electrically connected with the first lead of row 1017 of even column the 6th by the first via 103, the row of even column the 6th
One lead 1017 is electrically connected with the second lead of row 1028 of even column the 7th by the first via 103, the row of even column the 7th
Second lead 1028 is electrically connected with the first lead of row 1018 of even column the 8th by the first via 103, so as to form one
The complete even column data lead of bar.
It should be noted that being divided into eight the first leads of row 101 with four column data leads, each column data lead in the present embodiment
As a example by the second lead 102, be only used for teaching those skilled in the art how to implement the present invention, but do not mean that be only capable of use the arrangement
Mode, specifically using which kind of arrangement mode, implementation process can combine practice to be needed to determine.
In order to illustrate more clearly of the space structure of above-mentioned data lead, as shown in figure 5, being embodiment of the present invention array base
The generalized section of the data lead of plate.The first lead of spaced multistage 101 is located at the first metal layer, spaced many
The second lead of section 102 is located at second metal layer.It is provided between the first metal layer and second metal layer with the first via 103
First insulating barrier 201.First lead 101 of each data lead and the second lead 102 are connected into this by the first via 103
Data lead.The second insulating barrier 203 with the second via 202 is provided with second metal layer.Set on second insulating barrier 203
There is pixel electrode layer 204.Data lead is connected by the second via 202 with pixel electrode layer 204.
As can be seen that for the plane parallel to data lead, the first lead 101 and even number in odd column data lead
The first lead 101 in column data lead is alternately arranged in the projection of the plane, the second lead 102 in odd column data lead
It is alternately arranged in the projection of the plane with the second lead 102 in even column data lead.
Using array base palte provided in an embodiment of the present invention, every data lead of its wiring area is by the lead of multistage first
It is electrically connected with the lead of multistage second and is formed.The lead of multistage first is located at the first metal layer, and is spaced.The lead of multistage second
Positioned at second metal layer, and it is spaced.Arranged in row mode per data lead, every section of first lead and the second lead are with row
Mode is arranged.The lead of multistage first in the first metal layer, odd column data lead is distributed in the data lead belonging to it
Odd-numbered line, the lead of multistage first in even column data lead is distributed in the even number line of the data lead belonging to it；In the second gold medal
Category layer, the lead of multistage second in odd column data lead is distributed in the even number line of the data lead belonging to it, even number column data
The lead of multistage second in lead is distributed in the odd-numbered line of the data lead belonging to it.So that belonging to adjacent two first leads
Data lead is doubled in the lead spacing of the first metal layer, and the data lead belonging to adjacent two second leads is in the second gold medal
The lead spacing for belonging to layer is doubled.
Therefore, the embodiment of the present invention can increase on the premise of wiring area and non-change data lead line width is not increased
Data lead belonging to adjacent two first lead/the second leads substantially reduces peripheral wiring region in the spacing of same metal level
The probability that domain Electro-static Driven Comb occurs.
Second embodiment
As shown in fig. 6, being the fabrication processing schematic diagram of the data lead of embodiment of the present invention array base palte.The making
Technique may include steps of S610 to S670.
In step S610, the first lead of spaced multistage 101 as shown in Figure 2 is formed in the first metal layer；
As shown in Fig. 2 the first lead 101 is located at the first metal layer, and it is spaced.First lead 101 includes odd column
First lead 101 and the first lead of even column 101.The first lead of multistage 101 in odd column data lead is distributed in belonging to it
Data lead odd-numbered line, the first lead of multistage 101 in even column data lead is distributed in the data lead belonging to it
Even number line.Specifically, the first lead of multistage 101 in odd column data lead is sequentially distributed in the data lead belonging to it
A line, the third line, fifth line and the 7th row.The first lead of multistage 101 in even column data lead is sequentially distributed in belonging to it
The second row of data lead, fourth line, the 6th row and the 8th row.
That is, the first lead of odd column 101 specifically includes the first lead of odd column the first row 1011, odd column the third line
One lead 1012, the first lead of odd column fifth line 1013 and the first lead of row 1014 of odd column the 7th.The lead of even column first
101 specifically include the first lead of the second row of even column 1015, the first lead of even column fourth line 1016, the row first of even column the 6th
Lead 1017 and the first lead of row 1018 of even column the 8th.
In step S620, the first insulating barrier 201 is formed on the first metal layer；
In step S630, opened up such as Fig. 4 on corresponding first insulating barrier 201 at the corresponding endpoint of the lead of multistage first
The first shown via 103；
In step S640, the second lead of spaced multistage 102 is formed in second metal layer；
Fig. 3 shows the schematic top plan view of the second lead 102 shown in Fig. 1.As shown in figure 3, the second lead 102 is located at
Second metal layer, and be spaced.Second lead 102 includes the second lead of odd column 102 and the second lead of even column 102.Very
The lead of multistage second in ordered series of numbers data lead is distributed in the even number line of the data lead belonging to it, in even column data lead
The lead of multistage second is distributed in the odd-numbered line of the data lead belonging to it.Specifically, the multistage second in odd column data lead
Lead is distributed in two rows, fourth line, the 6th row and the 8th row of the data lead belonging to it.Multistage in even column data lead
Second lead is distributed in the first row, the third line, fifth line and the 7th row of the data lead belonging to it.
That is, the second lead of odd column 102 specifically includes the second row of odd column the second lead 1021, odd column fourth line
Two leads 1022, the second lead of row 1023 of odd column the 6th and the second lead of row 1024 of odd column the 8th.The lead of even column second
102 specifically include the second lead of even column the first row 1025, the second lead of even column the third line 1026, even column fifth line second
Lead 1027 and the second lead of row 1028 of even column the 7th.
In step S650, the second insulating barrier 203 is formed in second metal layer；
In step S660, second is opened up on corresponding second insulating barrier 203 at the corresponding endpoint of the lead of multistage first
Via 202；
In step S670, pixel electrode layer 204 is formed on the second insulating barrier 203, so that data lead passes through second
Via 202 is connected with pixel electrode layer 204.
The first lead 101 and the second lead 102 for being under the jurisdiction of same odd column data lead are gone here and there by the first via 103
It is unified into the data lead.Specifically, be under the jurisdiction of first lead of odd column the first row 1011 of same odd column data lead with
The second lead of the second row of odd column 1021 is electrically connected with by the first via 103, the second lead of the second row of odd column 1021
It is electrically connected with by the first via 103 with the first lead of odd column the third line 1012, the lead of odd column the third line first
1012 are electrically connected with the second lead of odd column fourth line 1022 by the first via 103, and odd column fourth line second is drawn
Line 1022 is electrically connected with the first lead of odd column fifth line 1013 by the first via 103, odd column fifth line first
Lead 1013 is electrically connected with the second lead of row 1023 of odd column the 6th by the first via 103, the row of odd column the 6th
Two leads 1023 are electrically connected with the first lead of row 1014 of odd column the 7th by the first via 103, the row of odd column the 7th
First lead 1014 is electrically connected with the second lead of row 1024 of odd column the 8th by the first via 103, so as to form one
The complete odd column data lead of bar.
The first lead 101 and the second lead 102 for being under the jurisdiction of same even column data lead are gone here and there by the first via 103
It is unified into the data lead.Specifically, be under the jurisdiction of second lead of even column the first row 1025 of same even column data lead with
The first lead of the second row of even column 1015 is electrically connected with by the first via 103, the first lead of the second row of even column 1015
It is electrically connected with by the first via 103 with the second lead of even column the third line 1026, the lead of even column the third line second
1026 are electrically connected with the first lead of even column fourth line 1016 by the first via 103, and even column fourth line first is drawn
Line 1016 is electrically connected with the second lead of even column fifth line 1027 by the first via 103, even column fifth line second
Lead 1027 is electrically connected with the first lead of row 1017 of even column the 6th by the first via 103, the row of even column the 6th
One lead 1017 is electrically connected with the second lead of row 1028 of even column the 7th by the first via 103, the row of even column the 7th
Second lead 1028 is electrically connected with the first lead of row 1018 of even column the 8th by the first via 103, so as to form one
The complete even column data lead of bar.
It should be noted that a via can also be only opened up, that is, step S330 is not performed, and in step S360
A via is opened up on the insulating barrier 203 of corresponding first insulating barrier 201 and second at the corresponding endpoint of the lead of multistage first.
The present embodiment is the process for making of the data lead of the array base palte in embodiment one, in step S670,
Every data lead of its wiring area is electrical by the lead of multistage second in the lead of multistage first in step S610 and step S640
It is formed by connecting.In step S610, the lead of multistage first is located at the first metal layer, and is spaced.The multistage in step S640
Second lead is located at second metal layer, and is spaced.Arranged in row mode per data lead, every section of first lead and second
Lead is arranged with line mode.In step S610, the lead of multistage first in odd column data lead is distributed in the number belonging to it
According to the odd-numbered line of lead, the lead of multistage first in even column data lead is distributed in the even number line of the data lead belonging to it.
The lead of multistage second in odd column data lead in step S640 is distributed in the even number line of the data lead belonging to it, even number
The lead of multistage second in column data lead is distributed in the odd-numbered line of the data lead belonging to it.So that adjacent two first leads
Affiliated data lead is doubled in the lead spacing of the first metal layer, and the data lead belonging to adjacent two second leads exists
The lead spacing of second metal layer is doubled.
Therefore, the embodiment of the present invention can increase on the premise of wiring area and non-change data lead line width is not increased
Data lead belonging to adjacent two first lead/the second leads substantially reduces peripheral wiring region in the spacing of same metal level
The probability that domain Electro-static Driven Comb occurs.
3rd embodiment
The present embodiment is the further optimization to the shape and material of the data lead in embodiment one and embodiment two.
In the present embodiment, the first lead 101 per data lead is parallel to each other, per the second lead of data lead
102 is parallel to each other, and the first lead 101 is identical with the line width of the second lead 102.
Because composition is identical with the line width of the second lead 102 per the first lead 101 of data lead so that per data
The line width of lead integrally keeps uniformity.
In the present embodiment, the material of the first lead 101 and the second lead 102 is copper, aluminium, molybdenum.Or, the first lead
101 and second the material of lead 102 be the alloy being made up of two or three in copper, aluminium and molybdenum.
In the present embodiment, the material of pixel electrode layer 204 is following any material：Tin indium oxide, indium zinc oxide and oxygen
Change tin.
Fourth embodiment
Array base palte in the present embodiment is more including what is connected one to one positioned at viewing area and a plurality of data lead
Data line (not shown in figure 1).First lead 101 is respectively positioned on the first metal layer with scan line (not shown in figure 1), and second draws
Line 102 is respectively positioned on second metal layer with data wire.During the manufacture craft for carrying out array base palte, the first lead 101 with sweep
Retouch line to be formed in a patterning processes, the second lead 102 is formed with data wire in a patterning processes, so as to can carry
The transmission quality of data-signal high.The first metal layer can be gate metal layer, and second metal layer can be source-drain electrode metal level.
Optionally, during the manufacture craft for carrying out array base palte, the first lead 101 can also be respectively positioned on scan line
Second metal layer, the second lead 102 can also be respectively positioned on the first metal layer with data wire.The first metal layer can be gate metal
Layer, second metal layer can be source-drain electrode metal level.
5th embodiment
The embodiment of the present invention provides a kind of liquid crystal display panel, including array base palte, coloured silk described in any of the above-described embodiment
Ilm substrate and the liquid crystal layer being formed between array base palte and color membrane substrates.
The embodiment of the present invention provides a kind of liquid crystal display device, including above-mentioned liquid crystal display panel.
Using liquid crystal display panel and/or liquid crystal display device in the present embodiment, due to changing its wiring area
The structure of data lead, enabling increase adjacent two on the premise of wiring area and non-change data lead line width is not increased
Data lead belonging to bar the first lead/the second lead substantially reduces peripheral wiring area electrostatic in the spacing of same metal level
Discharge the probability for occurring.
While it is disclosed that implementation method as above, but described content is only to facilitate understanding the present invention and adopting
Implementation method, is not limited to the present invention.Any those skilled in the art to which this invention pertains, are not departing from this
On the premise of the disclosed spirit and scope of invention, any modification and change can be made in the formal and details implemented,
But protection scope of the present invention, must be still defined by the scope of which is defined in the appended claims.
Claims (10)
1. a kind of array base palte, it is characterised in that including the data lead a plurality of parallel to each other in non-display area；Its
In, include per data lead：
It is arranged on the first metal layer, the lead of spaced multistage first；And
It is arranged on second metal layer, the lead of spaced multistage second；
Wherein, the first insulating barrier with the first via is provided between the first metal layer and the second metal layer；
The first lead and the second lead for being under the jurisdiction of same data lead are connected into the data lead by first via；
Also, for the plane parallel to the data lead, the first lead of adjacent two datas lead is handed in the projection of the plane
For arrangement, the second lead of adjacent two datas lead is alternately arranged in the projection of the plane.
2. array base palte according to claim 1, it is characterised in that the line width of first lead and second lead
It is identical.
3. array base palte according to claim 2, it is characterised in that also including positioned at viewing area and described a plurality of
The a plurality of data lines that data lead connects one to one.
4. array base palte according to claim 3, it is characterised in that first lead and scan line are respectively positioned on described the
One metal level, second lead is respectively positioned on the second metal layer with the data wire.
5. array base palte according to claim 3, it is characterised in that first lead and scan line are respectively positioned on described the
Two metal levels, second lead is respectively positioned on the first metal layer with the data wire.
6. the array base palte according to claim 4 or 5, it is characterised in that first lead and second lead
Material is：
Copper, aluminium, molybdenum；Or
The alloy being made up of two or three in copper, aluminium and molybdenum.
7. array base palte according to any one of claim 1 to 5, it is characterised in that also include：
It is formed at the second insulating barrier in the second metal layer, with the second via；And
It is formed at the pixel electrode layer on second insulating barrier；
The data lead is connected by second via with the pixel electrode layer.
8. array base palte according to claim 7, it is characterised in that the material of the pixel electrode layer is following any material
Material：Tin indium oxide, indium zinc oxide and tin oxide.
9. a kind of liquid crystal display panel, it is characterised in that including：
Array base palte as any one of claim 1 to 8；
Color membrane substrates；And
It is formed at the liquid crystal layer between the array base palte and the color membrane substrates.
10. a kind of liquid crystal display device, it is characterised in that including liquid crystal display panel as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710311729.4A CN106918970A (en) | 2017-05-05 | 2017-05-05 | Array base palte, liquid crystal display panel and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710311729.4A CN106918970A (en) | 2017-05-05 | 2017-05-05 | Array base palte, liquid crystal display panel and liquid crystal display device |
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| CN106918970A true CN106918970A (en) | 2017-07-04 |
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| CN201710311729.4A Pending CN106918970A (en) | 2017-05-05 | 2017-05-05 | Array base palte, liquid crystal display panel and liquid crystal display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020107734A1 (en) * | 2018-11-29 | 2020-06-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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Application publication date: 20170704 |