CN109103181A - A kind of semiconductor structure - Google Patents
A kind of semiconductor structure Download PDFInfo
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- CN109103181A CN109103181A CN201810962135.4A CN201810962135A CN109103181A CN 109103181 A CN109103181 A CN 109103181A CN 201810962135 A CN201810962135 A CN 201810962135A CN 109103181 A CN109103181 A CN 109103181A
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- chip
- semiconductor structure
- ground line
- structure according
- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Abstract
This application discloses a kind of semiconductor structure, which includes: the first chip and the second chip of stacking；First chip and the second chip include device and ground line, and the ground line of first chip is electrically connected with the ground line of the second chip；Second chip further includes the weld pad being used for signal transmission, and the weld pad is electrically connected with the ground line of second chip.In static discharge; localised protection is carried out without increasing the device near local diode pair on the electrostatic discharging path of semiconductor structure; and; connection structure for connecting the ground line on different chips not will increase the parasitic capacitance of chip; so; semiconductor structure provided by the present application can provide electrostatic discharge (ESD) protection under the premise of not increasing chip layout area, not increasing chip cost and not influencing high speed signal integrality.
Description
Technical field
This application involves the static discharge technical field of chip more particularly to a kind of semiconductor structures.
Background technique
Integrated circuit is highly susceptible to damage of electrostatic discharge, and this damage may be in manufacturing process, in transport or can not
Occur under the case where manipulation or use environment.Many static discharge standards, as human-body model (Human Body Model,
HBM), machine discharge mode (Machine Model, MM) and charging assembly mode (Charged Device Model, CDM),
It has been established for performance and robustness of the confirmation electronic equipment in manufacturing process.
There are static discharge risks for semiconductor structure, as an example, semiconductor structure usually passes through CDM (Charged
Device Model, charging assembly mode) carry out static discharge.In order to reduce static discharge risk existing for semiconductor structure,
A kind of existing semiconductor structure structure is increased near local diode pair on the electrostatic discharging path of semiconductor structure
Device progress localised protection, however the increase of local diode, the entire chip area that will lead to semiconductor structure increases, and version
The increase of the area of pictural surface will lead to chip cost raising, moreover, the parasitism that increased part diode introduces is electric for high speed signal
Hold the integrality that will affect high speed signal.
Summary of the invention
In view of this, this application provides a kind of semiconductor structure, not increase chip layout area, not increase chip
Cost and under the premise of not influencing high speed signal integrality, provides electrostatic discharge (ESD) protection.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
The first aspect of the application provides a kind of semiconductor structure, comprising:
The first chip and the second chip stacked；
First chip and the second chip include device and ground line, the ground line and the second core of first chip
The ground line of piece is electrically connected；
Second chip further includes the weld pad being used for signal transmission, the ground connection of the weld pad and second chip
Line electrical connection.
Optionally, first chip, the second chip further include the conductive plunger positioned at chip surface layer, first core
Conductive plunger in piece, the second chip is electrically connected with the ground line of chip where it, the conductive plunger of first chip and the
The conductive plunger of two chips is electrically connected.
Optionally, first chip, the second chip include substrate and the several layers interconnection line on the substrate,
At least one layer of interconnection line in the several layers interconnection line is as the ground line.
Optionally, first chip, in the second chip, one of them be storage chip, it is another be peripheral circuit chip.
Optionally, the device of first chip is electrically connected with the device of the second chip.
Optionally, to be also connected with power supply between the ground line of first chip and the ground line of second chip clamped
Circuit.
Optionally, described to be grounded inside, the surrounding or unilateral for being evenly distributed on its affiliated chip.
Optionally, the overall width of the ground line is not less than 5 microns.
Optionally, the total quantity of first chip or the conductive plunger in the second chip is no less than 10.
Optionally, the semiconductor structure further includes the packaging body for protecting semiconductor structure internal structure.
The second aspect of the application provides a kind of semiconductor structure, comprising:
The chip of several stackings, the chip include device, electrical connection ground line and be used for signal transmission
Weld pad；
Common ground ring is electrically connected with the weld pad of the chip.
Optionally, further includes: the chip of package several stackings and the packaging body of common ground ring.
Optionally, the overall width of the ground line is not less than 5 microns.
Optionally, first chip, the second chip include substrate and the several layers interconnection line on the substrate,
At least one layer of interconnection line in the several layers interconnection line is as the ground line.
Optionally, first chip, in the second chip, one of them be storage chip, it is another be peripheral circuit chip.
Compared to the prior art, the application include it is following the utility model has the advantages that
Based on above technical scheme it is found that the ground line electrical connection of each chip in semiconductor structure.In this way, partly leading
When body structure carries out static discharge, the electrostatic charge being not provided on the chip of weld pad passes through the ground line being disposed thereon and flow to
It is provided on the chip of weld pad, then realizes that final electrostatic is put using the ground wire being provided on the chip of weld pad and weld pad
Electricity.Therefore, in semiconductor structure provided by the present application, in static discharge, without on the static discharge road of semiconductor structure
Increase the device near local diode pair on diameter and carry out localised protection, moreover, because the electrical connection of the ground line of different chips
Not will increase the parasitic capacitance of chip, so, semiconductor structure provided by the present application, can not increase chip layout area,
Under the premise of not increasing chip cost and not influencing high speed signal integrality, electrostatic discharge (ESD) protection is provided.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of device principle figure of existing semiconductor structure provided by the present application；
Fig. 2 is the structural schematic diagram for the semiconductor structure that the embodiment of the present application one provides；
Fig. 3 is the discharge path figure for the semiconductor structure that the embodiment of the present application one provides；
Fig. 4 is the device principle figure for the semiconductor structure that the embodiment of the present application two provides；
Fig. 5 is the device principle figure for the semiconductor structure that the embodiment of the present application three provides.
Specific embodiment
There are CDM electric discharge risks for semiconductor structure.When CDM electric discharge, semiconductor structure integrally needs logical from chip interior
Weld pad is crossed to discharge to outside.It is not set if be provided on segment chip on weld pad but segment chip in the semiconductor structure
Weld pad is set, then when CDM discharges, the CDM charge for the chip for being not provided with weld pad in semiconductor structure needs to pass through through silicon via
(through silicon via, TSV) flows out the chip, and the chip for being provided with weld pad is flowed by other TSV, thus
By using the weld pad that is provided on the chip of weld pad to external discharge.
When TSV flow direction being provided with the chip of weld pad from the chip of not set weld pad due to CDM charge, it will to TSV
The device at both ends causes to fail.It is then desired to require to carry out special protection to semiconductor structure for CDM protection.
The prior art mainly increases local diode near the device for being connected to through silicon via and carries out localised protection.
Referring to Fig. 1, which is a kind of device principle figure of existing semiconductor structure provided by the present application.
The semiconductor structure of Fig. 1 includes: the first chip 111 and the second chip 112；Wherein, the first chip 111 includes:
One device 121 and the second device 122；Second chip 112 includes: third device 123 and four device 124；First device, 121 He
Third device 123 passes through the first TSV141 connection；Second device 122 is connected with four device 124 by the 2nd TSV142.This
It outside, further include for the weld pad 15 with peripheral circuit progress signal transmission on the second chip 112, which can be multiple.
When CDM electric discharge, the electrostatic charge in the first chip 111 will flow into the by the first TSV141 and the 2nd TSV142
Two chips 112, and using the weld pad 15 in the second chip 112 to external discharge.
In order to protect the device at through silicon via both ends, the first chip 111 further include: first partial diode 131 and second game
Portion's diode 132；Second chip 112 further include: third part diode 133 and the 4th local diode 134.Wherein, first
The first end of local diode 131 and the first device 121 are connected to the same end of the first TSV141, and first partial diode
131 second end ground connection or connection power supply；The first end of second local diode 132 and the second device 122 are connected to second
The same end of TSV142, and the second end ground connection of the second local diode 132 or connection power supply；Third part diode 133
First end and third device 123 are connected to the same end of the first TSV141, and the second end ground connection of third part diode 133 or
Connect power supply；The first end and four device 124 of 4th local diode 134 are connected to the same end of the 2nd TSV142, and the
The second end ground connection of four local diodes 134 or connection power supply.
When CDM electric discharge, first partial diode 131 carries out localised protection to the first device 121；Second local diode
132 pair of second device 122 carries out localised protection；Third part diode 133 carries out localised protection to third device 123；4th
Local diode 134 carries out localised protection to four device 124.
But inventor is the study found that above-mentioned semiconductor structure includes deficiency below:
Since above-mentioned semiconductor structure needs to increase local diode beside each device connecting with through silicon via, it will
Increase chip area, and through silicon via quantity is more, the quantity of the local diode of setting is also more, and then increased domain face
It is long-pending then bigger.When the quantity of through silicon via is more, chip area will be increased considerably, 200% or more can be can increase.However, version
Increasing considerably for the area of pictural surface is unacceptable.Moreover, the cost of chip can also be increased with the increase of chip area.
In addition, the parasitic capacitance that increased part diode introduces will affect the complete of high speed signal for high speed signal
Property.
In order to solve the problems, such as that above-mentioned semiconductor structure exists, the embodiment of the present application provides a kind of semiconductor structure, should
Chip includes: the first chip and the second chip of stacking；First chip and the second chip include device and ground line, institute
The ground line for stating the first chip is electrically connected with the ground line of the second chip；Second chip further includes being used for signal transmission
Weld pad, the weld pad is electrically connected with the ground line of second chip.
The ground line of each chip in semiconductor structure provided by the present application is electrically connected.In this way, semiconductor structure into
When row static discharge, the electrostatic charge being not provided on the chip of weld pad is flow to by the ground line being disposed thereon is provided with weldering
On the chip of pad, final static discharge then is realized using the ground line being provided on the chip of weld pad and weld pad.Cause
This, in semiconductor structure provided by the present application, in static discharge, without increasing on the electrostatic discharging path of semiconductor structure
The device near local diode pair is added to carry out localised protection, moreover, because the electrical connection of the ground line of different chips will not increase
Concrete-cored parasitic capacitance, so, semiconductor structure provided by the present application can not increase chip layout area, not increase
Chip cost and under the premise of not influencing high speed signal integrality, provides electrostatic discharge (ESD) protection.
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only this
Apply for a part of the embodiment, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall in the protection scope of this application.
Embodiment one
More fully understand that technical solution provided by the present application, the application are real in order to facilitate description and those skilled in the art
Apply example will be to be illustrated for including the semiconductor structure of two chips.
Referring to fig. 2, which is the structural schematic diagram for the semiconductor structure that the embodiment of the present application one provides.
The semiconductor structure of Fig. 2 includes the first chip 201 and the second chip 202, wherein the first chip 201 includes first
Conductive plunger 21a-21b, the second conductive plunger 22a-22b, the first substrate 231, the first device 241, the second device 242 and first
Ground line 251；Second chip 202 include the first conductive plunger 21c-21d, the second conductive plunger 22c-22d, the second substrate 232,
Third device 243, four device 244, second are grounded the 252, first weld pad 261 and the second weld pad 262.
The device of the device of first chip 201 and the second chip 202 electrical connection, moreover, the device of the first chip 201 and the
The device of two chips 202 can be electrically connected using various ways, for example, the device of the first chip 201 and the second chip 202
Device can be connected by the second conductive plunger.
Wherein, the device of the device of the first chip 201 and the second chip 202 is closed by the connection that the second conductive plunger connects
System, can be with specifically: the first device 241 and third device 243 are connected by the second conductive plunger 22a and the second conductive plunger 22c
It connects；Second device 242 is connected with four device 244 by the second conductive plunger 22b and the second conductive plunger 22d.
First ground line 251 is electrically connected with the second ground line 252, moreover, the first ground line 251 and the second ground line 252
It can be electrically connected using various ways.For example, the first ground line 251 and the second ground line 252 can pass through the first conduction
Plug connection.
Wherein, the connection relationship that the first ground line 251 can be connect with the second ground line 252 by the first conductive plunger,
It can be with specifically: the first position of the first ground line 251 and the first position of the second ground line 252 pass through the first conductive plunger
21a and the first conductive plunger 21c connection；The second position of first ground line 251 and the second position of the second ground line 252 pass through
First conductive plunger 21b and the first conductive plunger 21d connection.
The first weld pad 261 and the second weld pad 262 of second chip 202 are electrically connected with the second ground line, and the first weld pad
261 and second weld pad 262 be used to signal transmission.
It should be noted that conductive plunger can be formed by TSV technique.Moreover, different conductive plunger connections can be with
Different conductive plungers is connected by conducting wire, can also be connected two conductive plungers by grafting.
In addition, in the embodiment of the present application, the first chip 201 and the second chip 202 include substrate and be located at substrate it
On several layers interconnection line, at least one layer of interconnection line in the several layers interconnection line can be used as the ground line of respective chip.
Since electrostatic charge majority is located in substrate, thus, when the ground line in the substrate of different chips is led by first
After electric plug connection, the electrostatic charge being not provided on the chip of weld pad, which passes through the ground line and first being arranged on its substrate, is led
Electric plug is flow on the chip for being provided with weld pad, is then realized most using the ground wire being provided on the chip of weld pad and weld pad
Whole static discharge.
Technical solution provided by the present application is more fully understood in order to facilitate description and those skilled in the art, it below will be
It is illustrated for the discharge path of label electrostatic charge in semiconductor structure schematic diagram.
Referring to Fig. 3, which is the discharge path figure for the semiconductor structure that the embodiment of the present application one provides.
The semiconductor structure of Fig. 3 includes: the first chip 201 and the second chip 202, wherein the first chip 201 includes second
Conductive plunger 22a-22b, the first device 241, the second device 242 and the first ground line 251；Second chip 202 is led including second
Electric plug 22c-22d, third device 243, four device 244, second are grounded the 252, first weld pad 261 and the second weld pad 262.
Wherein, the first ground line 251 is connected with the second ground line 252 by the first conductive plunger.
One of discharge electrostatic charges path when semiconductor structure carries out static discharge, in the first chip 201 are as follows: first
It is grounded 251 → the first conductive plungers → second 252 → the first weld pads 261 of ground line；Electrostatic charge in second chip 202 is put
One of power path are as follows: the second 252 → the first weld pads 261 of ground line.
It should be noted that in the first chip 201, the second chip 202, one of them be storage chip, it is another be outer
Circuit chip is enclosed, for example, the first chip 201 can be storage chip and the second chip 202 can be peripheral circuit chip.
The ground line of each chip in semiconductor structure provided by the embodiments of the present application is connected to one by conductive plunger
It rises.In this way, being not provided with the electrostatic charge on the chip of weld pad by being arranged at it when semiconductor structure carries out static discharge
On ground line and conductive plunger flow on the chip for being provided with weld pad, this is then provided with connecing on the chip of weld pad
Ground wire and weld pad realize final static discharge.Therefore, in semiconductor structure provided by the present application, in static discharge, nothing
The device near local diode pair need to be increased on the electrostatic discharging path of semiconductor structure and carry out localised protection, moreover, with
It not will increase the parasitic capacitance of chip in the conductive plunger for connecting the ground line on different chips, so, the embodiment of the present application mentions
The semiconductor structure of confession, can not increase chip layout area, do not increase chip cost and do not influence high speed signal it is complete
Under the premise of property, electrostatic discharge (ESD) protection is provided.
In addition, in order to improve the discharging efficiency of electrostatic charge, the ground line of each chip can be evenly distributed on belonging to it
The inside of chip, surrounding or unilateral, in order to collect the electrostatic charge of all positions in chip.
Since the width of ground line is bigger, the velocity of discharge of electrostatic charge is faster, thus, in order to improve putting for electrostatic charge
The overall width of electrical efficiency, the ground line of each chip can be not less than 5 microns.Wherein, the overall width of ground line is each item ground connection
The sum of line width of line.
In order to improve the discharging efficiency of electrostatic charge, the total quantity of the conductive plunger of the first chip 201 and the second chip 202
No less than 10.
Moreover, in order to protect semiconductor structure internal structure, semiconductor structure can also include for protecting semiconductor junction
The packaging body of structure internal structure.
The above are the specific implementations for the semiconductor structure that the embodiment of the present application one provides, in the specific implementation
In, it is to be illustrated for including two chips in semiconductor structure.In fact, the extension as the embodiment of the present application,
Chip in semiconductor structure can also be three or three or more.In these chips, the device on different chips is electrically connected,
And the weld pad for carrying out signal transmission is provided at least one chip.It should be noted that including three or three or more cores
The internal structure of the semiconductor structure of piece and connection relationship and it is above-mentioned include two chips semiconductor structure internal structure with
Connection relationship is essentially identical, those skilled in the art it is upper include the base of the specific implementation of the semiconductor structure of two chips
On plinth, it is easy to obtain the internal structure and connection relationship of the semiconductor structure comprising other quantity chips, herein no longer in detail
Description.
In the specific implementation of above-mentioned semiconductor structure, the ground voltage of different chips is identical, therefore, can will not
Ground line with chip directly passes through conductive plunger TSV and links together.
In addition, in the semiconductor structure, the ground voltage of different chips is also possible to difference, in this case, for reality
The Electro-static Driven Comb of existing semiconductor structure, the embodiment of the present application also provides the another of the semiconductor structure for including static discharge structure-preserving
A kind of implementation.Referring specifically to embodiment two.
Embodiment two
The semiconductor structure that embodiment two provides is to improve to obtain on the basis of the semiconductor structure that embodiment one provides
, therefore, embodiment two is similar to the partial content of embodiment one, and for the sake of brevity, details are not described herein.
The ground line of first chip and the ground line of second chip in semiconductor structure provided by the embodiments of the present application
Between be also connected with power supply clamp circuit.
Power clamp circuit clamps down on the output voltage on scheduled level for input voltage to be become peak value.
Technical solution provided by the present application is more fully understood in order to facilitate description and those skilled in the art, it below will be with
Two chips and each chip in semiconductor structure respectively include being illustrated for a ground line.
Referring to fig. 4, which is the device principle figure for the semiconductor structure that the embodiment of the present application two provides.
The semiconductor structure of Fig. 4 includes: the first chip 411 and the second chip 412, and the device on the first chip 411 and
Device electrical connection on second chip 412；Wherein, the first chip 411 includes the first ground line 421, and the second chip 412 includes the
Two ground lines 422, power clamp circuit 43 and weld pad 44, and the first ground line 421 and power clamp circuit 43 are inserted by conductive
The first end of plug connection, the second ground line 422 is connect with power clamp circuit 43, and the second end and weldering of the second ground line 422
Pad 44 connects.
Discharge electrostatic charges path when semiconductor structure carries out static discharge, in the first chip 411 are as follows: the first ground connection
421 → conductive plunger of line → power clamp circuit 43 → the second is grounded 422 → weld pad 44；Electrostatic electricity in second chip 412
Lotus discharge path are as follows: second ground line 422 → weld pad 44.
Since the voltage clamping of the first ground line 421 to second can be grounded 422 voltage by power clamp circuit 43,
So as to smoothly carry out discharge electrostatic charges.
It should be noted that power clamp circuit 43 can be located in the first chip 411, the second chip can also be located at
In 412.
Further include between ground line in semiconductor structure provided by the embodiments of the present application on various substrates and conductive plunger
The power clamp circuit of connection, so that two chips including different ground terminal voltages are able to carry out telecommunication, in order to electrostatic
The smooth electric discharge of charge.
The above are the specific implementations for the semiconductor structure that the embodiment of the present application two provides, in the specific implementation
In, it is to be illustrated for including two chips in semiconductor structure.In fact, the extension as the embodiment of the present application,
Chip in semiconductor structure can also be three or three or more.In these chips, the device on different chips is electrically connected,
And the weld pad for carrying out signal transmission is provided at least one chip.It should be noted that including three or three or more cores
The internal structure of the semiconductor structure of piece and connection relationship and it is above-mentioned include two chips semiconductor structure internal structure with
Connection relationship is essentially identical, those skilled in the art it is upper include the base of the specific implementation of the semiconductor structure of two chips
On plinth, it is easy to obtain the internal structure and connection relationship of the semiconductor structure comprising other quantity chips, herein no longer in detail
Description.
In addition, the another implementation as the application, in order to improve the rate of static discharge, the embodiment of the present application is also mentioned
Another semiconductor structure is supplied, referring specifically to embodiment three.
Embodiment three
More fully understand that technical solution provided by the present application, the application are real in order to facilitate description and those skilled in the art
Applying example will be illustrated so that two chips in semiconductor structure and each chip respectively include a ground line as an example.
Referring to Fig. 5, which is the device principle figure for the semiconductor structure that the embodiment of the present application three provides.
The semiconductor structure of Fig. 5 includes: the first chip 511, the second chip 512 and common ground ring 56, and the first chip
Device electrical connection on device and the second chip 512 on 511；Wherein, the first chip 511 includes the first ground line 531 and the
One weld pad 541, and the first ground line 531 and the first weld pad 541 connect, the first weld pad 541 passes through the first metal lead wire 551 and public affairs
Ground loop 56 is electrically connected altogether；Second chip 512 includes the second ground line 532 and the second weld pad 542, and second is grounded 532 Hes
The connection of second weld pad 542, the second weld pad 542 are electrically connected by the second metal lead wire 552 with common ground ring 56.
Discharge electrostatic charges path when semiconductor structure carries out static discharge, in the first chip 511 are as follows: the first ground connection
531 → the first weld pad of line, 541 → the first 551 → common ground of metal lead wire ring 56；Discharge electrostatic charges in second chip 512
Path are as follows: second ground line 532 → the second weld pad, 542 → the second 552 → common ground of metal lead wire ring 56.
In addition, in order to improve the discharging efficiency of electrostatic charge, the ground line of each chip can be evenly distributed on belonging to it
The inside of chip, surrounding or unilateral, in order to collect the electrostatic charge of all positions in chip.
Since the width of ground line is bigger, the velocity of discharge of electrostatic charge is faster, thus, in order to improve putting for electrostatic charge
The overall width of electrical efficiency, the ground line of each chip can be not less than 5 microns.Wherein, overall width is the line width of each item ground line
The sum of.
In order to protect semiconductor structure internal structure, semiconductor structure can also include the chip for wrapping up several stackings
With the packaging body of common ground ring.
Each chip of semiconductor structure provided by the embodiments of the present application includes for carrying out signal biography with peripheral circuit
Defeated weld pad, therefore, it is possible to which electrostatic charge on each chip can be by the ground line and weld pad that are arranged on its substrate
It flow to common ground ring and realizes static discharge.Therefore, semiconductor structure provided by the embodiments of the present application can not increase chip
Chip area under the premise of not increasing chip cost and not influencing high speed signal integrality, provides electrostatic discharge (ESD) protection.
The above are the specific implementations for the semiconductor structure that the embodiment of the present application three provides, in the specific implementation
In, it is to be illustrated for including two chips in semiconductor structure.In fact, the extension as the embodiment of the present application,
Chip in semiconductor structure can also be three or three or more.In these chips, the device on different chips is electrically connected,
And the weld pad for carrying out signal transmission is provided on each chip.It should be noted that including the half of three or three or more chips
The internal structure of conductor structure and connection relationship with it is above-mentioned include that the internal structures of semiconductor structure of two chips is closed with connecting
Be it is essentially identical, those skilled in the art it is upper include the specific implementation of the semiconductor structure of two chips on the basis of,
It is readily available the internal structure and connection relationship of the semiconductor structure comprising other quantity chips, is not described in detail herein.
Claims (15)
1. a kind of semiconductor structure characterized by comprising
The first chip and the second chip stacked；
First chip and the second chip include device and ground line, ground line and the second chip of first chip
Ground line electrical connection；
Second chip further includes the weld pad being used for signal transmission, the ground line electricity of the weld pad and second chip
Connection.
2. semiconductor structure according to claim 1, which is characterized in that first chip, the second chip further include
Conductive plunger positioned at chip surface layer, the ground line of the conductive plunger in first chip, the second chip and chip where it
Electrical connection, the conductive plunger of first chip are electrically connected with the conductive plunger of the second chip.
3. semiconductor structure according to claim 1, which is characterized in that first chip, the second chip include lining
Bottom and the several layers interconnection line on the substrate, at least one layer of interconnection line in the several layers interconnection line be used as described in connect
Ground wire.
4. semiconductor structure according to claim 1, which is characterized in that in first chip, the second chip, wherein it
One be storage chip, it is another be peripheral circuit chip.
5. semiconductor structure according to claim 1, which is characterized in that the device of first chip and the second chip
Device electrical connection.
6. semiconductor structure according to claim 1-5, which is characterized in that the ground line of first chip and
Power supply clamp circuit is also connected between the ground line of second chip.
7. semiconductor structure according to claim 1-5, which is characterized in that the ground line is evenly distributed on it
The inside of affiliated chip, surrounding or unilateral.
8. semiconductor structure according to claim 1-5, which is characterized in that the overall width of the ground line is not small
In 5 microns.
9. semiconductor structure according to claim 1-5, which is characterized in that first chip or the second chip
In the total quantity of conductive plunger be no less than 10.
10. semiconductor structure according to claim 1-5, which is characterized in that the semiconductor structure further includes
For protecting the packaging body of semiconductor structure internal structure.
11. a kind of semiconductor structure characterized by comprising
The chip of several stackings, the chip include device, the ground line of electrical connection and the weld pad that is used for signal transmission；
Common ground ring is electrically connected with the weld pad of the chip.
12. semiconductor structure according to claim 11, which is characterized in that further include: the core of package several stackings
The packaging body of piece and common ground ring.
13. semiconductor structure according to claim 11 or 12, which is characterized in that the overall width of the ground line is not less than
5 microns.
14. semiconductor structure according to claim 11 or 12, which is characterized in that first chip, the second chip are equal
Several layers interconnection line including substrate and on the substrate, at least one layer of interconnection line conduct in the several layers interconnection line
The ground line.
15. semiconductor structure according to claim 11 or 12, which is characterized in that in first chip, the second chip,
One of them be storage chip, it is another be peripheral circuit chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810962135.4A CN109103181A (en) | 2018-08-22 | 2018-08-22 | A kind of semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810962135.4A CN109103181A (en) | 2018-08-22 | 2018-08-22 | A kind of semiconductor structure |
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| CN109103181A true CN109103181A (en) | 2018-12-28 |
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| CN201810962135.4A Pending CN109103181A (en) | 2018-08-22 | 2018-08-22 | A kind of semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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