CN108022887B - A kind of flexible package structure and preparation method thereof, wearable device - Google Patents
A kind of flexible package structure and preparation method thereof, wearable device Download PDFInfo
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- CN108022887B CN108022887B CN201610936617.3A CN201610936617A CN108022887B CN 108022887 B CN108022887 B CN 108022887B CN 201610936617 A CN201610936617 A CN 201610936617A CN 108022887 B CN108022887 B CN 108022887B
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 180
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The embodiment of the invention discloses a kind of flexible package structures, comprising: flexible encapsulating substrate, the first rigid packaging body, at least one second rigid packaging body；Described first rigid packaging body includes at least one first chip, and the rigid encapsulating material for coating at least one first chip；Described second rigid packaging body includes: at least one third chip, and the rigid encapsulating material for coating at least one third chip；Described first rigid packaging body and at least one described second rigid packaging body are placed in the upper surface of the flexible encapsulating substrate；Further include: flexible encapsulating material；The flexibility encapsulating material is at least by the described first rigid packaging body and at least one second rigid packaging body coats in wherein.The embodiment of the invention also discloses the manufacturing methods and wearable device of a kind of flexible package structure.
Description
Technical field
The present invention relates to semiconductor device packaging techniques more particularly to a kind of encapsulating structure and preparation method thereof, wearable
Equipment.
Background technique
Under the promotion that electronic product constantly develops to miniature, light, multi-functional, highly integrated and highly reliable direction, integrate
Circuit also develops towards integrated, micromation and modularization direction.In recent years, with Intelligent bracelet, intelligent shoe, Brilliant Eyes
The rise of the intelligence wearable device such as mirror, integrated circuit have increasing need for meeting the needs of soft flexible to be bonded user profile
Demand, with this come increase user experience and improve equipment gather data accuracy.Wherein, the flexible package skill of integrated circuit
Art can provide reliablely and stablely working environment for IC chip, protection IC chip, improve its flexible,
It plays an important role in terms of stability and reliability.But existing chip package process all passes through hard base in many cases,
Plate is connected with peripheral applications circuit trace, in this way, causing IC chip for rigid material, flexible encapsulating substrate and flexibility
Wiring board is not used effectively.How flexible package structure is made full use of, the effective flexibility for improving multi-chip-package device
Characteristic is an important topic of current multi-chip flexible package technology.It is therefore proposed that a kind of flexible multiconductor chip package exists
It is of great significance in wearable device application.
Summary of the invention
To solve existing technical problem, the embodiment of the present invention provides a kind of multi-chip framework encapsulation structure and its system
Make method, wearable device.
In order to achieve the above objectives, the technical solution of the embodiment of the present invention is achieved in that
First aspect of the embodiment of the present invention provides a kind of flexible package structure, and the encapsulating structure includes: flexible package
Substrate, the first rigid packaging body, at least one second rigid packaging body；The first rigid packaging body include at least one first
Chip, and the rigid encapsulating material for coating at least one first chip；The second rigid packaging body include: to
A few third chip, and the rigid encapsulating material for coating at least one third chip；The first hardness envelope
Dress body and at least one described second rigid packaging body are placed in the upper surface of the flexible encapsulating substrate；Wherein, the encapsulation
Structure further include: flexible encapsulating material；The flexibility encapsulating material at least will the first rigid packaging body at least one the
Two rigid packaging body coats are in wherein.
In above scheme, the described first rigid packaging body further includes at least one second chip；It is described at least one second
Chip is placed in the upper surface of at least one first chip；Rigid encapsulating material in described first rigid packaging body is then used for
Coat at least one described first chip and at least one described second chip；And/or
Described second rigid packaging body further includes at least one fourth chip；At least one described fourth chip is placed in described
The upper surface of at least one third chip；Rigid encapsulating material in the second rigid packaging body be then used to coat it is described at least
One third chip and at least one described fourth chip.
In above scheme, the encapsulating structure further include: at least one third hardness packaging body；The third hardness encapsulation
Body includes: at least one fifth chip, and the rigid encapsulating material for coating at least one fifth chip；Wherein,
The third hardness packaging body and the second rigid packaging body are symmetrically disposed on the two sides of the described first rigid packaging body；It is corresponding
Ground, the flexibility encapsulating material will the first rigid packaging body, at least one second hardness packaging body and at least one the
Three rigid packaging body coats are in wherein.
In above scheme, at least one described second rigid packaging body and at least one described third hardness packaging body incline
It is placed in the upper surface of the flexible encapsulating substrate, tiltedly in order to reduce area occupied.
In above scheme, the encapsulating structure further include: at least one conductive welding disk and connect with the conductive welding disk
At least one solder bump；First chip in described first rigid packaging body is led by the solder bump with described
Electrical bonding pads connection.
In above scheme, the encapsulating structure further include: be set to the described first rigid packaging body and the flexible package
Insulating protective layer between substrate, the insulating protective layer can prevent first hardness when flexible encapsulating substrate is bent
The removing of the first chip and solder bump and/or the solder bump and the conductive welding disk in packaging body.
In above scheme, one end of the second rigid packaging body is placed on the insulating protective layer, with slant setting in
The upper surface of the flexible encapsulating substrate.
In above scheme, the encapsulating structure further include: at least one soldered ball；At least one described soldered ball is set to described
The lower surface of flexible encapsulating substrate, for being connected with the external terminal of the encapsulating structure.
Second aspect of the embodiment of the present invention provides a kind of wearable device, and the above institute is provided in the wearable device
The flexible package structure stated.
The third aspect of the embodiment of the present invention provides a kind of manufacturing method of flexible package structure, which comprises
In the upper surface of flexible encapsulating substrate, the first rigid packaging body and at least one second rigid packaging body are at least set；
Described first rigid packaging body includes at least one first chip, and the hardness for coating at least one first chip
Encapsulating material；Described second rigid packaging body includes: at least one third chip, and for coating at least one described third
The rigid encapsulating material of chip；
Using flexible encapsulating material at least by the described first rigid packaging body and at least one second rigid packaging body coats
In wherein.
In above scheme, the method also includes:
At least one third hardness packaging body is formed in the upper surface of the flexible encapsulating substrate, so that the third is rigid
Packaging body and the second rigid packaging body are symmetrically disposed on the two sides of the described first rigid packaging body；The third hardness encapsulation
Body includes: at least one fifth chip, and the rigid encapsulating material for coating at least one fifth chip；
Correspondingly, described to utilize flexible encapsulating material at least by the described first rigid packaging body and at least one second hardness
Packaging body coats are in wherein, comprising:
Using flexible encapsulating material by the described first rigid packaging body, at least one second rigid packaging body and at least one
A third hardness packaging body coats are in wherein.
Encapsulating structure described in the embodiment of the present invention and its manufacturing method, wearable device, can be by multiple integrated chips
Into same framework encapsulation structure, to effectively increase encapsulation integrated level；Moreover, because encapsulation described in the embodiment of the present invention
Chip is fixed using rigid encapsulating material in structure, and uses flexible encapsulating material by rigid packaging body coats, so, encapsulation
Multiple chips in structure can change arrangements of chips shape with the bending degree of flexible encapsulating substrate, meet integrated chip
The requirement of flexible characteristic；Further, and in the encapsulating structure as described in the embodiment of the present invention inside chip is to be encapsulated firmly
It completes, so protecting internal chip structure, ensure that signal integrity requirement.
Detailed description of the invention
In attached drawing (it is not necessarily drawn to scale), similar appended drawing reference can describe phase in different views
As component.Similar reference numerals with different letter suffix can indicate the different examples of similar component.Attached drawing with example and
Unrestricted mode generally shows each embodiment discussed herein.
Fig. 1 is the structural schematic diagram one of flexible package of embodiment of the present invention structure；
Fig. 2 to Fig. 5 is the structural schematic diagram of flexible package of embodiment of the present invention structure in the fabrication process；
Fig. 6 is the structural schematic diagram two of flexible package of embodiment of the present invention structure；
Fig. 7 is the structural schematic diagram three of flexible package of embodiment of the present invention structure；
Fig. 8 is the structural schematic diagram four of flexible package of embodiment of the present invention structure；
Fig. 9 is the structural schematic diagram five of flexible package of embodiment of the present invention structure.
Specific embodiment
Two classes can be divided into from package material by being currently used in wearable device chip, and one kind is hard encapsulating housing, such as
Hard chip packing-body is attached to clothes product using conducting wire by wearable silicon chip (patent No.: CN03815127.8), the patent
On, since chip uses hard packaging body, problems of Signal Integrity is unaffected, it is widely applied in existing wearable device,
But hard packaging body cannot paste and user profile, influences user experience, and the accuracy of data collection is to be improved；Another kind of is to adopt
With flexible encapsulant material, such as the method (patent No.: CN201511027139.6) of electronic device and manufacture electronic device, use
Flexible chip and flexible base board design a kind of foldable and deployable chip, can be completely suitable for wearable device, but patent institute
Flexible chip and the flexible encapsulating substrate problems of Signal Integrity due to caused by its mechanical bend and electromagnetic interference problem stated be
Flexible encapsulating substrate is applied to the important restriction factor of the highly dense Electronic Packaging of high speed.It is short of in terms of signal integrity processing, and
The chip manufacturing process difficulty of organic material chip is big, expensive.
Therefore, to solve the above problems, the embodiment of the present invention proposes a kind of flexible multiconductor piece for wearable device
Encapsulating structure and preparation method thereof, can be applied to integrated circuit it is open and flat and bending two states, be preferably bonded human body contour outline,
Flexible package inside chip is, so ensure that signal integrity requirement, to protect inside chip through encapsulating completion firmly simultaneously
Structure.In order to more fully hereinafter understand the features of the present invention and technology contents, with reference to the accompanying drawing to realization of the invention
It is described in detail, appended attached drawing purposes of discussion only for reference, is not used to limit the present invention.
Embodiment one
A kind of flexible package structure is present embodiments provided, specifically, in order to solve in existing multi-chip package technology not
Meet integrated chip flexible characteristic requirement, the problem of multi-chip tiling occupies excessive substrate area, flexibility described in the present embodiment
Multichip packaging structure specifically includes: flexible encapsulating substrate, the first rigid packaging body, at least one second rigid packaging body；Institute
Stating the first rigid packaging body includes at least one first chip, and the hardness packet for coating at least one first chip
Closure material；Described second rigid packaging body includes: at least one third chip, and for coating at least one described third core
The rigid encapsulating material of piece；Described first rigid packaging body and at least one described second rigid packaging body are placed in the flexibility
The upper surface of package substrate；Wherein, the encapsulating structure further include: flexible encapsulating material；The flexibility encapsulating material at least will
Described first rigid packaging body and at least one second rigid packaging body coats are in wherein.
Here, to meet the needs of existing multi-chip, the described first rigid packaging body further includes at least one second chip；
At least one described second chip is placed in the upper surface of at least one first chip；And/or the second hardness packaging body
It further include at least one fourth chip；At least one described fourth chip is placed in the upper surface of at least one third chip.
Accordingly, the rigid encapsulating material in the described first rigid packaging body be then specifically used for coating at least one described first chip and
At least one described second chip；It is described at least that rigid encapsulating material in described second rigid packaging body is then specifically used for cladding
One third chip and at least one described fourth chip.
Specifically, in practical applications, first chip in the described first rigid packaging body is placed in the flexible envelope
The upper surface of substrate is filled, second chip is stacked on first chip；Similarly, the institute in the described second rigid packaging body
The upper surface that third chip is placed in the flexible encapsulating substrate is stated, the fourth chip is stacked on the third chip.
In one embodiment, the encapsulating structure further include: at least one third hardness packaging body；The third is hard
Property packaging body include: at least one fifth chip, and the rigid encapsulating material for coating at least one fifth chip；
Wherein, the third hardness packaging body and the second rigid packaging body are symmetrically disposed on the two of the described first rigid packaging body
Side；Accordingly, the flexible encapsulating material will the described first rigid packaging body, at least one second hardness packaging body and at least
One third hardness packaging body coats is in wherein.
Similarly, the third hardness packaging body can also include at least one the 6th chip, at least one described the 6th core
Piece is placed in the upper surface of at least one fifth chip；Accordingly, the rigid encapsulating material in the third hardness packaging body
Then it is specifically used for coating at least one described fifth chip and at least one described the 6th chip.With the described second rigid packaging body
Structure is similar, and the fifth chip in the third hardness packaging body is placed in the upper surface of the flexible encapsulating substrate, described
6th chip is stacked in the fifth chip.
Here, for convenient for reduction occupied space, at least one described second rigid packaging body and at least one described third
The rigid equal slant setting of packaging body is in the upper surface of the flexible encapsulating substrate, in order to reduce area occupied.For example, in a tool
In body embodiment, the third chip is set to the upper right side of the flexible encapsulating substrate, and the fourth chip is stacked in described
On third chip, and the fifth chip is set to the upper left side of the flexible encapsulating substrate, and the 6th chip is stacked in
In the fifth chip, in this way, forming the corresponding second rigid packaging body in left and right and third hardness packaging body.
In practical applications, the encapsulating structure further include: at least one conductive welding disk and with the conductive welding disk connect
At least one solder bump connect；First chip in the first rigid packaging body by the solder bump with it is described
Conductive welding disk connection.Here, the third chip, fourth chip, fifth chip and the 6th chip upper surface are provided with pad
End, and can be electrically connected by flexible lead wire and the conductive welding disk.Further, the conductive welding disk can also incite somebody to action
Chip pin is connected with encapsulating structure external terminal.
In another embodiment, the encapsulating structure further include: be set to the described first rigid packaging body and described
Insulating protective layer between flexible encapsulating substrate, the insulating protective layer can prevent described when flexible encapsulating substrate is bent
The removing of the first chip and solder bump and/or the solder bump and the conductive welding disk in first rigid packaging body.This
In, after the encapsulating structure is provided with the insulating protective layer, one end of the described second rigid packaging body is placed in the insulation
On protective layer, with slant setting in the upper surface of the flexible encapsulating substrate.In practical applications, for make it is described second hardness
Packaging body and the third hardness packaging body form symmetrical structure, and one end of the third hardness packaging body is also placed in the insulation
On protective layer, with slant setting in the upper surface of the flexible encapsulating substrate.For example, the lower surface of the described first rigid packaging body
Insulating protective layer is each formed with side.
In practical applications, the encapsulating structure further include: at least one soldered ball；At least one described soldered ball is set to institute
The lower surface for stating flexible encapsulating substrate, for being connected with the external terminal of the encapsulating structure.Here, the conductive welding disk may be used also
Chip pin to be connected with the soldered ball.
Here, above-described flexible encapsulating substrate, which uses, contains molecular interface body (COF, chip on flexible
Printed circuit) flexible material, for example, by using thermoplasticity without glue coated polyimide copper foil；The soldered ball can be for not
With conductive metal structures such as the Sn/Ag soldered ball of size, Cu pillar；The insulating protective layer is mainly made of epoxy resin, can
Chip is protected to exempt from affected by environment, can also reduce thermal expansion mismatch between chip and flexible encapsulating substrate influences；The solder bump
It may include but be not limited to Au, Ni/Sn, Cu, Cu/Pb-Sn, In, Pb/Sn；The pad end is metal structure and and chip interior
Circuit structure electrically interconnects；The flexible lead wire may include but be not limited to it is all kinds of have flexibility can be electrically connected material；It is described hard
Property encapsulating material may include but be not limited to the rigid encapsulating material such as metal, plastics and ceramics；It is described flexibility encapsulating material may include
But it is not limited to poly- silicon cycloalkanes, polyurethanes, polyimides, polyether-ether-ketone, this kind of high molecular material of electrically conducting transparent terylene.
In this way, flexible package structure described in the embodiment of the present invention can be by multiple integrated chips to same framework encapsulation knot
In structure, to effectively increase encapsulation integrated level；Moreover, because using hardness packet in encapsulating structure described in the embodiment of the present invention
Closure material fixes chip, and uses flexible encapsulating material by rigid packaging body coats, in this way, multiple chips in encapsulating structure
Arrangements of chips shape can be changed with the bending degree of flexible encapsulating substrate, meet the requirement of integrated chip flexible characteristic；
Further, and in the encapsulating structure as described in the embodiment of the present invention inside chip is through encapsulating completion firmly, so protection
Internal chip structure, ensure that signal integrity requirement.
In addition, the flexible package structure as described in the embodiment of the present invention meets the requirement of integrated chip flexible characteristic,
So can effectively be bonded the flexible circuit of wearable device when applying in wearable device.Moreover, multiple chip inclinations
It stacks compared with the tiling of existing chip, integrated level of the embodiment of the present invention is high, and substrate area occupied is smaller, and consumptive material is few.
The embodiment of the present invention is described in further details below in conjunction with Fig. 1；Specifically, as shown in Figure 1, flexible multiconductor piece
Encapsulating structure includes:
Flexible encapsulating substrate 102, the flexible encapsulating substrate 102 are COF flexible material, the flexible encapsulating substrate 102
Physical protection is played to entire encapsulating structure, stress mitigates, moisture-proof effect of radiating；
At least one conductive welding disk 101, the conductive welding disk 101 is located at the upper surface of flexible encapsulating substrate 102, described to lead
Electrical bonding pads 101 are conductive metallic material；
At least one soldered ball 103, positioned at the lower surface of the flexible encapsulating substrate 102；Wherein, the conductive welding disk 101
Chip pin can be connected with soldered ball 103；The soldered ball 103 can be connected with encapsulating structure external terminal；
First chip 202 is placed in 102 upper surface of flexible encapsulating substrate, and specifically, first chip 202 is with upside-down mounting key
Conjunction mode is connected with flexible encapsulating substrate 102；
At least one solder bump 201, the solder bump 201 are located at first chip 202 and flexible encapsulating substrate
Between 102, and it is connected with conductive welding disk 101；
Insulating protective layer 205 is set between the flexible encapsulating substrate 102 and first chip 202, the insulation
Protective layer 205 can use epoxide resin material, in this way, as the protective layer of the first chip, and then in flexible encapsulating substrate
When 102 bending, first chip 202 and solder bump 201 and/or solder bump 201 and conductive welding disk 101 can be prevented
Removing；
Second chip 203 is located at the upper surface of first chip 202, using through silicon via technology or flexible lead wire bonding techniques with it is soft
Property package substrate 102 on conductive welding disk 101 be connected；
The hardness encapsulating material 204, for the first chip 202 and the second chip 203 to be coated on wherein, and then soft
Property package substrate 102 when being bent, can prevent the first chip 202 and the second chip 203 from rupturing delamination, and prevent flexible package
Substrate tearing；Here, first chip 202, the second chip 203 and rigid encapsulating material 204 constitute the first hardness encapsulation
Body；
Third chip 301 and 302 slant setting of fourth chip are all drawn using flexibility in the left side of flexible encapsulating substrate 102
The mode of line bonding is connected with flexible encapsulating substrate 102；
The third chip 301 and fourth chip 302 are coated on wherein by rigid encapsulating material 303；Here, described
Three chips 301, fourth chip 302 and rigid encapsulating material 303 constitute the second rigid packaging body；
The third hardness packaging body and state third core that fifth chip 401, the 6th chip 402, rigid encapsulating material 403 are formed
The structure for the second rigid packaging body that piece 301, fourth chip 302, rigid encapsulating material 303 are formed is the same and symmetrical；
Flexible encapsulating material 501 is used for the first rigid packaging body, the second rigid packaging body and third hardness packaging body packet
It is overlying on wherein, to form flexible multiconductor chip package 601.
Here, compared with prior art, in flexible package structure described in the embodiment of the present invention, the first rigid packaging body,
Second rigid packaging body, third hardness packaging body pass through flexible encapsulating material cladding, in this way, that can become according to external force
Change under the premise of the flexible degree that different arrangement shapes improves entire encapsulating structure is presented in rigid packaging body, guarantee chip with it is soft
Property package substrate between signal transmission path not with external force act on and change, ensure that signal integrity.Moreover, this implementation
Third chip, fourth chip, fifth chip and the 6th chip described in example can stack this structure by inclination to cooperate
It is less to occupy flexible encapsulating substrate area compared with existing for the flexible variety of entire encapsulating structure.Further, the present embodiment
Described entire encapsulating structure can at least integrate six chips, improve integrated chip density, and the encapsulating structure can
To be realized with existing equipment and technique, lay a good foundation to be effectively applied in all kinds of wearable devices.
Embodiment two
Present embodiments provide the manufacturing method of flexible package structure described in more than one embodiments one；Specifically, institute
The method of stating includes:
In the upper surface of flexible encapsulating substrate, the first rigid packaging body and at least one second rigid packaging body are at least set；
Described first rigid packaging body includes at least one first chip, and the hardness for coating at least one first chip
Encapsulating material；Described second rigid packaging body includes: at least one third chip, and for coating at least one described third
The rigid encapsulating material of chip；
Using flexible encapsulating material at least by the described first rigid packaging body and at least one second rigid packaging body coats
In wherein.
Here, to meet the needs of existing multi-chip, the described first rigid packaging body further includes at least one second chip；
At least one described second chip is placed in the upper surface of at least one first chip；And/or the second hardness packaging body
It further include at least one fourth chip；At least one described fourth chip is placed in the upper surface of at least one third chip.
Accordingly, the rigid encapsulating material in the described first rigid packaging body be then specifically used for coating at least one described first chip and
At least one described second chip；It is described at least that rigid encapsulating material in described second rigid packaging body is then specifically used for cladding
One third chip and at least one described fourth chip.
In one embodiment, the method also includes: the flexible encapsulating substrate upper surface formed at least one
A third hardness packaging body, so that the third hardness packaging body and the second rigid packaging body are symmetrically disposed on described first
The two sides of rigid packaging body；The third hardness packaging body includes: at least one fifth chip, and for coat it is described at least
The rigid encapsulating material of one fifth chip；Correspondingly, using flexible encapsulating material by the described first rigid packaging body, at least one
A second rigid packaging body and at least one third hardness packaging body coats are in wherein.Here, in practical applications, it is described extremely
Few one second rigid packaging body and at least one described equal slant setting of third hardness packaging body are in the flexible encapsulating substrate
Upper surface, in order to reduce area occupied.
Similarly, the third hardness packaging body can also include at least one the 6th chip, at least one described the 6th core
Piece is placed in the upper surface of at least one fifth chip；Accordingly, the rigid encapsulating material in the third hardness packaging body
Then it is specifically used for coating at least one described fifth chip and at least one described the 6th chip.
Fig. 2 to Fig. 5 is the structural schematic diagram of multi-chip of embodiment of the present invention framework encapsulation structure in the fabrication process；Below
It is described in further details in conjunction with Fig. 2 to Fig. 4 method described in the embodiment of the present invention；Specifically,
Step 1 is conductive weldering on the upside of the flexible encapsulating substrate 102 as shown in Fig. 2, providing flexible encapsulating substrate 102
Disk 101, downside are soldered ball 103, and the conductive welding disk 101 and soldered ball 103 are that conductive metallic material is formed, and the two is soft
Property package substrate 102 in have an electrical connection, the flexible encapsulating substrate 102 can change according to external force and respective curved becomes
Change, has the characteristics that mechanical flexibility and high density interconnection；
Step 2, as shown in figure 3, the first chip 202 is placed in the upper surface of the flexible encapsulating substrate 102, described the
One chip 202 can be used as logic chip, is connected using flip chip technology with flexible encapsulating substrate 102,202 signal of the first chip
Downwards, the solder bump 201 on chip is electrically connected by being heated and pressurizeed technology and conductive welding disk 101 at end, has it excellent
Good electrical property and high reliability；
Step 3, as shown in figure 4, stacking the second chip 203, first chip in 202 upper surface of the first chip
202 use through silicon via usually as storage chip, second chip 203 usually as logic chip, second chip 203
(TVS, through silicon via) technology or flexible lead wire bonding techniques and conductive welding disk 101 are electrically connected；Described first
Chip 202 and other gaps of flexible encapsulating substrate 102 in addition to the part that is electrically connected are by impressing or method for dispensing glue is filled
Insulating protective layer 205, the insulating protective layer 205 are made of epoxy resin and silicon rubber, can protect solder bump 201, make
Solder bump 201 is not damaged when chip stress, is protected 202 lower surface of the first chip yet, and rigid encapsulating material 204 is adopted
The first chip 202 and the second chip 203 are coated wherein with plastics or ceramic processing technology, to form the first hardness encapsulation
Body；
Step 4, as shown in figure 5, in the upper left side slant setting third chip 301 of the flexible encapsulating substrate 102, institute
301 left end of third chip is stated against flexible encapsulating substrate 102,301 right end of third chip abuts insulating protective layer 205, inclines
It is tiltedly placed with and is conducive to cooperation flexible encapsulating substrate bending change；At least one the 4th core is stacked on the third chip 301
Piece 302, the third chip 301 and fourth chip 302 are all electrically connected using flexible lead wire bonding techniques with conductive welding disk 101
It connects, rigid encapsulating material 303 coats third chip 301 and fourth chip 302 wherein, to form the second rigid packaging body；
Similarly, third hardness packaging body and third chip that fifth chip 401, the 6th chip 402 and rigid encapsulating material 403 are formed
301, fourth chip 302 is similar with the second rigid structure of packaging body that rigid encapsulating material 303 is formed and is symmetric；I.e.
In the upper right side slant setting fifth chip 401 of the flexible encapsulating substrate 102,401 right end of fifth chip is against flexibility
Package substrate 102,401 left end of fifth chip abut insulating protective layer 205, and slant setting is conducive to cooperate flexible package base
Plate benging variation；At least one the 6th chip 402, the fifth chip 401 and the 6th are stacked on the fifth chip 401
Chip 402 is all electrically connected using flexible lead wire bonding techniques and conductive welding disk 101.
Step 5, as shown in Figure 1, in the first rigid packaging body, the second rigid packaging body, third hardness packaging body and flexibility
It being coated on package substrate 102 using flexible encapsulating material 501, the flexibility encapsulating material 501 is used to protect entire encapsulating structure,
Respective curved variation can also be changed according to external force.
In one embodiment, as shown in fig. 6, in the tiled state of flexible multiconductor chip package shown in Fig. 1,
When entire packaging body both ends up tilt under by upward stress effect, the second rigid packaging body and third hardness packaging body
It corresponding can be lifted to flexible encapsulating substrate contact jaw.
In one embodiment, as shown in fig. 7, in the tiled state of flexible multiconductor chip package shown in Fig. 1,
When entire packaging body both ends tilt down under by downward stress effect, the second rigid packaging body and third hardness packaging body
It can be corresponding low to flexible encapsulating substrate contact jaw.
In one embodiment, as shown in figure 8, in the tiled state of flexible multiconductor chip package shown in Fig. 1,
When entire packaging body left end tilts down under by downward stress effect, right end is upwarped to past under upward stress effect
It rises, correspondingly, the second rigid packaging body can be corresponding low to flexible encapsulating substrate contact jaw, and third hardness packaging body and flexibility
Package substrate contact jaw can be lifted accordingly.
The present embodiment additionally provides a kind of wearable device, and above-described encapsulation knot is provided in the wearable device
Structure.In one embodiment, as shown in figure 9, flexible multiconductor chip package 601 is applied showing in wearable device 602
It is intended to, the chip flexible package structure 601 can change and corresponding change according to the stress of the wearable device 602.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (7)
1. a kind of flexible package structure, which is characterized in that the encapsulating structure includes: flexible encapsulating substrate, the first hardness encapsulation
Body, at least one second rigid packaging body；Described first rigid packaging body includes at least one first chip, and for coating
The rigid encapsulating material of at least one first chip；Described second rigid packaging body includes: at least one third chip, with
And the rigid encapsulating material for coating at least one third chip；The first rigid packaging body and it is described at least one
Second rigid packaging body is placed in the upper surface of the flexible encapsulating substrate；Wherein, the encapsulating structure further include: flexibility encapsulating
Material；The flexibility encapsulating material is at least by the described first rigid packaging body and at least one second rigid packaging body coats in it
In；
The encapsulating structure further include: at least one conductive welding disk and at least one solder being connect with the conductive welding disk
Salient point；First chip in described first rigid packaging body is connect by the solder bump with the conductive welding disk；
The encapsulating structure further include: the insulation being set between the described first rigid packaging body and the flexible encapsulating substrate is protected
Sheath, the insulating protective layer can prevent the first core in the described first rigid packaging body when flexible encapsulating substrate is bent
The removing of piece and solder bump and/or the solder bump and the conductive welding disk；
Wherein, one end of the described second rigid packaging body is placed on the insulating protective layer, with slant setting in the flexible envelope
Fill the upper surface of substrate.
2. encapsulating structure according to claim 1, which is characterized in that the described first rigid packaging body further includes at least one
Second chip；At least one described second chip is placed in the upper surface of at least one first chip；The first hardness envelope
Rigid encapsulating material in dress body is then used to coat at least one described first chip and at least one described second chip；With/
Or,
Described second rigid packaging body further includes at least one fourth chip；At least one described fourth chip be placed in it is described at least
The upper surface of one third chip；Rigid encapsulating material in the second rigid packaging body be then used to coat it is described at least one
Third chip and at least one described fourth chip.
3. flexible package structure according to claim 1 or 2, which is characterized in that the encapsulating structure further include: at least one
A third hardness packaging body；The third hardness packaging body includes: at least one fifth chip, and for coat it is described at least
The rigid encapsulating material of one fifth chip；Wherein, the third hardness packaging body is symmetrically set with the described second rigid packaging body
It is placed in the two sides of the described first rigid packaging body；Accordingly, the flexible encapsulating material will the first hardness packaging body, at least
One second rigid packaging body and at least one third hardness packaging body coats are in wherein.
4. flexible package structure according to claim 3, which is characterized in that at least one described second rigid packaging body and
At least one described equal slant setting of third hardness packaging body is occupied in the upper surface of the flexible encapsulating substrate in order to reduce
Area.
5. a kind of wearable device, which is characterized in that be provided in the wearable device described in any one of Claims 1-4
Flexible package structure.
6. a kind of manufacturing method of flexible package structure, which is characterized in that the described method includes:
In the upper surface of flexible encapsulating substrate, the first rigid packaging body and at least one second rigid packaging body are at least set；It is described
First rigid packaging body includes at least one first chip, and the hardness encapsulating for coating at least one first chip
Material；Described second rigid packaging body includes: at least one third chip, and for coating at least one described third chip
Rigid encapsulating material；
Using flexible encapsulating material at least by the described first rigid packaging body and at least one second rigid packaging body coats in it
In；
First chip in described first rigid packaging body is connect by solder bump with conductive welding disk；
Insulating protective layer is set between the described first rigid packaging body and the flexible encapsulating substrate；The insulating protective layer energy
It is enough in flexible encapsulating substrate bending, prevent the first chip in the described first rigid packaging body and solder bump and/or described
The removing of solder bump and the conductive welding disk；
One end of described second rigid packaging body is placed on the insulating protective layer, with slant setting in the flexible package base
The upper surface of plate.
7. manufacturing method according to claim 6, which is characterized in that the method also includes:
At least one third hardness packaging body is formed in the upper surface of the flexible encapsulating substrate, so that the third hardness encapsulates
Body and the second rigid packaging body are symmetrically disposed on the two sides of the described first rigid packaging body；The third hardness packaging body packet
It includes: at least one fifth chip, and the rigid encapsulating material for coating at least one fifth chip；
Correspondingly, described at least to be encapsulated the described first rigid packaging body and at least one second hardness using flexible encapsulating material
Body is coated on wherein, comprising:
Using flexible encapsulating material by the described first rigid packaging body, at least one second rigid packaging body and at least one the
Three rigid packaging body coats are in wherein.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936617.3A CN108022887B (en) | 2016-11-01 | 2016-11-01 | A kind of flexible package structure and preparation method thereof, wearable device |
| PCT/CN2017/081745 WO2018082275A1 (en) | 2016-11-01 | 2017-04-24 | Flexible package structure and preparation method therefor, and wearable device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936617.3A CN108022887B (en) | 2016-11-01 | 2016-11-01 | A kind of flexible package structure and preparation method thereof, wearable device |
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| CN108022887A CN108022887A (en) | 2018-05-11 |
| CN108022887B true CN108022887B (en) | 2019-10-18 |
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| CN108847442B (en) * | 2018-06-30 | 2022-01-25 | 山东昊润自动化技术有限公司 | Pressure chip packaging method |
| CN110739232B (en) * | 2018-07-20 | 2022-02-01 | 浙江清华柔性电子技术研究院 | Flexible packaging structure, manufacturing method and wearable device |
| CN112964282A (en) * | 2019-12-13 | 2021-06-15 | 北京联合大学 | Intelligent graphene flexible electronic skin and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5439849A (en) * | 1994-02-02 | 1995-08-08 | At&T Corp. | Encapsulation techniques which include forming a thin glass layer onto a polymer layer |
| CN1201257A (en) * | 1997-06-02 | 1998-12-09 | 三菱电机株式会社 | Semiconductor package body and semiconductor module using same |
| CN1330398A (en) * | 2000-06-16 | 2002-01-09 | 国际商业机器公司 | Tube core level encapsulation and manufacturing method thereof |
| CN105590903A (en) * | 2014-11-12 | 2016-05-18 | 英特尔公司 | Flexible system-level packaging solution scheme of wearable device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016111512A1 (en) * | 2015-01-09 | 2016-07-14 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
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2016
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- 2017-04-24 WO PCT/CN2017/081745 patent/WO2018082275A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5439849A (en) * | 1994-02-02 | 1995-08-08 | At&T Corp. | Encapsulation techniques which include forming a thin glass layer onto a polymer layer |
| CN1201257A (en) * | 1997-06-02 | 1998-12-09 | 三菱电机株式会社 | Semiconductor package body and semiconductor module using same |
| CN1330398A (en) * | 2000-06-16 | 2002-01-09 | 国际商业机器公司 | Tube core level encapsulation and manufacturing method thereof |
| CN105590903A (en) * | 2014-11-12 | 2016-05-18 | 英特尔公司 | Flexible system-level packaging solution scheme of wearable device |
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| WO2018082275A1 (en) | 2018-05-11 |
| CN108022887A (en) | 2018-05-11 |
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