CN114496733A - High-resistivity composite substrate, preparation method and electronic component - Google Patents

High-resistivity composite substrate, preparation method and electronic component Download PDF

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CN114496733A
CN114496733A CN202210392221.2A CN202210392221A CN114496733A CN 114496733 A CN114496733 A CN 114496733A CN 202210392221 A CN202210392221 A CN 202210392221A CN 114496733 A CN114496733 A CN 114496733A
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layer
gettering
substrate
interface
silicon
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CN114496733B (en
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杨超
李真宇
胡卉
胡文
孔霞
刘亚明
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Jinan Jingzheng Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

The application discloses a high-resistivity composite substrate, a preparation method and an electronic component, and belongs to the technical field of semiconductors, wherein a polycrystalline silicon layer with a first thickness is prepared on a substrate layer; preparing a gettering layer on the polycrystalline silicon layer to obtain a prefabricated body, wherein the gettering layer is made of silicon dioxide, silicon nitride or silicon oxynitride; annealing the prefabricated body to enable impurities in the prefabricated body to migrate from the first interface to the second interface; and removing the gettering layer and the polycrystalline silicon layer with the second thickness to enable the thickness of the residual polycrystalline silicon layer to meet the target thickness requirement, thereby obtaining the composite substrate. And activating impurities at the interface of the substrate layer and the polycrystalline silicon layer in a mode of combining the gettering layer with high-temperature annealing, transferring the impurities to the vicinity of the interface of the gettering layer and the polycrystalline silicon layer, and removing the impurities at the interface of the substrate layer and the polycrystalline silicon layer in a mode of removing the gettering layer and a part of the polycrystalline silicon layer close to the gettering layer to obtain the composite substrate with low loss and high resistivity.

Description

High-resistivity composite substrate, preparation method and electronic component
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a high-resistivity composite substrate, a preparation method and an electronic component.
Background
The composite substrate refers to a semiconductor material with a multilayer structure, and a common composite substrate comprises an active layer, an insulating layer and a substrate layer which are sequentially stacked, wherein the active layer and the insulating layer are main functional layers and are used for realizing propagation of signals such as light, electricity, sound and the like.
When the insulating layer is in direct contact with the substrate layer, a plurality of defect levels exist in the insulating layer near the interface between the insulating layer and the substrate layer, and the defect levels can attract carriers, so that the carriers in the substrate layer are attracted to the vicinity of the interface between the insulating layer and the substrate layer by the defect levels in the insulating layer, and a Surface Parasitic Conductance effect (PSC) is generated on the substrate layer, so that the effective resistivity of the substrate layer near the interface between the substrate layer and the substrate layer is greatly reduced. In order to solve the technical problem of low effective resistivity, a polysilicon layer is often disposed between an insulating layer and a substrate layer in the prior art, so that the polysilicon layer can be used as a trap layer rich in carrier traps to suppress PSCs.
Although the introduction of the polysilicon layer can improve the resistivity of the substrate layer to some extent, impurities, mainly boron and phosphorus impurities, are inevitably retained and concentrated at the interface between the polysilicon layer and the substrate layer. When the content of boron and/or phosphorus impurities is too high, the mobility of carriers near the interfaces of the polycrystalline silicon layer and the substrate layer is high, so that the resistivity of the polycrystalline silicon layer and the substrate layer is low, the loss of components prepared by the composite substrate is increased, signal crosstalk is generated, and the application requirements cannot be met.
Therefore, how to further improve the resistivity of the composite substrate with the polysilicon layer is a technical problem which needs to be solved at present.
Disclosure of Invention
In order to solve the technical problem that the resistivity of the composite substrate is low due to the fact that the content of impurities in the composite substrate is too high, the application provides the high-resistivity composite substrate, the preparation method and the electronic component.
In a first aspect, the present application provides a method for preparing a high resistivity composite substrate, comprising:
preparing a polysilicon layer with a first thickness on the substrate layer;
preparing a gettering layer on the polycrystalline silicon layer to obtain a prefabricated body, wherein the gettering layer is made of silicon dioxide, silicon nitride or silicon oxynitride;
annealing the prefabricated body to enable impurities in the prefabricated body to migrate from a first interface to a second interface, wherein the first interface is an interface between the polycrystalline silicon layer and the substrate layer, and the second interface is an interface between the polycrystalline silicon layer and the gettering layer;
and removing the gettering layer and the polycrystalline silicon layer with the second thickness to enable the thickness of the residual polycrystalline silicon layer to meet the target thickness requirement, thereby obtaining the composite substrate.
In one implementation, the impurity content of the first interface in the composite substrate is less than 1 × 1011atom/cm2。
In one implementation, the resistivity of the polysilicon layer remaining in the composite substrate and at the first interface is greater than 5000 Ω & cm, wherein the substrate layer is made of silicon or silicon carbide.
In one implementation manner, the annealing temperature used for the annealing treatment is 700-1200 ℃, the annealing time is 1-50 h, and the annealing atmosphere is nitrogen or argon.
In one implementation, if the material of the gettering layer is silicon nitride, the gettering layer is prepared by a deposition method; if the material of the gettering layer is silicon dioxide or silicon oxynitride, preparing the gettering layer by adopting a deposition method or a thermal oxidation method, wherein the oxidation temperature of the gettering layer prepared by adopting the thermal oxidation method is 900-1100 ℃, the oxidation time is 15-240 min, and the gas atmosphere is oxygen;
in an implementation manner, if the gettering layer is prepared by a thermal oxidation method, the annealing temperature used for the annealing treatment is the same as the oxidation temperature for preparing the gettering layer, the annealing time is 15min to 240min, and the annealing atmosphere is oxygen.
In one implementation mode, the thickness of the gettering layer is greater than 200nm, and the thickness of the remaining polysilicon layer is 500nm to 3000 nm.
In one implementation, the method further comprises:
preparing an insulating layer on the remaining polysilicon layer;
an active layer is prepared on the insulating layer.
In one implementation mode, the material of the insulating layer is silicon dioxide, silicon oxynitride or silicon nitride; the active layer is made of lithium niobate, lithium tantalate, lithium tetraborate, quartz, potassium titanyl phosphate, rubidium titanyl phosphate, gallium arsenide or silicon.
In a second aspect, the present application further provides a high resistivity composite substrate, which is prepared by the method for preparing a high resistivity composite substrate according to any one of the first aspect.
In a third aspect, the present application further provides an electronic component including the high-resistivity composite substrate according to the second aspect.
In summary, the high-resistivity composite substrate, the preparation method and the electronic component provided by the application have the following beneficial effects: the method comprises the steps of preparing a polycrystalline silicon layer with a first thickness on a substrate layer, then continuously preparing a thin gettering layer on the polycrystalline silicon layer, activating impurities at the interface of the substrate layer and the polycrystalline silicon layer in a mode of combining the gettering layer with high-temperature annealing, enabling the impurities to migrate to the position near the interface of the gettering layer and the polycrystalline silicon layer, and then removing the impurities at the interface of the substrate layer and the polycrystalline silicon layer in a mode of removing the gettering layer and a part of the polycrystalline silicon layer near the gettering layer to obtain the composite substrate with low loss and high resistivity.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a high resistivity composite substrate according to an embodiment of the present disclosure;
FIG. 2 is a graph showing the results of resistivity measurements of layers in a pre-fabricated article before and after annealing in an example of the present application.
Description of the reference numerals
100-substrate layer, 200-polysilicon layer, 300-gettering layer, 210-removing polysilicon layer, 220-retaining polysilicon layer, 400-insulating layer, 500-active layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As described in the background section, some B and/or P impurities remain inevitably and concentrate at the interface of the polysilicon layer and the substrate layer when the composite substrate is prepared. For example, the environment or equipment used during cleaning, spin-drying, polysilicon preparation, etc., may introduce boron and/or phosphorus impurities that may adhere to the surface of the substrate layer. In addition, the substrate layer is usually doped with ions to increase the resistivity of the substrate layer, for example, a silicon ingot doped with boron or phosphorus is used, so that after the silicon ingot doped with boron or phosphorus is cut into silicon wafers, impurities such as B or P adhere to the surfaces of the silicon wafers.
When the content of impurities, B and/or P, on the surface of the substrate layer is too high, the mobility of carriers near the interface between the polycrystalline silicon layer and the substrate layer is high, so that the resistivity near the interface between the polycrystalline silicon layer and the substrate layer is low, and further, the loss of components prepared by using the composite substrate is increased, signal crosstalk is generated, and the application requirements cannot be met. In order to solve the technical problem, the application provides a preparation method of a high-resistivity composite substrate.
The following describes a method for manufacturing a high-resistivity composite substrate according to an embodiment of the present application with reference to the drawings.
As shown in fig. 1, a method for preparing a high-resistivity composite substrate according to an embodiment of the present application includes the following steps:
step S100, a polysilicon layer 200 of a first thickness is prepared on the substrate layer 100.
The method for preparing the polysilicon layer 200 is not limited in the present application, and for example, the polysilicon layer 200 may be prepared by a deposition method, specifically, a deposition method such as a Low Pressure Chemical Vapor Deposition (LPCVD), a Plasma Enhanced Chemical Vapor Deposition (PECVD), and an Atmospheric Pressure Chemical Vapor Deposition (APCVD). The temperature range for preparing the polysilicon layer 200 may be 600 to 700 ℃, and more preferably 600 to 650 ℃.
The material of the substrate layer 100 is not limited in this application, and the material of the substrate layer 100 is a semiconductor material, for example, the material of the substrate layer 100 may be silicon or silicon carbide. Wherein, the silicon or the silicon carbide is a single crystal material.
It should be noted that, after the step S100, some boron and/or phosphorus impurities inevitably remain and accumulate in the substrate layer 100 and in the vicinity of the interface between the polysilicon layer 200 and the substrate layer 100, and these boron and/or phosphorus impurities are the main cause of the lower resistivity in the subsequently prepared polysilicon layer 200 and in the vicinity of the interface between the polysilicon layer 200 and the substrate layer 100, and therefore, the preparation method provided by the present application mainly aims to migrate the boron and/or phosphorus impurities in the vicinity of the interface between the enriched polysilicon layer 200 and the substrate layer 100 to the vicinity of the interface between the polysilicon layer 200 and the gettering layer 300.
Step S200, preparing a gettering layer 300 on the polysilicon layer 200 to obtain a pre-fabricated body, wherein the gettering layer 300 is made of silicon dioxide, silicon nitride, or silicon oxynitride.
The method of preparing the gettering layer 300 is not limited in this application, and for example: if the material of the gettering layer 300 is silicon nitride, the gettering layer 300 may be prepared by a deposition method; if the material of the gettering layer 300 is silicon dioxide or silicon oxynitride, the gettering layer 300 may be prepared by a deposition method or a thermal oxidation method, wherein the oxidation temperature of the gettering layer 300 prepared by the thermal oxidation method is 900 to 1100 ℃, the oxidation time is 15min to 240min, and the gas atmosphere is oxygen.
The thickness of the gettering layer 300 is not limited in the present application, and the thickness of the gettering layer 300 is required to be larger than 200nm, but the thickness of the gettering layer 300 may not be too thick in consideration of material cost.
Step S300, annealing the pre-fabricated body to make impurities in the pre-fabricated body migrate from a first interface to a second interface, where the first interface is an interface between the polysilicon layer 200 and the substrate layer 100, and the second interface is an interface between the polysilicon layer 200 and the gettering layer 300.
It should be noted that the impurities in the pre-preparation body refer to impurities boron and/or phosphorus that are concentrated near the interface between the polysilicon layer 200 and the substrate layer 100 and can affect the resistivity of the polysilicon layer 200 and the substrate layer 100.
In the annealing process of step S300, due to the temperature increase, the impurities in the pre-fabricated object may be thermally diffused, i.e., the impurities in the pre-fabricated object may be migrated. The migration of the impurities may be lateral or longitudinal. Taking the polysilicon layer 200 in the prefabricated body as an example, the transverse migration refers to the migration of impurities in the diameter direction of the polysilicon layer 200, and because the diameter of the polysilicon layer 200 in the prefabricated body is the same as the diameter of a wafer used by the substrate layer 100, and the diameter of the wafer is generally 76.2mm, 100mm, 150mm, 200mm and the like, the transverse migration of the impurities in the polysilicon layer 200 is the millimeter-scale migration; the vertical migration refers to the migration of impurities in the thickness direction of the polysilicon layer 200, i.e. in the direction of two interfaces of the polysilicon layer 200, and since the thickness of the polysilicon layer 200 is generally 300-3000 nm, the vertical migration of impurities in the polysilicon layer 200 is a nano-scale migration. It can be seen that the lateral migration distance is much greater than the longitudinal migration distance, and therefore the lateral migration of impurities within the polysilicon layer 200 is negligible.
The substrate layer 100 is a regularly and orderly arranged single crystal structure, for example, the substrate layer 100 is made of monocrystalline silicon; since the polysilicon layer 200 is made of polysilicon and has a large number of polysilicon grain boundaries, impurities are more likely to diffuse into the polysilicon layer 200 and less likely to diffuse into the substrate layer 100.
Meanwhile, the impurities are easier to migrate to the interface, so that most of the impurities migrate from the first interface to the second interface and migrate to the vicinity of the second interface. When the diffusion speed of the impurity in the gettering layer 300 is slow, the impurity may be concentrated near the second interface; when the diffusion rate of the impurity in the gettering layer 300 is fast, the impurity continues to diffuse into the gettering layer. It can be seen that the main function of the gettering layer 300 fabricated on the polysilicon layer 200 in the present application is to provide an enrichment interface or enrichment layer structure for migration of impurities, so that the impurities are more easily migrated toward the gettering layer 300.
Taking the gettering layer 300 as silicon dioxide as an example, after the annealing treatment, since the diffusion rate of the B and/or P impurities in the silicon dioxide is low, the B and/or P impurities are concentrated in the vicinity of the second interface.
In the present application, the annealing temperature, annealing time, annealing atmosphere, and the like of the annealing treatment are not limited. For example, the annealing temperature used for the annealing treatment may be 700 to 1200 ℃, the annealing time may be 1 to 50 hours, and the annealing atmosphere may be nitrogen, oxygen, or argon.
It should be further noted that, according to the present application, the annealing temperature and the annealing time may be adjusted according to the target thickness of the remaining crystalline silicon layer, so that the resistivity of the obtained composite substrate meets the preset requirement. Under the same annealing time condition, the higher the annealing temperature is, the faster the migration speed of the impurities is, and the more the migration quantity is; the longer the annealing time, the more the amount of impurity migration under the same annealing time conditions.
In an implementation manner, if the deposition method is used to prepare the gettering layer 300 in step S200, the annealing temperature used in the annealing process in step S300 may be 700-.
In an implementation manner, if the thermal oxidation method is used to prepare the gettering layer 300 in step S200, the annealing temperature used in the annealing process in step S300 may be 700-.
In an implementation manner, if the thermal oxidation method is adopted to prepare the gettering layer 300 in step S200, wherein the reaction atmosphere for preparing the gettering layer 300 by the thermal oxidation method is oxygen, and the oxidation temperature is 900 to 1100 ℃, in this way, the gettering layer 300 can be annealed by directly utilizing the reaction atmosphere (oxygen) and the oxidation temperature of the thermal oxidation, and the annealing time can be 15 to 240 min. That is, this implementation may complete the steps of preparing the gettering layer 300 and annealing treatment in the oxidation furnace, which may simplify the preparation process.
And S400, removing the gettering layer 300 and the polysilicon layer of the second thickness to enable the thickness of the remaining polysilicon layer to meet the target thickness requirement, thereby obtaining the composite substrate.
For ease of description, the removed polysilicon layer is referred to herein as removed polysilicon layer 210 and the remaining polysilicon layer is referred to as retained polysilicon layer 220. Thus, the second thickness of the polysilicon layer is the thickness of the removed polysilicon layer 210, and the second thickness is smaller than the first thickness.
After the processing in step S300, most of the impurities in the substrate layer 100 and the vicinity of the first interface may be migrated to the vicinity of the second interface, so that the gettering layer 300 and the region of the polysilicon layer 200, which is rich in impurities at this time, are removed, that is, most of the impurities in the pre-preparation body may be removed, and the impurity content at the interface between the reserved polysilicon layer 220 and the substrate layer 100 is reduced, so as not to affect the resistivity of the reserved polysilicon layer 220 and the substrate layer 100.
It should be noted here that the impurity only causes the decrease of the resistivity when the content of the element reaches a certain level, so that the present application does not require the removal of all the impurity, as long as the resistivity of the remaining polysilicon layer 220 and the vicinity of the interface between the remaining polysilicon layer 220 and the substrate layer 100 can satisfy the predetermined resistivity requirement. For example: the resistivity of the reserved polysilicon layer 220 and the reserved polysilicon layer 220 near the interface with the substrate layer 100 is required to be greater than 10000 Ω & cm; another example is: the resistivity of the remaining polysilicon layer 220 and the vicinity of the interface of the remaining polysilicon layer 220 and the substrate layer 100 is required to be greater than 5000 Ω & cm.
It should be noted that the specific thicknesses of the polysilicon layer 200, the polysilicon layer 210, and the polysilicon layer 220 are not limited in the present application. The thickness of the reserved polysilicon layer 220 can be set according to actual requirements, for example, the thickness of the reserved polysilicon layer 220 is 500nm to 3000 nm. It should be understood that the thickness of the remaining polysilicon layer 220 should be a predetermined target thickness value before the composite substrate of the present application is prepared, so that the thickness of the polysilicon layer 200 prepared in step S100 is greater than the predetermined target thickness of the remaining polysilicon layer 220.
It should also be noted that, in practice, a composite substrate with a resistivity that meets the requirements may be prepared by measuring the impurity content and/or resistivity at various depths of the annealed preform.
The impurity content of the first interface in the composite substrate prepared by the preparation method of the high-resistivity composite substrate provided by the above embodiment of the present application can be lower than 2 × 1011atom/cm2. Wherein, 2 is multiplied by 1011atom/cm2Refers to the total content of B impurity and P impurity at the first interface in the composite substrate, for example, the content of B impurity at the first interface in the composite substrate is 5X 1010atom/cm2The P impurity content of the first interface in the composite substrate is 4 x 1010atom/cm2. If the substrate layer 100 is a silicon substrate, the resistivity at the first interface and the remaining polysilicon layer 220 in the composite substrate are both greater than 5000 Ω & cm.
After the composite substrate is prepared in step S400, the steps S500 and S600 may be further performed to prepare the insulating layer 400 and the active layer 500 based on the composite substrate.
Step S500, preparing an insulating layer 400 on the remaining polysilicon layer 220.
Step S600, preparing an active layer 500 on the insulating layer 400.
The method for preparing the insulating layer 400 on the remaining polysilicon layer 220 is not limited in the present application, and any conventional implementation manner, such as deposition method, oxidation method, etc., may be adopted, and the material of the insulating layer 400 is not limited in the present application, and may be silicon dioxide, silicon oxynitride, silicon nitride, etc. When the insulating layer 400 is prepared by adopting an oxidation method, the reserved polycrystalline silicon layer 220 can be directly subjected to oxidation treatment to obtain the insulating layer 400, and the oxidation temperature can be 900-1000 ℃; thus, the silicon dioxide layer formed by oxidation of the portion of the polysilicon layer 220 away from the substrate layer is retained as the insulating layer 400, and the portion of the polysilicon layer 220 not oxidized near the substrate layer is retained as polysilicon.
The present application is also not limited to the method of forming the active layer 500 on the insulating layer 400, and for example, an ion implantation-bonding separation method or a direct bonding-mechanical thinning method may be used.
The ion implantation-bonding separation method is to perform ion implantation from one surface of a film substrate to the inside of the film substrate, so as to form an active layer 500, an ion implantation layer and a residual layer on the film substrate; then, one surface of the active layer 500 of the film substrate is bonded to the insulating layer 400 to obtain a bonded body, and the bonded body is subjected to heat treatment to peel off the residual layer from the bonded body, so that the active layer 500 is prepared on the insulating layer 400.
The direct bonding-mechanical thinning method is to directly bond the thin film substrate and the insulating layer 400, and then to thin the thickness of the thin film substrate by means of grinding or the like to obtain the active layer 500. As can be seen, the thin film substrate refers to a base material having a certain thickness for obtaining the active layer 500.
The material of the active layer 500 is not limited in the present application, and may be, for example, lithium niobate, lithium tantalate, lithium tetraborate, quartz, potassium titanyl phosphate, rubidium titanyl phosphate, gallium arsenide, silicon, or the like.
The following describes beneficial effects of the method for preparing the composite substrate for improving resistivity provided by the embodiment of the application by specific examples.
Example one
Step 1: a6-inch silicon wafer having a resistivity of greater than 10000. omega. cm and a thickness of 0.675mm was prepared as a substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 1.6 mu m on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-700 ℃.
And step 3: and preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting an LPCVD (low pressure chemical vapor deposition) method to obtain a prefabricated body, wherein the thickness of the silicon dioxide gettering layer is 300 nm.
And 4, step 4: and (3) carrying out high-temperature annealing treatment on the prefabricated body prepared in the step (3), wherein the annealing temperature is 850 ℃, the annealing time is 10 hours, the annealing atmosphere is nitrogen, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer.
And 5: the thickness requirement of the polysilicon layer required by the target product to be reserved is 1um, and the resistivity is more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the obtained composite substrate comprises the silicon substrate and the reserved polycrystalline silicon layer, and the thickness of the reserved polycrystalline silicon layer is 1 um.
In the examples, the pre-fabricated bodies before and after annealing were subjected to resistivity tests using an extended resistance tester (SRP), respectively.
As shown in FIG. 2, curve a in FIG. 2 represents the resistivity of each layer in the preform after the annealing treatment, and curve b in FIG. 2 represents the resistivity of each layer in the preform before the annealing treatment.
As can be seen from the curve b in fig. 2, the resistivity of the polysilicon layer 200 before the annealing treatment and the resistivity near the interface between the polysilicon layer 200 and the substrate layer 100 are relatively low due to the influence of impurities, and thus the use requirements of downstream devices cannot be met. As can be seen from the curve a in fig. 1, the resistivity of the polysilicon layer 200 near the interface with the substrate layer 100 and the resistivity of the remaining polysilicon layer 220 become high, and the resistivity of the polysilicon layer 210 and the gettering layer 300 near the interface with the removed polysilicon layer 210 becomes low, because the gettering layer 300 is disposed on the polysilicon layer 200, a gettering interface is provided, the tolerance of the gettering interface to impurities is higher, and at the same time, because there are many polysilicon grain boundaries, the impurities can be favorably diffused to the vicinity of the gettering interface, and then by removing the gettering layer 300 and a portion of the polysilicon layer close to the gettering layer 300, a low-loss composite substrate satisfying the resistivity greater than 10000 Ω & cm is obtained. As can be seen from curve a in FIG. 2, the resistivity of the remaining polysilicon layer 220 in the composite substrate is greater than 10000 Ω & cm, and the resistivity between the silicon substrate and the remaining polysilicon layer 220 is also greater than 10000 Ω & cm.
Example two
Step 1: a6-inch silicon wafer having a thickness of 0.675mm and a resistivity of greater than 10000. omega. cm was prepared as a substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 2500nm on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-700 ℃.
And step 3: preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting an oxidation method to obtain a pre-prepared body, wherein oxygen is introduced into an oxidation furnace, the oxidation temperature is 900 ℃, and the oxidation time is 240min, so that the silicon dioxide gettering layer with the thickness of 200nm is obtained.
And 4, step 4: and (4) carrying out high-temperature annealing treatment on the prefabricated body prepared in the step (3) at 1000 ℃, wherein the annealing time is 10h, the annealing atmosphere is nitrogen, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer.
And 5: the thickness of the polysilicon layer required by the target product to be reserved is required to be 1.3 μm, and the resistivity is set to be more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the resulting composite substrate comprised a silicon substrate and a remaining polysilicon layer, the remaining polysilicon layer having a thickness of 1.3 μm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remained in the composite substrate obtained after the annealing treatment is greater than 10000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remained is greater than 10000 Ω & lt/EN & gt cm.
Step 6: and (3) continuously preparing a silicon dioxide insulating layer on the reserved polycrystalline silicon layer in the step (5) by a high-temperature oxidation method, wherein the thermal oxidation temperature is 900 ℃, the thermal oxidation time is 10h, the part, far away from the substrate layer, in the reserved polycrystalline silicon layer is oxidized into the silicon dioxide insulating layer, the thickness of the silicon dioxide layer is 680nm, the part, close to the substrate layer, is not oxidized and is still polycrystalline silicon, and the thickness of the unoxidized polycrystalline silicon layer is 1000 nm. The surface of the silicon dioxide layer obtained after oxidation was polished to 500 nm.
And 7: and (4) preparing a lithium niobate active layer on the silicon dioxide layer prepared in the step (6) by an ion implantation-bonding separation method.
EXAMPLE III
Step 1: a6-inch silicon wafer having a resistivity of greater than 10000. omega. cm and a thickness of 0.675mm was prepared as a substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 2500nm on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-700 ℃.
And step 3: and preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting a thermal oxidation method to obtain a pre-prepared body, wherein oxygen is introduced into an oxidation furnace, the oxidation temperature is 900 ℃, and the oxidation time is 240min, so that the silicon dioxide gettering layer with the thickness of 200nm is obtained.
And 4, step 4: and (3) continuously annealing the prefabricated body in the step (3) in an oxygen atmosphere, wherein the annealing temperature is 900 ℃, the annealing time is 240min, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer. It will be appreciated that annealing in an oxygen atmosphere corresponds to a prolonged oxidation time, and therefore the thickness of the gettering layer will continue to grow during annealing.
And 5: the thickness of the polysilicon layer required by the target product is required to be 1000nm, and the resistivity is set to be more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the obtained composite substrate comprises a silicon substrate and a reserved polycrystalline silicon layer, and the thickness of the reserved polycrystalline silicon layer is 1000 nm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remained in the composite substrate obtained after the annealing treatment is greater than 10000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remained is greater than 10000 Ω & lt/EN & gt cm.
Step 6: an 800nm silicon dioxide insulating layer is prepared on the polysilicon layer by a deposition method.
And 7: and (4) preparing a lithium niobate active layer on the silicon dioxide layer prepared in the step (6) by an ion implantation-bonding separation method.
Example four
Step 1: a4-inch silicon carbide wafer having a resistivity of greater than 5000. omega. cm and a thickness of 0.525mm was prepared as the substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 1 mu m on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-650 ℃.
And step 3: and preparing a silicon nitride gettering layer on the polycrystalline silicon layer by an LPCVD (low pressure chemical vapor deposition) method to obtain a prefabricated body, wherein the thickness of the silicon nitride gettering layer is 300 nm.
And 4, step 4: and (3) carrying out high-temperature annealing treatment on the prefabricated body prepared in the step (3), wherein the annealing temperature is 700 ℃, the annealing time is 50 hours, the annealing atmosphere is argon, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon nitride gettering layer and the polycrystalline silicon layer.
And 5: the thickness of the polysilicon layer required by the target product is required to be 500nm, and the resistivity is greater than 5000 Ω & lt/EN & gt cm; and removing the silicon nitride gettering layer and the part of the polysilicon layer close to the silicon nitride gettering layer (i.e. removing the polysilicon layer) by polishing, wherein the polysilicon layer which is not removed is the remaining polysilicon layer. Thus, the obtained composite substrate comprises the silicon carbide substrate and the remaining polycrystalline silicon layer, and the thickness of the remaining polycrystalline silicon layer is 500 nm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remaining in the composite substrate obtained after the annealing treatment is greater than 5000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remaining is greater than 5000 Ω & lt/EN & gt cm.
Step 6: preparing a 800nm silicon nitride insulating layer on the polycrystalline silicon layer by a deposition method;
and 7: and (3) preparing a lithium tantalate active layer on the silicon nitride layer prepared in the step (6) by a direct bonding-mechanical thinning method.
EXAMPLE five
Step 1: a4-inch silicon wafer having a resistivity of greater than 5000. omega. cm and a thickness of 0.525mm was prepared as the substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 3 microns on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-650 ℃.
And step 3: and preparing a silicon oxynitride gettering layer on the polysilicon layer by an LPCVD (low pressure chemical vapor deposition) method to obtain a pre-prepared body, wherein the thickness of the silicon oxynitride gettering layer is 500 nm.
And 4, step 4: and (3) carrying out high-temperature annealing treatment on the prefabricated body prepared in the step (3), wherein the annealing temperature is 1100 ℃, the annealing time is 5 hours, the annealing atmosphere is argon, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon oxynitride gettering layer and the polycrystalline silicon layer.
And 5: the thickness requirement of the polysilicon layer required by the target product to be preserved is 2000nm, and the resistivity is more than 5000 Ω & cm; and removing the silicon oxynitride gettering layer and the part of the polysilicon layer close to the silicon oxynitride gettering layer (i.e. removing the polysilicon layer) by polishing, wherein the polysilicon layer which is not removed is the remaining polysilicon layer. Thus, the obtained composite substrate comprises a silicon substrate and a reserved polycrystalline silicon layer, and the thickness of the reserved polycrystalline silicon layer is 2000 nm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remaining in the composite substrate obtained after the annealing treatment is greater than 5000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remaining is greater than 5000 Ω & lt/EN & gt cm.
Step 6: preparing a 1000nm silicon dioxide insulating layer on the polycrystalline silicon layer by a deposition method;
and 7: and (3) preparing a lithium tantalate active layer on the silicon nitride layer prepared in the step (6) by a direct bonding-mechanical thinning method.
EXAMPLE six
Step 1: a6-inch silicon wafer having a thickness of 0.675mm and a resistivity of greater than 10000. omega. cm was prepared as a substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 2000nm on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-700 ℃.
And step 3: and preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting an oxidation method to obtain a pre-prepared body, wherein oxygen is introduced into an oxidation furnace, the oxidation temperature is 1100 ℃, and the oxidation time is 15min, so that the silicon dioxide gettering layer with the thickness of 200nm is obtained.
And 4, step 4: and (3) carrying out high-temperature annealing treatment on the prefabricated body prepared in the step (3) at 1200 ℃, wherein the annealing time is 1h, the annealing atmosphere is argon, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer.
And 5: the thickness of the polysilicon layer required by the target product to be reserved is required to be 1.3 μm, and the resistivity is set to be more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the resulting composite substrate comprised a silicon substrate and a remaining polysilicon layer, the remaining polysilicon layer having a thickness of 1.3 μm.
And testing the resistivity of the polysilicon layer reserved in the composite substrate obtained after the annealing treatment to be greater than 10000 Ω & cm and the resistivity between the substrate layer and the reserved polysilicon layer to be greater than 10000 Ω & cm through an extended resistance tester (SRP).
Step 6: and (3) continuously preparing a silicon dioxide insulating layer on the reserved polycrystalline silicon layer in the step (5) by a high-temperature oxidation method, wherein the thermal oxidation temperature is 900 ℃, the thermal oxidation time is 10h, the part, far away from the substrate layer, in the reserved polycrystalline silicon layer is oxidized into the silicon dioxide insulating layer, the thickness of the silicon dioxide layer is 680nm, the part, close to the substrate layer, is not oxidized and is still polycrystalline silicon, and the thickness of the unoxidized polycrystalline silicon layer is 1000 nm. The surface of the silicon dioxide layer obtained after oxidation was polished to 500 nm.
And 7: and (4) preparing a lithium niobate active layer on the silicon dioxide layer prepared in the step (6) by an ion implantation-bonding separation method.
EXAMPLE seven
Step 1: a6-inch silicon wafer having a thickness of 0.675mm and a resistivity of greater than 10000. omega. cm was prepared as a substrate layer.
Step 2: and preparing a polycrystalline silicon layer with the thickness of 2000nm on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polycrystalline silicon layer is 600-700 ℃.
And 3, step 3: and preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting an oxidation method to obtain a pre-prepared body, wherein oxygen is introduced into an oxidation furnace, the oxidation temperature is 1100 ℃, and the oxidation time is 15min, so that the silicon dioxide gettering layer with the thickness of 200nm is obtained.
And 4, step 4: and (3) continuously annealing the prefabricated body in the step (3) in an oxygen atmosphere, wherein the annealing temperature is 1100 ℃, the annealing time is 15min, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer. It will be appreciated that annealing in an oxygen atmosphere corresponds to a prolonged oxidation time, and therefore the thickness of the gettering layer will continue to grow during annealing.
And 5: the thickness of the polysilicon layer required by the target product to be reserved is required to be 1.3 μm, and the resistivity is set to be more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the resulting composite substrate comprised a silicon substrate and a remaining polysilicon layer, the remaining polysilicon layer having a thickness of 1.3 μm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remained in the composite substrate obtained after the annealing treatment is greater than 10000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remained is greater than 10000 Ω & lt/EN & gt cm.
Step 6: and (3) continuously preparing a silicon dioxide insulating layer on the reserved polycrystalline silicon layer in the step (5) by a high-temperature oxidation method, wherein the thermal oxidation temperature is 900 ℃, the thermal oxidation time is 10h, the part, far away from the substrate layer, in the reserved polycrystalline silicon layer is oxidized into the silicon dioxide insulating layer, the thickness of the silicon dioxide layer is 680nm, the part, close to the substrate layer, is not oxidized and is still polycrystalline silicon, and the thickness of the unoxidized polycrystalline silicon layer is 1000 nm. The surface of the silicon dioxide layer obtained after oxidation was polished to 500 nm.
And 7: and (4) preparing a lithium niobate active layer on the silicon dioxide layer prepared in the step (6) by an ion implantation-bonding separation method.
Example eight
Step 1: a6-inch silicon wafer having a thickness of 0.675mm and a resistivity of greater than 10000. omega. cm was prepared as a substrate layer.
Step 2: and preparing a polysilicon layer with the thickness of 1000nm on the substrate layer by adopting an LPCVD (low pressure chemical vapor deposition) method, wherein the preparation temperature of the polysilicon layer is 600-700 ℃.
And step 3: and preparing a silicon dioxide gettering layer on the polycrystalline silicon layer by adopting an oxidation method to obtain a pre-prepared body, wherein oxygen is introduced into an oxidation furnace, the oxidation temperature is 950 ℃, the oxidation time is 200min, and the silicon dioxide gettering layer with the thickness of more than 200nm is obtained.
And 4, step 4: and (3) continuously annealing the prefabricated body in the step (3) in an oxygen atmosphere, wherein the annealing temperature is 950 ℃, the annealing time is 180min, and impurities in the prefabricated body diffuse to the vicinity of the interface between the silicon dioxide gettering layer and the polycrystalline silicon layer. It will be appreciated that annealing in an oxygen atmosphere corresponds to a prolonged oxidation time, and therefore the thickness of the gettering layer will continue to grow during annealing.
And 5: the thickness of the polysilicon layer required by the target product is required to be 500 μm, and the resistivity is set to be more than 10000 Ω & cm; the silicon dioxide gettering layer and the portion of the polysilicon layer adjacent to the silicon dioxide gettering layer are removed by polishing (i.e., the polysilicon layer is removed), wherein the polysilicon layer that is not removed is the remaining polysilicon layer. Thus, the obtained composite substrate comprises a silicon substrate and a reserved polycrystalline silicon layer, and the thickness of the reserved polycrystalline silicon layer is 500 nm.
And testing by an extended resistance tester (SRP) that the resistivity of the polysilicon layer remained in the composite substrate obtained after the annealing treatment is greater than 10000 Ω & lt/EN & gt cm, and the resistivity between the substrate layer and the polysilicon layer remained is greater than 10000 Ω & lt/EN & gt cm.
Step 6: and continuously preparing the 800nm silicon oxynitride insulating layer on the remaining polycrystalline silicon layer in the step 5 by a deposition method.
And 7: and (4) preparing a lithium niobate active layer on the silicon oxynitride insulating layer prepared in the step (6) by an ion implantation-bonding separation method.
In summary, according to the preparation method of the high-resistivity composite substrate provided by the embodiment of the application, the polycrystalline silicon layer with the first thickness is prepared on the substrate layer, then the thin gettering layer is continuously prepared on the polycrystalline silicon layer, the impurities at the interface of the substrate layer and the polycrystalline silicon layer are activated in a mode of combining the gettering layer with high-temperature annealing, the impurities are migrated to the vicinity of the interface of the gettering layer and the polycrystalline silicon layer, and then the impurities at the interface of the substrate layer and the polycrystalline silicon layer are removed in a mode of removing the gettering layer and a part of the polycrystalline silicon layer close to the vicinity of the gettering layer, so that the composite substrate with low loss and high resistivity is obtained.
The application also provides a high-resistivity composite substrate, and the high-resistivity composite substrate is prepared by adopting the preparation method of the high-resistivity composite substrate provided by the embodiment of the application.
The application also provides an electronic component, which comprises the high-resistivity composite substrate.
The same and similar parts among the various embodiments in the specification can be referred to each other, and especially, the parts of the embodiments corresponding to the high-resistivity composite substrate and the electronic component can be referred to the parts of the preparation method of the high-resistivity composite substrate.
The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.

Claims (11)

1. A method for preparing a high-resistivity composite substrate is characterized by comprising the following steps:
preparing a polysilicon layer with a first thickness on the substrate layer;
preparing a gettering layer on the polycrystalline silicon layer to obtain a prefabricated body, wherein the gettering layer is made of silicon dioxide, silicon nitride or silicon oxynitride;
annealing the prefabricated body to enable impurities in the prefabricated body to migrate from a first interface to a second interface, wherein the first interface is an interface between the polycrystalline silicon layer and the substrate layer, and the second interface is an interface between the polycrystalline silicon layer and the gettering layer;
and removing the gettering layer and the polycrystalline silicon layer with the second thickness to enable the thickness of the remaining polycrystalline silicon layer to meet the target thickness requirement, thereby obtaining the composite substrate.
2. The method of claim 1, wherein the first interface of the composite substrate has an impurity content of less than 2 x 1011atoms/cm2。
3. The method according to claim 1, wherein the polysilicon layer remaining in the composite substrate and the resistivity at the first interface are both greater than 5000 Ω & cm, and wherein the substrate layer is made of silicon or silicon carbide.
4. The preparation method according to claim 1, wherein the annealing temperature is 700-1200 ℃, the annealing time is 1-50 h, and the annealing atmosphere is nitrogen or argon.
5. The production method according to claim 4, wherein if the material of the gettering layer is silicon nitride, the gettering layer is produced by a deposition method; and if the material of the gettering layer is silicon dioxide or silicon oxynitride, preparing the gettering layer by adopting a deposition method or a thermal oxidation method, wherein the oxidation temperature of the gettering layer prepared by adopting the thermal oxidation method is 900-1100 ℃, the oxidation time is 15-240 min, and the gas atmosphere is oxygen.
6. The method according to claim 1, wherein if the gettering layer is formed by a thermal oxidation method, an annealing temperature used for the annealing is the same as an oxidation temperature for forming the gettering layer, an annealing time is 15min to 240min, and an annealing atmosphere is oxygen.
7. The method according to claim 1, wherein the gettering layer has a thickness greater than 200nm, and the remaining polysilicon layer has a thickness of 500nm to 3000 nm.
8. The method of claim 1, further comprising:
preparing an insulating layer on the remaining polysilicon layer;
an active layer is prepared on the insulating layer.
9. The manufacturing method according to claim 8, wherein the insulating layer is made of silicon dioxide, silicon oxynitride, or silicon nitride; the active layer is made of lithium niobate, lithium tantalate, lithium tetraborate, quartz, potassium titanyl phosphate, rubidium titanyl phosphate, gallium arsenide or silicon.
10. A high-resistivity composite substrate characterized by being produced by the method for producing a high-resistivity composite substrate according to any one of claims 1 to 9.
11. An electronic component comprising the high-resistivity composite substrate according to claim 10.
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