CN114490211A

CN114490211A - Computer testing device and method

Info

Publication number: CN114490211A
Application number: CN202111675686.0A
Authority: CN
Inventors: 秦意乔; 张则民; 苗三朋
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Dawning Information Industry Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-05-13

Abstract

The application relates to a computer test device and a method, wherein the computer test device comprises a control unit, a debugging interface, a power interface and a sleep awakening interface. The debugging interface, the power supply interface and the sleep awakening interface are all used for being connected with a to-be-tested machine; the debugging interface is used for the control unit to send a starting signal or a wake-up signal to the to-be-tested machine through the debugging interface; the power interface is used for the control unit to send a power signal to the machine to be tested through the power interface so as to enable the machine to be tested to work normally; the sleep awakening interface is used for enabling the control unit to send awakening signals to the to-be-tested machine through the sleep awakening interface. The application provides a computer testing arrangement does not need the higher intelligent test system of price when testing the await measuring machine to with being connected of await measuring machine simple, the practicality is higher.

Description

Computer testing device and method

Technical Field

The present application relates to the field of testing technologies, and in particular, to a computer testing apparatus and method.

Background

With the development of electronic technology, computers have become necessary equipment for information processing. In order to ensure the stability of the computer motherboard, when the motherboard is manufactured, various tests, such as an on/off test, a sleep/wake-up test, a sleep wake-up test, and the like, need to be performed on the computer.

In the conventional technology, an intelligent test system is generally used to perform an on/off test, a sleep/wake-up test, and the like on a computer. However, the intelligent test system is expensive, and the connection between the intelligent test system and the dut during testing is complicated, and the practicability is low.

Disclosure of Invention

Therefore, in order to solve the above technical problems, it is necessary to provide a computer testing apparatus and method which do not need to use an expensive intelligent testing system, are simple to connect, and have high practicability.

In one aspect, an embodiment of the present application provides a computer test apparatus, which includes a control unit, a debug interface, a power interface, and a sleep wake-up interface;

the debugging interface, the power supply interface and the sleep awakening interface are all used for being connected with a to-be-tested machine;

the debugging interface is used for the control unit to send a starting signal or a wake-up signal to the to-be-tested machine through the debugging interface;

the power interface is used for enabling the control unit to send a power signal to the machine to be tested through the power interface so as to enable the machine to be tested to work normally;

and the sleep awakening interface is used for enabling the control unit to send awakening signals to the to-be-tested machine through the sleep awakening interface.

Need not to use the higher intelligent test system of price when testing the await measuring machine through above-mentioned computer testing arrangement, the connected mode of computer testing arrangement and await measuring machine is simple, convenient operation in the test procedure. Moreover, the computer testing device can realize the startup and shutdown test, the dormancy awakening test and the sleep awakening test of the computer to be tested, and has higher practicability.

In one embodiment, the power interface comprises a first interface and a second interface, the first interface is used for being connected with the machine to be tested, and the second interface is used for being connected with the ATX power supply;

and the control unit is used for sending the power supply signal provided by the ATX power supply to the machine to be tested through the first interface and the second interface.

According to the computer testing device, the ATX power supply can be controlled by the control unit to provide the power supply signal for the to-be-tested machine, so that the to-be-tested machine can be tested in a starting state by switching on alternating current.

In one embodiment, the control unit is used for sending a startup signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to startup and shutdown test; the starting signal is used for indicating the machine to be tested to send a power-on signal to the control unit through the first interface;

the control unit is also used for sending a power-on signal to the ATX power supply through the second interface, and the power-on signal is used for indicating the ATX power supply to send a power supply signal so as to enable the to-be-tested device to be in a starting state; the power supply signal is used for indicating the to-be-tested machine to execute a shutdown program and sending a down electric signal to the control unit through the first interface;

and the control unit is also used for sending a lower electric signal to the ATX power supply through the second interface, and the lower electric signal is used for indicating the ATX power supply to stop sending the power supply signal so as to enable the machine to be tested to be in a shutdown state.

The computer testing device can simulate the actual scene, firstly connects the alternating current of the to-be-tested machine, then enables the to-be-tested machine to enter the starting process of the starting state through the starting button, accords with the common use scene of a user, and can carry out more accurate test on the to-be-tested machine.

In one embodiment, the control unit is used for sending a starting-up signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to a power-on and power-off test or a dormancy awakening test; the starting signal is used for indicating the machine to be tested to execute a shutdown program or a dormant program so as to enable the machine to be tested to be in a shutdown state or a dormant state;

the control unit is also used for sending a wake-up signal to the machine to be tested through the debugging interface when the machine to be tested is in a dormant state so as to enable the machine to be tested to be in a starting state;

and the control unit is also used for receiving the state signal sent by the machine to be tested.

The computer testing device can simulate the starting process of the to-be-tested computer entering the starting state through the power on/off key after the to-be-tested computer is powered on in an actual application scene, and the process of awakening the to-be-tested computer from the dormant state through the power on/off key, so that the computer testing device conforms to the common use scene of a user and can test the to-be-tested computer more accurately.

In one embodiment, the control unit is used for sending a starting signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to sleep wake-up test; the starting signal is used for indicating the machine to be tested to execute the sleep program so as to enable the machine to be tested to be in a sleep state;

the control unit is also used for sending a wake-up signal to the to-be-tested machine through the sleep wake-up interface; or sending a wake-up signal to the to-be-tested machine through the debugging interface so as to enable the to-be-tested machine to be in a starting state;

The computer testing device can simulate the process of awakening the to-be-tested computer through the startup and shutdown key in the sleep state of the to-be-tested computer in the actual application scene and the process of awakening the to-be-tested computer through the keyboard or the mouse, accords with the common use scene of a user, and can carry out more accurate test on the to-be-tested computer.

In one embodiment, the computer test apparatus further comprises: the expansion interface is used for being connected with the expansion control unit;

and the extended interface is used for the control unit to send a wake-up signal to the to-be-tested machine through the sleep wake-up interface on the extended control unit.

According to the computer testing device, the control unit can send the awakening signal to the to-be-tested machine through the expansion interface, so that the control unit can send the awakening signal to the two to-be-tested machines through the sleep awakening interface and the expansion interface simultaneously. When the number of the expansion interfaces is more than one, the control unit can simultaneously send wake-up signals to the plurality of the to-be-tested machines to realize the sleep wake-up test of the plurality of the to-be-tested machines,

in one embodiment, the computer test apparatus further comprises: the test interface is used for being connected with a machine to be tested;

and the test interface is used for enabling the control unit to send a test signal to the machine to be tested through the test interface, and the test signal is used for testing the working state of the machine to be tested.

According to the computer testing device, the control unit can realize the testing of the working state of the machine to be tested through the testing interface, and the function of the computer testing device can be expanded, so that the practicability of the computer testing device is improved.

In one embodiment, the computer test apparatus further comprises: the first storage unit interface is used for being connected with the first storage unit;

and the first storage unit interface is used for enabling the control unit to send the information to be stored to the first storage unit through the first storage unit interface.

According to the computer testing device, the first storage unit interface connected with the first storage unit is arranged, so that the information of various tests performed on the computer to be tested by the computer testing device can be stored, the fault can be positioned and analyzed by reading the information in the first storage unit when the test fails, and the practicability of the computer testing device can be improved.

In one embodiment, the computer test apparatus further comprises: the second storage unit interface is used for being connected with the second storage unit;

and the second storage unit interface is used for the control unit to execute the program in the second storage unit through the second storage unit interface.

According to the computer testing device, the problem that the internal storage space of the control unit is insufficient can be solved by arranging the second storage unit interface connected with the second storage unit, so that a large file can be processed by using the computer testing device, and the practicability of the computer testing device is improved.

In one embodiment, the computer test apparatus further comprises: the display unit interface is used for being connected with the display unit;

and the display unit interface is used for the control unit to send the information to be displayed to the display unit through the display unit interface.

According to the computer testing device, the display unit interface connected with the display unit is arranged, so that the information of various tests performed on the computer to be tested by the computer testing device can be displayed, the functions of the computer testing device can be expanded, and the practicability of the computer testing device is improved.

In one embodiment, the computer test apparatus further comprises: the network interface is used for being connected with the machine to be tested;

and the network interface is used for enabling the control unit to send a control signal to the machine to be tested through the network interface.

According to the computer testing device, the remote control of the computer to be tested can be realized through the computer testing device through the setting of the network interface, the functions of the computer testing device are expanded, and the practicability of the computer testing device can be improved.

In one embodiment, the computer test apparatus further comprises: the key matrix interface is used for being connected with a to-be-tested machine;

and the key matrix interface is used for enabling the control unit to send an information setting signal to the to-be-tested machine through the key matrix interface.

According to the computer testing device, the key matrix interface connected with the computer to be tested is arranged, so that the information of the computer to be tested can be set, the functions of the computer testing device are expanded, and the practicability of the computer testing device is improved.

In another aspect, an embodiment of the present application provides a computer testing method, for use in the computer testing apparatus provided in the above embodiment, the method including:

the control unit sends a starting signal to the to-be-tested machine through the debugging interface, wherein the starting signal is used for indicating the to-be-tested machine to execute a shutdown program or a dormant program so as to enable the to-be-tested machine to be in a shutdown state or a dormant state;

and when the to-be-tested machine is in a dormant state, the control unit sends a wake-up signal to the to-be-tested machine through the debugging interface so as to enable the to-be-tested machine to be in a starting state.

In one embodiment, the power-on signal is further used to instruct the dut to send a power-on signal to the control unit, and the method further includes:

the control unit sends a power-on signal to the ATX power supply through the second interface, and the power-on signal is used for indicating the ATX power supply to send a power supply signal so as to enable the power supply to be detected to be in a starting state; the power supply signal is used for indicating the to-be-tested machine to execute a shutdown program and sending a power-off signal to the control unit;

the control unit sends a lower electric signal to the ATX power supply through the second interface, and the lower electric signal is used for indicating the ATX power supply to stop sending the power supply signal so that the to-be-tested machine is in a shutdown state.

In one embodiment, the power-on signal is further used to instruct the dut to execute a sleep program, so that the dut is in a sleep state, and the method further includes:

the control unit sends a wake-up signal to the machine to be tested through the sleep wake-up interface;

or the control unit sends a wake-up signal to the to-be-tested machine through the debugging interface so as to enable the to-be-tested machine to be in a starting state.

The embodiment of the application provides a computer test device and a method, wherein the computer test device comprises a control unit, a debugging interface, a power interface and a sleep awakening interface; the debugging interface, the power supply interface and the sleep awakening interface are all used for being connected with a to-be-tested machine; the debugging interface is used for the control unit to send a starting signal or a wake-up signal to the to-be-tested machine through the debugging interface; the power interface is used for the control unit to send a power signal to the machine to be tested through the power interface so as to enable the machine to be tested to work normally; the sleep awakening interface is used for enabling the control unit to send awakening signals to the to-be-tested machine through the sleep awakening interface. The computer testing device provided by the embodiment of the application can carry out the startup test and the awakening test (simulating the awakening operation of the startup and shutdown key) on the to-be-tested machine by connecting the debugging interface with the to-be-tested machine; through connecting power source interface, can provide working power supply to the test set for the control signal that the control unit sent can normally be received to the test set. The sleep awakening interface is connected with the to-be-tested machine, and the to-be-tested machine can be subjected to awakening test (the awakening operation of a keyboard or a mouse is simulated). When the computer testing device provided by the embodiment is used for testing the to-be-tested machine, an intelligent testing system with higher price is not needed, and the connection mode of the computer testing device and the to-be-tested machine in the testing process is simple and convenient to operate. Moreover, the computer testing device provided by the embodiment can realize the startup and shutdown test, the dormancy awakening test and the dormancy awakening test of the to-be-tested machine, and has higher practicability.

Drawings

FIG. 1 is a schematic diagram of a computer test apparatus according to an embodiment;

FIG. 2 is a schematic structural diagram of a computer test apparatus according to another embodiment;

FIG. 3 is a schematic structural diagram of a computer test apparatus according to another embodiment;

FIG. 4 is a flow chart illustrating steps of a computer testing method according to one embodiment;

FIG. 5 is a flow chart illustrating steps of a computer testing method according to another embodiment;

FIG. 6 is a flowchart illustrating steps of a computer testing method according to another embodiment.

Description of reference numerals:

10. a computer test device; 11. an ATX power supply; 100. a control unit; 101. debugging an interface; 102. a power interface; 112. a first interface; 122. a second interface; 103. a sleep wake-up interface; 104. expanding an interface; 105. a test interface; 106. a first storage unit interface; 107. a second storage unit interface; 108. a display unit interface; 109. a network interface; 110. a key matrix interface; 20. a machine to be tested; 21. an expansion control unit; 22. a first storage unit; 23. a second storage unit; 24. a display unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

As shown in fig. 1, an embodiment of the present application provides a computer test apparatus 10, where the computer test apparatus 10 includes a control unit 100, a debug interface 101, a power interface 102, and a sleep-wake interface 103. The control unit 100 may be various types of single-chip microcomputers, and the control unit 100 implements its functions by executing programs in an internal memory. The present embodiment does not limit the specific model of the control unit 100 as long as the function thereof can be implemented. Specifically, the control unit 100 is a GD32F40I single chip microcomputer.

The debug interface 101, the power interface 102, and the sleep-wake interface 103 are all interfaces provided on the control unit 100. The present embodiment does not limit the number of the debug interface 101, the power interface 102, and the sleep/wake-up interface 103, as long as the functions thereof can be realized.

When the computer test apparatus 10 is used to test the device under test 20, the debug interface 101 is connected to the device under test 20. The control unit 100 may send a power-on signal to the dut 20 through the debug interface 101 to enable the dut 20 to enter a power-on state. Meanwhile, the control unit 100 may also send a wake-up signal to the dut 20 through the debug interface 101, so as to simulate a user to wake up the dut 20 through a power-on key, and wake up the dut 20 from a sleep state to enter a power-on state. So that the power-on and sleep wake-up tests of the dut 20 can be implemented. The dut 20 is a general-purpose computer.

Specifically, the debug interface 101 is connected to the control unit 100 by 4 general purpose input/output (GPIO), the debug interface 101 is connected to the dut 20 through a connection terminal, which is a 2x 5K 10 Header, the connection terminal is connected to a chassis front panel connector of the dut 20, the chassis front panel connector includes four interfaces, which are PWR LEDs (power supply lamps): an indicator light for indicating the on-off state of the DUT 20; HDD LED (hard disk lamp): the indicating lamp is used for indicating the read-write state of the hard disk; PWR RST (power reset): for implementing a reset function; PWR BTN (power switch key). When the dut 20 is in the power-on state, the PWR LED will light up.

When the computer test apparatus 10 is used to test the power on/off of the dut 20, the power interface 102 is connected to the dut 20, and the control unit 100 can send a power signal to the dut 20 through the power interface 102, so that the dut 20 can be powered on to operate normally. Specifically, the power interface 102 is a 24pin power interface.

When the computer testing apparatus 10 is used to perform the wake-up test on the dut 20, the sleep wake-up interface 103 is connected to the dut 20, and the control unit 100 can send a wake-up signal to the dut 20 through the sleep wake-up interface 103 to wake up the dut 20 from the sleep state and enter the power-on state.

Specifically, the sleep wake-up interface 103 is a USB interface, the sleep wake-up interface 103 is connected to a USB interface in the dut 20, and the simulated keyboard in the control unit 100 simulates a user to wake up the dut 20 through a keyboard or a mouse, so as to implement the sleep wake-up test on the dut 20.

The computer test device 10 provided in the embodiment of the present application includes a control unit 100, a debug interface 101, a power interface 102, and a sleep wake-up interface 103; the debugging interface 101, the power interface 102 and the sleep awakening interface 103 are all used for being connected with the machine to be tested 20; the debug interface 101 is used for the control unit 100 to send a power-on signal or a wake-up signal to the dut 20 through the debug interface 101; the power interface 102 is used for the control unit 100 to send a power signal to the dut 20 through the power interface 102, so that the dut 20 operates normally; the sleep wake-up interface 103 is used for the control unit 100 to send a wake-up signal to the dut 20 through the sleep wake-up interface 103. The computer test device 10 provided in the embodiment of the present application can perform a power-on test and a wake-up test (simulate a wake-up operation of a power-on/off key) on the to-be-tested device 20 by connecting the debug interface 101 with the to-be-tested device 20; by connecting the power interface 102, an operating power can be supplied to the dut 20, so that the dut 20 can normally receive the control signal sent by the control unit 100. The sleep wake-up interface 103 is connected to the dut 20, so that a wake-up test (simulating a wake-up operation of a keyboard or a mouse) can be performed on the dut 20. When the computer testing device 10 provided by the embodiment is used for testing the to-be-tested device 20, an intelligent testing system with higher price is not needed, and the connection mode between the computer testing device 10 and the to-be-tested device 20 is simple and convenient to operate in the testing process. Moreover, the computer test device 10 provided in this embodiment can implement the power on/off test, the sleep wake-up test, and the sleep wake-up test for the device under test 20, and has high practicability.

In addition, when there are a plurality of debug interfaces 101, power interfaces 102, and sleep wake-up interfaces 103, a plurality of devices under test 20 can be tested simultaneously using the computer test apparatus 10 provided in the present application. The debugging interface 101, the power interface 102 and the sleep awakening interface 103 have different structures, have a fool-proof design, can avoid wrong insertion, and have higher practicability.

As shown in fig. 2, in one embodiment the power interface 102 includes a first interface 112 and a second interface 122, the first interface 112 is for connecting with the dut 20, and the second interface 122 is for connecting with the ATX power supply 11. That is, the control unit 100 may communicate the ATX power supply 11 with the dut 20 through the first interface 112 and the second interface 122. The ATX power supply 11 is a working power supply of the dut 20, and the ATX power supply 11 can convert 220V ac power of the commercial power into dc 5V, 12V, 5VAUX used inside the dut (power supplied to the motherboard of the dut 20 by the ATX power supply 11 when the dut 20 is in the shutdown state).

The control unit 100 receives the power signal of the ATX power source 11 through the first interface 112, and transmits the power signal to the dut 20 through the second interface 122, so as to provide the dut 20 with operating power, so that the dut 20 operates normally.

In this embodiment, the ATX power supply 11 is connected to the dut 20 through the control unit 100 via the first interface 112 and the second interface 122, and the control unit 100 can control the ATX power supply 11 to provide a power signal to the dut 20, so as to implement a power-on test of the dut 20 (a test in which the dut enters a power-on state when ac power is turned on).

In one embodiment, the computer test apparatus 10 provided in the embodiment of the present application is used to test the power on/off of the dut 20 (when the dut 20 is not powered on with 220V ac). Connecting the second interface 122 with the ATX power supply 11, wherein the ATX power supply 11 is connected with the commercial power; the first interface 112 is connected to the dut 20.

The control unit 100 sends a startup signal to the dut 20 through the debug interface 101; after receiving the power-ON signal, the dut 20 sends a power-ON (PS _ ON pull-down) signal to the control unit 100 through the first interface 112; the control unit 100 forwards the power-on signal to the ATX power supply 11. After receiving the power-on signal, the ATX power source 11 sends a power signal, and the power signal is transmitted to the dut 20 through the first interface 112, the control unit 100, and the second interface 122. After the ATX power supply 11 is powered on, a power-on complete (PWR _ OK) signal is sent to the control unit 100, the control unit 100 forwards the signal to the dut 20, and the dut 20 automatically enters a power-on state, thereby implementing a power-on test of the dut 20.

After the dut 20 receives the signal after the power-ON is completed, the dut 20 automatically turns off the power-off program and sends a power-off (PS _ ON pull-up) signal to the control unit 100 through the first interface 112. After receiving the power-down signal, the control unit 100 forwards the power-down signal to the ATX power supply 11, so that the ATX power supply 11 stops sending the power supply signal, and the dut 20 is in a shutdown state.

In this embodiment, the control unit 100 controls the ATX power supply 11 to send a power signal to the dut 20, so as to implement the power-on and power-off test of the dut 20. Therefore, in an actual scene, the alternating current of the to-be-tested device 20 is firstly switched on, and then the to-be-tested device 20 enters the starting-up process of the starting-up state through the starting-up key, so that the normal use scene of a user is met, and the to-be-tested device 20 can be tested more accurately. And repeating the above steps, the cycle test of the on/off of the device under test 20 can be realized.

In one embodiment, debug interface 101 is connected to dut 20 when dut 20 is turned on and off (dut 20 is always on with 220V ac during testing) using computer test apparatus 10 provided herein. The dut 20 is internally provided with a shutdown program.

The control unit 100 sends a startup signal to the dut 20 through the debug interface 101; after the dut 20 receives the signal to be powered on and enters the power on state, the dut 20 automatically executes the power off program, so that the dut 20 is in the power off state, and the power on/off test of the dut 20 is implemented. The control unit 100 may also receive a status signal (power-off status signal) of the dut 20.

In this embodiment, the control unit 100 sends a power-on signal to the dut 20 through the debug interface 101, so as to perform a power-on/off test on the dut 20. Therefore, the startup process of the to-be-tested device 20 entering the startup state through the startup and shutdown key after the to-be-tested device 20 is powered on in an actual application scene can be simulated, the normal use scene of a user is met, and the to-be-tested device 20 can be tested more accurately. And repeating the above steps, the cycle test of the on/off of the device under test 20 can be realized.

In a sleep wake-up test of the dut 20 using the computer test apparatus 10 provided in the present application, the debug interface 101 is connected to the dut 20. The dut 20 is internally provided with a sleep program.

The control unit 100 sends a startup signal to the dut 20 through the debug interface 101; after the dut 20 receives the power-on signal and the dut 20 enters the power-on state, the dut 20 automatically executes the hibernation program to put the dut 20 in the hibernation state. After the dut 20 is in the sleep state, the control unit 100 receives a state signal (sleep state signal) sent by the dut 20, sends a wake-up signal to the dut 20 through the debug interface 101 according to the state signal, wakes up the dut 20 from the sleep state, and makes the dut enter the power-on state, thereby implementing the sleep wake-up test on the dut 20.

In this embodiment, the control unit 100 sends a wake-up signal to the dut 20 through the debug interface 101, so that the dut 20 can be woken up from the sleep state. Therefore, the process of awakening the to-be-tested device 20 through the power on/off key in the dormant state of the to-be-tested device 20 in the actual application scene can be simulated, the common use scene of a user is met, and the to-be-tested device 20 can be tested more accurately. Repeating the above process can implement a cycle test of sleep wakeup of the dut 20.

In one embodiment, when the computer test apparatus 10 of the present application is used to test wake-up from sleep of the device under test 20, the debug interface 101 is connected to the device under test 20, and the wake-up-from-sleep interface 103 is connected to the device under test 20. The dut 20 is internally provided with a sleep program.

The control unit 100 sends a power-on signal to the dut 20 through the debug interface 101, and after the dut 20 receives the power-on signal and the dut 20 enters the power-on state, the dut 20 automatically executes the sleep program, so that the dut 20 is in the sleep state. After the dut 20 is in the sleep state, the control unit 100 receives a state signal (sleep state signal) sent by the dut 20, sends a wake-up signal to the dut 20 through the debug interface 101 according to the state signal, wakes up the dut 20 from the sleep state, and makes it enter the power-on state, thereby simulating the wake-up operation of the dut 20 by the user through the power-on/off key. Repeating the above process can implement a sleep wake-up cycle test for the dut 20.

After receiving the state signal (sleep state signal) sent by the dut 20, the control unit 100 may also send a wake-up signal to the dut 20 through the sleep wake-up interface 103 according to the state signal, so as to wake up the dut 20 from the sleep state and enable the dut to enter the power-on state, thereby simulating the wake-up operation of the dut 20 by the user through the mouse or the keyboard. The above process is repeated to realize the sleep awakening cycle test of the machine to be tested.

In this embodiment, the control unit 100 sends the wake-up signal to the to-be-tested device 20 through the debug interface 101, may wake up the to-be-tested device 20 from a sleep state, and may simulate a process of waking up the to-be-tested device 20 through the power on/off key in an actual application scene when the to-be-tested device 20 is in the sleep state; the control unit 100 sends a wake-up signal to the dut 20 through the sleep wake-up interface 103 to wake up the dut 20 from the sleep state, which may simulate a process of waking up the dut 20 through a keyboard or a mouse when the dut 20 is in the sleep state in an actual application scenario. Thus, the method conforms to the common use scene of the user, and can perform more accurate test on the device under test 20. Repeating the above process can implement a sleep wake-up cycle test for the dut 20.

Referring to FIG. 3, in one embodiment, the computer test device 10 further includes an expansion interface 104. The expansion interface 104 is used for connection to the expansion control unit 21. The expansion control unit 21 is provided with a sleep wake-up interface. The extension control unit 21 may be a single chip microcomputer, and the type of the extension control unit 21 may be the same as or different from that of the control unit 100, which is not limited in this application. There may be more than one expansion interface 104, and the embodiment is not limited thereto.

The extension interface 104 is used for the control unit 100 to send a wake-up signal to the dut 20 through the sleep wake-up interface on the extension control unit 21. In other words, the sleep wake-up interface on the extended control unit 21 is connected to the dut 20, and the control unit 100 may send the wake-up signal to the dut 20 through the sleep wake-up interface of the extended control unit 21.

In this embodiment, the control unit 100 can send the wake-up signal to the dut 20 through the expansion interface 104, so that the control unit 100 in the computer testing apparatus 10 can send the wake-up signal to the two duts 20 through the sleep wake-up interface 103 and the expansion interface 104 at the same time, when there are a plurality of expansion interfaces 104, the control unit 100 can send the wake-up signal to the plurality of duts 20 at the same time, thereby implementing the sleep wake-up test on the plurality of duts 20, and making the computer testing apparatus 10 have higher practicability.

With continued reference to FIG. 3, in one embodiment, the computer test device 10 further includes a test interface 105. The test interface 105 is used to interface with the dut 20. The number of the test interfaces 105 may be plural, and the embodiment is not limited thereto.

The test interface 105 is used for the control unit 100 to send a test signal to the dut 20 through the test interface 105, where the test signal is used to test the operating state of the dut 20. In other words, the test interface 105 is connected to the dut 20, and the control unit 100 may transmit the test signal to the dut 20 through the test interface 105. Specifically, the operating state of the dut 20 may refer to a voltage signal of the dut 20, an operating temperature of a motherboard of the dut 20, or a rotation speed of a fan of the dut 20. That is, the test signal may be used to implement a test of the voltage signal of the dut 20; the test signal can also be used for testing the working temperature of the mainboard of the to-be-tested device 20; the test signal may also be used to implement a test of the rotational speed of the fan in the dut 20, and the like. The specific test of the working state of the dut 20 may be set according to the actual application scenario, which is not limited in this example.

In this embodiment, the control unit 100 can test the operating state of the dut 20 through the test interface 105, and can expand the functions of the computer test apparatus 10, thereby improving the practicability of the computer test apparatus 10.

In a specific embodiment, the test interface 105 comprises a 5-way unit AD acquisition channel, 8 GPIO bidirectional pins, two UART serial ports, and an I2C interface. The test interface 105 is connected with the control unit 100 through 16 GPIOs.

With continued reference to FIG. 3, in one embodiment, the computer test apparatus 10 further comprises a first memory cell interface 106. The first storage unit interface 106 is used to connect with the first storage unit 22. The first storage unit 22 may be an SD card, and the present embodiment does not limit the kind of the first storage unit 22.

The first storage unit interface 106 is used for the control unit 100 to send information to be stored to the first storage unit 22 through the first storage unit interface 106. In other words, by connecting the first storage unit interface 106 with the first storage unit 22, the control unit 100 can transmit information to be stored to the first storage unit 22 through the first storage unit interface 106.

Specifically, when the computer test apparatus 10 is used to perform the power on/off test, the sleep wake-up test, and the sleep wake-up test on the device under test 20, the control unit 100 may store information of the tests (test times, test time, test results, etc.) in the first storage unit 22 through the first storage unit interface 106.

In this embodiment, by setting the first storage unit interface 106 connected to the first storage unit 22, the information of various tests performed on the dut 20 by the computer testing apparatus 10 can be stored, so that when a test fails, a worker can locate and analyze the failure by reading the information in the first storage unit 22 by using the SPI protocol, and the practicability of the computer testing apparatus 10 can be improved.

With continued reference to FIG. 3, in one embodiment, the computer test apparatus 10 further comprises a second storage unit interface 107. The second storage unit interface 107 is used to connect with the second storage unit 23. The second storage unit 23 may be a 16-bit SDRAM chip, and the embodiment does not limit the specific kind of the second storage unit 23.

The second storage unit interface 107 is used for the control unit 100 to execute the program in the second storage unit 23 through the second storage unit interface 107. In other words, by connecting the second storage unit interface 107 with the second storage unit 23, the control unit 100 can execute the program in the second storage unit 23.

In this embodiment, by providing the second storage unit interface 107 connected to the second storage unit 23, the problem of insufficient internal storage space of the control unit 100 can be compensated, so that a large file can be processed by using the computer test apparatus 10, and the practicability of the computer test apparatus 10 is improved.

With continued reference to FIG. 3, in one embodiment, the computer test device 10 further includes a display unit interface 108. The display unit interface 108 is used to interface with the display unit 24. The display unit 24 may be a display liquid crystal panel, and the present embodiment does not limit the kind of the display unit 24.

The display unit interface 108 is used for the control unit 100 to send information to be displayed to the display unit 24 through the display unit interface 108. In other words, the display unit interface 108 is connected with the display unit 24, and the control unit 100 can transmit information to be displayed to the display unit 24 through the display unit interface 108.

In this embodiment, by providing the display unit interface 108 connected to the display unit 24, the information of various tests performed on the dut 20 by the computer test apparatus 10 can be displayed, for example, the number of tests, the test time, the test result, the voltage signal of the dut 20, the operating temperature of the motherboard of the dut 20, the rotation speed of the fan of the dut 20, and the like are displayed, so that the functions of the computer test apparatus 10 can be expanded, and the practicability of the computer test apparatus 10 can be improved.

With continued reference to fig. 3, in one embodiment, the computer test apparatus 10 further includes a network interface 109, and the network interface 109 is used for connecting with the dut 20. The present embodiment does not limit the kind, number, and the like of the network interfaces 109. In one particular embodiment, the network interfaces are 10M and 100M network interfaces (RJ45) of the RMII protocol.

The network interface 109 is used for the control unit 100 to send a control signal to the dut 20 through the network interface 109. In other words, the network interface 109 is connected to the dut 20, and the remote control device can send a control signal to the dut 20 through the network interface 109 on the control unit 100. The control signal may be a power-on signal, a wake-up signal, etc. That is, in this embodiment, the computer test apparatus 10 can remotely control the dut 20 through the network interface 109, thereby expanding the functions of the computer test apparatus 10 and improving the practicability of the computer test apparatus 10.

With continued reference to FIG. 3, in one embodiment, the computer test device 10 further includes a key matrix interface 110. The key matrix interface 110 is used for connecting with the dut 20. Specifically, the key matrix interface 110 is connected to the control unit 100 through 8 GPIOs.

The key matrix interface 110 is used for the control unit 100 to send an information setting signal to the dut 20 through the key matrix interface 110. In other words, the key matrix interface 110 is connected to the dut 20, and the control unit 100 may transmit the information setting signal to the dut 20 through the key matrix interface 110. Specifically, the information setting signal may be an IP address setting signal or a time and date setting signal, that is, the control unit 100 may set an IP address or time and date of the device under test 20 through the key matrix interface 110. The present embodiment does not limit the type of the information setting signal, and the user can select the information setting signal according to the actual application scenario.

In this embodiment, by providing the key matrix interface 110 connected to the dut 20, information of the dut 20 can be set, so that the functions of the computer test apparatus 10 are expanded, and the practicability of the computer test apparatus 10 is improved.

In an alternative embodiment, the computer test apparatus 10 further comprises a power supply interface, wherein the power supply interface is used for connecting with an ac power supply, and the ac power supply supplies power to the control unit 100 through the power supply interface to ensure the normal operation of the control unit 100.

In an optional embodiment, the computer testing apparatus 10 further includes a backup power supply interface, where the backup power supply interface is configured to be connected to an ac power source, and the backup power supply interface is configured to supply power to the control unit 100 through the backup interface when the power supply interface fails, so as to ensure that the control unit 100 can work normally.

In an optional embodiment, the computer test apparatus 10 further includes a tooling board, and the control unit 100, the debugging interface 101, the power interface 102, the sleep wake-up interface 103, the expansion interface 104, the test interface 105, the first storage unit interface 106, the second storage unit interface 107, the display unit interface 108, the network interface 109, and the key matrix interface 110 may be mounted on the tooling board.

In an alternative embodiment, the computer test apparatus 10 further comprises a plurality of function keys, each function key corresponding to a test function that the computer test apparatus 10 can implement. Specifically, the computer test device comprises an AC test key, a DC test key, a dormancy awakening test key and a reset key. By operating the AC test key, the control unit 100 starts the AC power on/off test on the dut 20, that is, the control unit 100 controls the ATX power supply 11 to provide the power signal to the dut 20, so that the dut 20 enters the power on or power off state. By operating the DC test key, the control unit 100 starts a DC power on/off test on the device under test 20, that is, after the device under test 20 switches on the ac power, the device under test 20 enters a power on state by simulating the operation of the switch key; by operating the sleep wake-up button, the control unit 100 starts to perform a sleep wake-up test on the dut 20; by operating the sleep wake-up button, the control unit 100 starts to perform the sleep wake-up operation on the dut 20; by operating the reset key, the control unit 100 can stop the program executed at this time, and the computer test apparatus 10 can be restored to the initial state. Therefore, the control unit 100 can realize the functions thereof through key operation, and the control unit 100 is not required to be externally connected with other equipment for parameter setting, so that the operation is simple.

In one embodiment, the computer test apparatus 10 further comprises a program burning interface (GD32F450IK) through which a program can be written into the internal memory of the control unit 100.

As shown in fig. 4, an embodiment of the present application provides a computer testing method, which is used in the computer testing apparatus provided in the above embodiment. The computer test method comprises the following steps:

step 400, the control unit sends a power-on signal to the dut through the debug interface, where the power-on signal is used to instruct the dut to execute a power-off program or a sleep program, so that the dut is in a power-off state or a sleep state.

Step 410, when the dut is in the sleep state, the control unit sends a wake-up signal to the dut through the debug interface, so that the dut is in the power-on state.

The computer test method provided by the embodiment can realize the on-off test (the to-be-tested machine is always connected with 220V alternating current in the test process) and the dormancy awakening test of the to-be-tested machine. For a specific description of the computer testing method, reference may be made to the description in the above embodiment of the computer testing apparatus, and details are not repeated here. The computer test method is used in a computer test device, and the method has the beneficial effects of the computer test device, and is not described herein again.

As shown in fig. 5, in an embodiment, the power-on signal is further used to instruct the dut to send a power-on signal to the control unit, and the method further includes:

step 500, the control unit sends a power-on signal to the ATX power supply through the second interface, where the power-on signal is used to instruct the ATX power supply to send a power signal, so that the power supply to be tested is in a power-on state; the power supply signal is used for indicating the to-be-tested machine to execute a shutdown program and sending a power-off signal to the control unit;

and step 510, the control unit sends a power-down signal to the ATX power supply through the second interface, wherein the power-down signal is used for indicating the ATX power supply to stop sending the power supply signal, so that the machine to be tested is in a shutdown state.

The computer test method provided by the embodiment can realize the on-off test of the to-be-tested machine (before the test is started, the to-be-tested machine is not switched on with 220V alternating current). For a specific description of the computer testing method, reference may be made to the description in the above embodiment of the computer testing apparatus, and details are not repeated here. The computer testing method is used in the computer testing device, and the method has the beneficial effects of the computer testing device, and is not repeated herein.

As shown in fig. 6, in an embodiment, the power-on signal is further used to instruct the dut to execute a sleep program, so that the dut is in a sleep state, and the method further includes:

step 600, the control unit sends a wake-up signal to the to-be-tested machine through the sleep wake-up interface so as to enable the to-be-tested machine to be in a starting state;

step 610, the control unit sends a wake-up signal to the dut through the debug interface, so that the dut is in a power-on state.

The computer test method provided by the embodiment can realize the sleep wake-up test of the to-be-tested computer. For a specific description of the computer testing method, reference may be made to the description in the above embodiment of the computer testing apparatus, and details are not repeated here. The computer testing method is used in the computer testing device, and the method has the beneficial effects of the computer testing device, and is not repeated herein.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A computer test device is characterized by comprising a control unit, a debugging interface, a power interface and a sleep awakening interface;

the debugging interface, the power supply interface and the sleep awakening interface are all used for being connected with a machine to be tested;

the power interface is used for the control unit to send a power signal to the machine to be tested through the power interface so as to enable the machine to be tested to work normally;

and the sleep awakening interface is used for the control unit to send the awakening signal to the machine to be tested through the sleep awakening interface.

2. The computer test apparatus of claim 1, wherein the power interface comprises a first interface and a second interface, the first interface is configured to connect to the dut, and the second interface is configured to connect to an ATX power supply;

3. The computer test apparatus of claim 2,

the control unit is used for sending a starting-up signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to a starting-up and shutdown test; the starting signal is used for indicating the to-be-tested machine to send a power-on signal to the control unit through the first interface;

the control unit is further configured to send the power-on signal to the ATX power supply through the second interface, where the power-on signal is used to instruct the ATX power supply to send a power signal, so that the device under test is in a power-on state; the power supply signal is used for indicating the to-be-tested machine to execute a shutdown program and sending a power-off signal to the control unit through the first interface;

the control unit is further configured to send the lower electric signal to the ATX power supply through the second interface, where the lower electric signal is used to instruct the ATX power supply to stop sending a power signal, so that the to-be-tested device is in a shutdown state.

4. The computer test apparatus of claim 1,

the control unit is used for sending a starting-up signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to a power-on and power-off test or a dormancy awakening test; the starting signal is used for indicating the to-be-tested machine to execute a shutdown program or a dormant program so as to enable the to-be-tested machine to be in a shutdown state or a dormant state;

the control unit is further configured to send a wake-up signal to the to-be-tested device through the debugging interface when the to-be-tested device is in the dormant state, so that the to-be-tested device is in a power-on state;

the control unit is also used for receiving the state signal sent by the machine to be tested.

5. The computer test apparatus of claim 1,

the control unit is used for sending a starting-up signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is subjected to sleep awakening test; the starting signal is used for indicating the machine to be tested to execute a sleep program so as to enable the machine to be tested to be in a sleep state;

the control unit is also used for sending a wake-up signal to the to-be-tested machine through the sleep wake-up interface; or sending the wake-up signal to the to-be-tested machine through the debugging interface so as to enable the to-be-tested machine to be in a starting state;

6. The computer test apparatus of claim 1, further comprising: the expansion interface is used for being connected with the expansion control unit;

the extended interface is used for the control unit to send a wake-up signal to the to-be-tested device through the sleep wake-up interface on the extended control unit.

7. The computer test apparatus of claim 1, further comprising: the first storage unit interface is used for being connected with the first storage unit;

the first storage unit interface is used for the control unit to send information to be stored to the first storage unit through the first storage unit interface.

8. A computer test method for use in a computer test apparatus as claimed in any one of claims 1 to 7, the method comprising:

the control unit sends a starting-up signal to the to-be-tested machine through the debugging interface, wherein the starting-up signal is used for indicating the to-be-tested machine to execute a shutdown program or a dormant program so as to enable the to-be-tested machine to be in a shutdown state or a dormant state;

and the control unit sends a wake-up signal to the to-be-tested machine through the debugging interface when the to-be-tested machine is in a dormant state, so that the to-be-tested machine is in a starting state.

9. The method of claim 8, wherein the power-on signal is further configured to instruct the device under test to send a power-on signal to the control unit, the method further comprising:

the control unit sends the power-on signal to the ATX power supply through a second interface, and the power-on signal is used for indicating the ATX power supply to send a power supply signal so as to enable the power supply to be tested to be in a starting state; the power supply signal is used for indicating the to-be-tested machine to execute a shutdown program and sending a power-down signal to the control unit;

the control unit sends the lower electric signal to the ATX power supply through the second interface, and the lower electric signal is used for indicating the ATX power supply to stop sending the power signal so as to enable the machine to be tested to be in the shutdown state.

10. The method of claim 8, wherein the power-on signal is further configured to instruct the dut to execute a sleep program so that the dut is in a sleep state, and wherein the method further comprises:

or the control unit sends the wake-up signal to the to-be-tested machine through the debugging interface so as to enable the to-be-tested machine to be in the starting-up state.