CN107656856B - CPLD-based system state display method and device - Google Patents
CPLD-based system state display method and device Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
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Abstract
The invention provides a CPLD-based system state display method and device, wherein the method comprises the following steps: monitoring the BMC activation state through the CPLD; when the BMC is not activated, sending system state information acquired by the PCH to the CPLD, wherein the CPLD performs LPC decoding on the system state information, and outputs the decoded system state information through a simulated UART interface for display; and when the BMC is activated, sending the system state information acquired by the PCH to the BMC, carrying out LPC decoding on the system state information by the BMC, outputting the decoded system state information through an SYS UART interface, and displaying the decoded system state information. The invention selects the CPLD chip to assist the BMC to output the UART interface of the system, analyzes the GPIO, LPC and UART and detects the related signals of the peripheral chip and outputs the signals through the simulation UART interface, thereby more comprehensively collecting the state information.
Description
Technical Field
The invention relates to the technical field of computer servers, in particular to a CPLD-based system state display method and device.
Background
With the development of information technology, the application of servers is more and more extensive, the performance of servers is also continuously upgraded, BMC (Baseboard Management Controller) is used as a main control chip and a monitoring chip in a server system, the work performed by BMC is more and more, and more information needs to be collected and monitored.
Because the number of logic units and pin pins of the BMC is limited, a rapidly changing system signal cannot be captured, and because the BMC needs certain starting time and restarting operation limitation, the whole system cannot be monitored and controlled in real time at a certain time point; moreover, the BMC has more monitoring and management functions and larger load, so that certain influence is brought to the monitoring and controllability of the system by utilizing the BMC.
Therefore, the system status cannot be completely monitored and displayed by only using the BMC.
Disclosure of Invention
The invention aims to provide a CPLD-based system state display method and device, which aim to solve the problem that a BMC in a server system cannot monitor and control the whole system in real time in the whole process, and realize the purpose of utilizing the CPLD to assist the BMC in monitoring and controlling the system.
In order to achieve the technical purpose, the invention provides a system state display method based on a CPLD, which comprises the following steps:
monitoring the BMC activation state through the CPLD;
when the BMC is not activated, sending system state information acquired by the PCH to the CPLD, wherein the CPLD performs LPC decoding on the system state information, and outputs the decoded system state information through a simulated UART interface for display;
and when the BMC is activated, sending the system state information acquired by the PCH to the BMC, carrying out LPC decoding on the system state information by the BMC, outputting the decoded system state information through an SYS UART interface, and displaying the decoded system state information.
Preferably, the system state information includes progress, temperature, and debug Port of the BIOS fetch code.
Preferably, the analog UART interface is obtained by simulating a GPIO interface of the CPLD.
Preferably, the CPLD also monitors system state information of the CPU and VR.
The embodiment of the invention also provides a system state display device based on the CPLD, which comprises the CPLD, the BMC and the PCH;
the CPLD comprises a GPIO interface, an LPC interface and an analog UART interface, the GPIO interface is connected to a UART interface of the BMC, the LPC interface is connected to an LPC interface of the PCH, and the analog UART interface is connected to a DEBUG COM printing interface;
the LPC interface of the BMC is connected to the LPC interface of the PCH, the PCIE interface is connected to the PCH, and the SYS UART interface is connected to the SYS COM printing interface.
Preferably, system state information is transmitted between the CPLD and the PCH, and the system state information includes progress, temperature, and debug Port of the bios fetch code.
Preferably, the analog UART interface is obtained by simulating a GPIO interface of the CPLD.
Preferably, the device further comprises a CPU and a VR, and the CPU and the VR are respectively connected with the CPLD.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, the invention utilizes the CPLD to assist the BMC in system monitoring and management, and more comprehensively collects state information. The starting time of the CPLD is far earlier than that of other chips including the BMC, so that the starting time of the BMC is not required to be considered; the CPLD can detect nanosecond-level signals, so that the problem that the BMC cannot capture fast signals due to slow monitoring time is perfectly solved; in addition, as the CPLD resources and the pin are enough, the problem that the BMC resources and the pin are not enough is solved; finally, the BMC cannot monitor the system when restarting or burning, but has no influence on the CPLD, and the CPLD is relatively stable.
Drawings
Fig. 1 is a flowchart of a CPLD-based system state display method provided in an embodiment of the present invention;
fig. 2 is a block diagram of a CPLD-based system state display device according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
The method and the device for displaying the system state based on the CPLD according to the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present invention discloses a CPLD-based system state display method, including:
monitoring the BMC activation state through the CPLD;
when the BMC is not activated, sending system state information acquired by the PCH to the CPLD, wherein the CPLD performs LPC decoding on the system state information, and outputs the decoded system state information through a simulated UART interface for display;
and when the BMC is activated, sending the system state information acquired by the PCH to the BMC, carrying out LPC decoding on the system state information by the BMC, outputting the decoded system state information through an SYS UART interface, and displaying the decoded system state information.
The main chip components in the server mainly include a CPU, a BMC, a CPLD (Complex programmable logic Device), a VR (Voltage Regulator), a COM interface, and a PCH (Platform Controller Hub).
The power management of each core chip in the system is completed by VR, the CPLD controls the power-on time sequence of the whole system, after the CPLD is powered on, the CPU starts the fetch code from the PCH through the DMI bus and configures the internal register of the CPU, so that the whole system starts to work.
The BMC acquires other information in the system from the PCH through the PCIE interface and the LPC interface, wherein the information comprises progress, temperature, debug Port and the like of the BIOSfetch code, and the information is stored in the ROM after the BMC is activated and is transmitted to the SYS COM interface through the SYSUATR interface to be printed. However, since the BMC itself needs a certain startup time and a limitation of the restart operation, the BMC has a certain influence on monitoring the system state information during the time before the startup.
In the embodiment of the invention, the main chips of the server are connected with the CPLD according to the connection mode shown in FIG. 2, the signals of all chip components are transmitted to the CPLD, and the internal monitoring module of the CPLD processes different functional signals and latches the signals into the internal register, so that the system state in the system can be monitored.
After the system is powered on, the CPLD is activated to start to collect system state information and print and display the system state information, simultaneously the CPLD monitors the BMC activation state, and the system state information monitored by the BMC is transmitted to the CPLD for system state monitoring according to the activation state of the BMC:
the GPIO interface of the CPLD is connected with the UART interface of the BMC, so that the BMC state is monitored, and whether the BMC is activated or not is judged.
When the BMC is not activated, transmitting system signals acquired from the PCH and originally monitored by the BMC, including progress, temperature, DEBUG Port and the like of the BIOSfetch code to the CPLD, analyzing the system state information by the CPLD through an internal LPC decoding module to obtain corresponding information, simulating the GPIO by the CPLD to obtain a UART interface, outputting the analyzed system state information to a DEBUG COM printing interface through a simulated UART interface, printing and displaying related system prompt information.
When the BMC is activated, the CPLD does not share the monitoring task of the BMC any more, the BMC receives a part of LPC signals through an LPC protocol interface, and receives system signals acquired from the PCH through a PCIE interface, wherein the system signals comprise the progress, the temperature, the debug Port and the like of the BIOS fetch code, and the system state information is transmitted to an SYS UART interface in the BMC, is output to an SYS COM printing interface for printing and displays related system prompt information.
According to the invention, the CPLD chip is selected to assist the BMC to output the UART interface of the system, the GPIO, the LPC, the UART and the related signals of the detection peripheral chip are analyzed and output through the simulation UART interface, so that different prompt information is displayed, and meanwhile, the activation state of the BMC is monitored, and when the BMC is not activated, the system state information received by the BMC is output, so that the state information is collected more comprehensively.
The starting time of the CPLD is far earlier than that of other chips including the BMC, so that the starting time of the BMC is not required to be considered; the CPLD can detect nanosecond-level signals, so that the problem that the BMC cannot capture fast signals due to slow monitoring time is perfectly solved; in addition, as the CPLD resources and the pin are enough, the problem that the BMC resources and the pin are not enough is solved; finally, the BMC cannot monitor the system when restarting or burning, but has no influence on the CPLD, and the CPLD is relatively stable.
The embodiment of the invention also discloses a system state display device based on the CPLD, which comprises the CPLD, the BMC and the PCH as shown in figure 2.
The CPLD comprises a GPIO interface, an LPC interface and an analog UART interface, the GPIO interface is connected to a UART interface of the BMC, the LPC interface is connected to an LPC interface of the PCH, and the analog UART interface is connected to a DEBUG COM printing interface.
The LPC interface of the BMC is connected to the LPC interface of the PCH, the PCIE interface is connected to the PCH, and the SYS UART interface is connected to the SYS COM printing interface.
The GPIO interface of the CPLD is connected with the UART interface of the BMC, so that the BMC state is monitored, and whether the BMC is activated or not is judged.
When the BMC is not activated, transmitting system signals acquired from the PCH and originally monitored by the BMC, including progress, temperature, DEBUG Port and the like of the BIOSfetch code to the CPLD, analyzing the system state information by the CPLD through an internal LPC decoding module to obtain corresponding information, simulating the GPIO interface by the CPLD to obtain a UART interface, and outputting the analyzed system state information to a DEBUG COM printing interface through a simulated UART interface for printing.
When the BMC is activated, the CPLD does not share the monitoring task of the BMC any more, the BMC receives a part of LPC signals through an LPC protocol interface, and receives system signals acquired from the PCH through a PCIE interface, wherein the system signals comprise the progress, the temperature, the debug Port and the like of the BIOS fetch code, and the system state information is transmitted to an SYS UART interface in the BMC, is output to an SYS COM printing interface for printing and displays related system prompt information.
The device also comprises a CPU and a VR, wherein the CPU and the VR are respectively connected with a monitor of the CPLD, so that the system information of other main chips in the CPLD monitoring system is realized.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A CPLD-based system state display method is characterized by comprising the following steps:
monitoring the BMC activation state through the CPLD; the monitoring of the BMC activation state through the CPLD is to monitor the BMC state by connecting a GPIO interface of the CPLD with a UART interface of the BMC and judge whether the BMC is activated;
when the BMC is not activated, sending system state information acquired by the PCH to the CPLD, wherein the CPLD performs LPC decoding on the system state information, and outputs the decoded system state information through a simulated UART interface for display;
and when the BMC is activated, sending the system state information acquired by the PCH to the BMC, carrying out LPC decoding on the system state information by the BMC, outputting the decoded system state information through an SYS UART interface, and displaying the decoded system state information.
2. The CPLD-based system state display method of claim 1, wherein the system state information includes progress, temperature and debug Port of BIOS fetch code.
3. The CPLD-based system state display method according to claim 1, wherein the simulated UART interface is obtained by simulating a GPIO interface of a CPLD.
4. The CPLD-based system status display method of claim 1, wherein the CPLD also monitors the system status information of the CPU and VR.
5. A system state display device based on CPLD is characterized by comprising a CPLD, a BMC and a PCH;
the CPLD comprises a GPIO interface, an LPC interface and an analog UART interface, the GPIO interface is connected to a UART interface of the BMC, the LPC interface is connected to an LPC interface of the PCH, and the analog UART interface is connected to a DEBUG COM printing interface;
the LPC interface of the BMC is connected to the LPC interface of the PCH, the PCIE interface is connected to the PCH, and the SYS UART interface is connected to the SYS COM printing interface.
6. The CPLD-based system status display device according to claim 5, wherein system status information is transmitted between the CPLD and the PCH, and the system status information includes the progress, temperature and debug Port of the BIOS fetch code.
7. The CPLD-based system state display device according to claim 5, wherein the simulated UART interface is obtained by simulating a GPIO interface of the CPLD.
8. The CPLD-based system status display device according to claim 5, wherein the device further comprises a CPU and a VR, the CPU and VR are respectively connected with the CPLD.
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| CN108845913A (en) * | 2018-06-19 | 2018-11-20 | 郑州云海信息技术有限公司 | A kind of diagnostic card of system and its I/O state for obtaining CPLD |
| CN109032678B (en) * | 2018-07-18 | 2020-07-07 | 苏州浪潮智能科技有限公司 | Method, apparatus, medium, and method for controlling amount of BIOS print information |
| CN109062828A (en) * | 2018-07-19 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of CPLD and storage control circuit |
| CN109120143B (en) * | 2018-07-25 | 2021-08-10 | 郑州云海信息技术有限公司 | Method, main controller and system for controlling power on and power off |
| CN109308244A (en) * | 2018-09-13 | 2019-02-05 | 郑州云海信息技术有限公司 | A kind of display methods, system and the associated component of BMC module state |
| CN111679948B (en) * | 2019-03-11 | 2023-08-15 | 深圳富联富桂精密工业有限公司 | Hard disk state monitoring system and method thereof |
| CN114077566B (en) * | 2020-08-20 | 2023-10-13 | 富联精密电子(天津)有限公司 | System and method for data processing between upper computer and CPLD |
| CN112363894A (en) * | 2020-11-09 | 2021-02-12 | 北京计算机技术及应用研究所 | Domestic computer fault alarm system |
| CN113204466B (en) * | 2021-04-29 | 2022-11-18 | 山东英信计算机技术有限公司 | Over-temperature protection method and electronic equipment |
| CN114817096B (en) * | 2022-04-08 | 2023-07-25 | 苏州浪潮智能科技有限公司 | System, method, equipment and computer readable medium for switching serial ports of BMC and BIOS |
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| CN102722232B (en) * | 2012-05-30 | 2016-09-21 | 曙光信息产业(北京)有限公司 | Control system that a kind of ATCA blade powers on and method |
| CN103970635A (en) * | 2014-04-28 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Server hardware fault self-diagnosis method |
| CN104516434B (en) * | 2014-12-11 | 2018-03-30 | 曙光云计算集团有限公司 | Server system |
| CN104375915A (en) * | 2014-12-16 | 2015-02-25 | 浪潮电子信息产业股份有限公司 | Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing |
| CN104572226A (en) * | 2015-02-04 | 2015-04-29 | 浪潮(北京)电子信息产业有限公司 | Method and device for detecting mainboard starting abnormity |
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