CN114489502B - Parallel RAM-based data array management method and device and storage equipment - Google Patents
Parallel RAM-based data array management method and device and storage equipment Download PDFInfo
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- 238000007726 management method Methods 0.000 title claims abstract description 46
- 238000013523 data management Methods 0.000 claims abstract description 35
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The embodiment of the application discloses a data array management method based on parallel RAM, which comprises the following steps: receiving a data management request, and determining a request type and a feature address corresponding to the data management request; inquiring the storage state of a corresponding storage unit of the characteristic address in each RAM; and executing corresponding processing on each RAM according to the request type. The embodiment of the application also discloses a data array management device and a storage device based on the parallel RAM.
Description
Technical Field
The present disclosure relates to memory management technologies, and in particular, to a method, an apparatus, and a storage device for managing a data array based on parallel RAM.
Background
In practical application, with the increasing flexible demands of data caching function, the application of the data array storage module is wider, and based on the parallel random access memory (Random Access Memory), the data array storage formed by the RAM blocks can effectively solve the RAM write address conflict situation, so the demand of the realization method for supporting and efficiently managing and controlling the RAM is more obvious.
In order to meet the data array management composed of a plurality of RAMs, currently, the main stream practice in the industry is to instantiate each RAM, and the upper layer controls the RAMs according to specific requirements, so that each independent RAM block corresponds to a set of complete control module, but the resource waste is caused, and the control efficiency is reduced; at present, a technical scheme for simultaneously controlling multiple RAMs and independently controlling and distinguishing read-write of each RAM is not available.
Disclosure of Invention
The embodiment of the application provides a data array management method based on parallel RAM, which comprises the following steps:
receiving a data management request, and determining a request type and a feature address corresponding to the data management request;
inquiring the storage state of a corresponding storage unit of the characteristic address in each RAM;
and executing corresponding processing on each RAM according to the request type.
In some embodiments, when the request type corresponding to the data management request is a cache data request, the executing, according to the request type, a corresponding process on each RAM includes:
and writing the cache data into the storage unit with at least one writable storage state corresponding to the characteristic address.
In some embodiments, when the request type corresponding to the data management request is a query data request, the executing, according to the request type, a corresponding process on each RAM includes:
reading the data content of the storage unit of each RAM corresponding to the query address;
outputting the data content which is non-writable in the storage state of the corresponding storage unit;
and outputting the data content 0 with the storage state of the corresponding storage unit being writable.
In some embodiments, when the request type corresponding to the data management request is a clear data request, the executing, according to the request type, a corresponding process on each RAM includes:
and setting the storage state of the storage unit corresponding to the characteristic address to be writable.
In some embodiments, the method further comprises:
correspondingly storing the storage state of each storage unit of each RAM in a two-dimensional array Bitmap;
the step of inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM comprises the following steps: and inquiring the storage state of each corresponding storage unit in each RAM of the characteristic address stored in the Bitmap.
The embodiment of the application provides a data array management device based on parallel RAM, which comprises:
the receiving and transmitting module is used for receiving a data management request and determining a request type and a characteristic address corresponding to the data management request;
the control module is used for inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM;
and the processing module is used for executing corresponding processing on each RAM according to the request type.
In some embodiments, when the request type corresponding to the data management request is a cache data request, the processing module is specifically configured to:
and writing the cache data into the storage unit with at least one writable storage state corresponding to the characteristic address.
In some embodiments, when the request type corresponding to the data management request is a query data request, the processing module is specifically configured to:
reading the data content of the storage unit of each RAM corresponding to the query address;
outputting the data content which is non-writable in the storage state of the corresponding storage unit;
and outputting the data content 0 with the storage state of the corresponding storage unit being writable.
In some embodiments, when the request type corresponding to the data management request is a clear data request, the processing module is specifically configured to:
and setting the storage state of the storage unit corresponding to the characteristic address to be writable.
The embodiment of the application discloses a storage device, comprising: a data array composed of more than two RAMs in parallel and any one of the data array management devices based on the parallel RAMs for managing the data array.
In the technical scheme of the embodiment of the application, a request type and a characteristic address corresponding to a data management request are determined by receiving the data management request; inquiring the storage state of a corresponding storage unit of the characteristic address in each RAM; and executing corresponding processing on each RAM according to the request type. The read-write address line of each RAM in the data array of the parallel RAMs is shared; by inquiring the storage state of the corresponding storage unit in each RAM, independent read-write control distinction can be carried out on each RAM, and unified control and management of a plurality of RAMs in parallel are realized.
Drawings
The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
FIG. 1 is a flow chart of a data array management method based on parallel RAM according to an embodiment of the present application;
FIG. 2a is an exploded flow chart of step 103 in the parallel RAM-based data array management method of FIG. 1;
FIG. 2b is an exploded flowchart of step 103 in the parallel RAM-based data array management method of FIG. 1;
FIG. 2c is an exploded flowchart of step 103 in the parallel RAM-based data array management method of FIG. 1;
FIG. 3 is a schematic diagram of a parallel RAM-based data array management method according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a data array management device based on parallel RAM according to an embodiment of the present application.
Detailed Description
For a more complete understanding of the nature and the technical content of the embodiments of the present application, reference should be made to the following detailed description of embodiments of the present application in connection with the accompanying drawings, which are provided for purposes of illustration only and are not intended to limit the embodiments of the present application.
For a more complete understanding of the features and technical content of the embodiments of the present application, reference should be made to the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings, which are for purposes of illustration only and not intended to limit the embodiments of the present application.
In the description of the embodiments of the present application, it should be noted that, the term "first\second\third" related to the embodiments of the present application is merely to distinguish similar objects, and does not represent a specific ordering for the objects, and it is understood that "first\second\third" may interchange a specific order or sequence where allowed. It is to be understood that the "first\second\third" distinguishing objects may be interchanged where appropriate such that the embodiments of the present application described herein may be implemented in sequences other than those illustrated or described herein.
It is understood that the parallel RAM-based data array in the embodiments of the present application includes a data array composed of two or more RAMs in parallel. The technical scheme is not limited to the specific number of the RAMs, and the technical scheme can be realized by more than 2 RAMs.
The RAM in the present application may include physical RAM, such as RAM in a chip, or RAM in a hardware system of a computer, a removable electronic device, or the like; virtual RAM, such as RAM emulated in a virtual software environment such as a virtual machine, may also be included.
Fig. 1 is a flow chart of a parallel RAM-based data array management method according to an embodiment of the present application, as shown in fig. 1, a parallel RAM-based data array management method 100 according to an embodiment of the present application includes:
step 101, a data management request is received, and a request type and a feature address corresponding to the data management request are determined.
In this embodiment of the present application, the request types corresponding to the data management request may include: cache data requests, query data requests, or flush data requests.
The feature address may be a feature bit field or an upper-level path indication in the data, and in this embodiment of the present application, the feature address may be used to match address information of a corresponding storage unit of the data corresponding to the request type in the data array of the parallel RAM.
Caching a data request, namely caching the data and managing the data; in some embodiments, the cache data request may specifically include cache data; the cache data can be sent to the data array from outside, or can be actively obtained from outside by the data array management end; the feature address may be a field contained in the cache data, and may be obtained by parsing the cache data; the address data may also be address data corresponding to the cache data, for example, in some embodiments, the feature address corresponding to the cache data is obtained by means of matching a query, where the feature address is not directly written into the cache data, but is obtained by means of separate sending or active acquisition.
The query data request may include a data fetch access query to a data array of the parallel RAM, and correspondingly, the feature address may include a query address corresponding to a memory location address in the data array of the target parallel RAM.
The flush data request may include a release of a memory function for at least a portion of the memory cells in the data array of the parallel RAM, i.e., setting the memory state of at least a portion of the memory cells in the data array of the parallel RAM to a writable state, and correspondingly, the feature address may include a query address corresponding to the memory cells for which the flush data request is to release the memory function.
Step 102, the storage state of the corresponding storage unit of the characteristic address in each RAM is queried.
It will be appreciated that a parallel RAM based data array is made up of multiple RAMs in parallel; the portion of the RAM responsible for storing data is the memory matrix, which is made up of a large array of memory cells. In some embodiments, the number of storage units of the plurality of RAMs is the same, and the same feature address can be matched with a corresponding storage unit in each RAM, for example, a data array consisting of 8 RAMs in parallel, and then the same feature address can be matched with 8 storage units; in some embodiments, the number of memory locations of the plurality of RAMs is not exactly the same, and the same feature address can be matched to at least more than one memory location.
In some embodiments, the above method further comprises: and correspondingly storing the storage state of each storage unit of each RAM in a two-dimensional array Bitmap.
Bitmap is a data structure representing a dense set of finite fields, each element occurring at least once, without other data and elements associated.
In some embodiments of the present application, by establishing a Bitmap mechanism, a storage state of a storage unit of each RAM is correspondingly marked in a Bitmap, specifically, a storage state of a corresponding designated storage unit in the Bitmap may be represented by 0 or 1, where 0 indicates that the storage unit is in a writable state, and 1 indicates that the storage unit is in an unwritable state. After each operation is carried out on a storage unit of the RAM, correspondingly updating the storage state of the storage unit in the Bitmap; or, the storage state of the designated storage unit in the Bitmap is set to represent the storage state of the storage unit; it will be appreciated that the writing of data into the memory locations in the RAM is typically performed in an overlapping fashion, and whether there is data in the memory locations does not affect whether the memory locations can write new data, and therefore, RAM data validity discrimination control can be performed by correspondingly marking the memory states of the memory locations of each RAM in the Bitmap.
Correspondingly, in some embodiments, querying the memory state of the corresponding memory location of the feature address in each RAM may include: and inquiring the storage state of each corresponding storage unit in each RAM of the characteristic address stored in the Bitmap.
Step 103, corresponding processing is executed for each RAM according to the request type.
In the embodiment of the application, read-write address lines of each RAM in a data array of parallel RAMs are shared; by inquiring the storage state of the corresponding storage unit in each RAM, unified control and management of a plurality of RAMs in parallel are realized.
Specifically, a corresponding processing method is described for each RAM for different request types by some embodiments.
Fig. 2a is a partially exploded schematic diagram of step 103 in the parallel RAM-based data array management method shown in fig. 1, as shown in fig. 2a, in some embodiments, when a request type corresponding to a data management request is a cache data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:
step 103a, writing the cache data into a storage unit with at least one storage state corresponding to the characteristic address being writable.
For example, in some embodiments, 8 parallel RAMs are provided, the cache data is written into the RAMs according to the feature addresses, and when the first RAM address conflicts, that is, when the storage state of the storage unit of the first RAM corresponding to the feature address is non-writable, the cache data is written into the RAM of which any address in the remaining RAMs does not conflict.
In some embodiments, if the storage state of the storage unit corresponding to the feature address in each RAM is non-writable, the sender of the cache data request feeds back the cache failure information, and returns or discards the cache data that fails.
And further, the unified management of data writing of the data array based on the parallel RAM is realized.
FIG. 2b is an exploded flowchart of step 103 in the parallel RAM-based data array management method shown in FIG. 1, in some embodiments, as shown in FIG. 2b, when the request type corresponding to the data management request is a query data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:
step 103b1, reading the data content of the storage unit of each RAM corresponding to the query address;
step 103b2, outputting the data content whose storage state is non-writable;
step 103b3, storing the data in which the storage state of the corresponding storage unit is writable in 0 and outputting the data.
And further, the unified management of data query of the data array based on the parallel RAM, namely the unified management of data reading, is realized.
FIG. 2c is an exploded flowchart of step 103 in the parallel RAM-based data array management method shown in FIG. 1. In some embodiments, as shown in FIG. 2c, when the request type corresponding to the data management request is a clear data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:
in step 103c, the storage state of the storage unit corresponding to the feature address is set to be writable.
It will be appreciated that the writing of data into the memory cells in the RAM is typically performed in an overlay manner, and whether there is data in a memory cell does not affect whether the memory cell is capable of writing new data, so that the memory function release for each RAM can be achieved by correspondingly marking the memory state of the memory cell in the Bitmap as writable.
And further, the unified management of data clearing of the data array based on the parallel RAM is realized.
In some embodiments, the above method further comprises:
taking a first preset duration as a period, subtracting 1 from a buffer data life cycle count value stored in a storage unit of each RAM;
and setting the storage state of the storage unit with the buffer data life cycle count value of 0 stored in each RAM as writable by taking the second preset time length as a period.
It can be understood that in the above embodiment, the first preset duration is taken as the training period of subtracting 1 from the survival period count value of the cache data, and the second preset duration is taken as the training period of detecting that the survival period count value of the cache data is 0 and emptying.
In some embodiments, the timing function for the first preset duration and the second preset duration may be implemented by an internal timer or an external timer.
The initial value of the life cycle count value of the cache data stored in the RAM storage unit can be set when the cache data is written, and can be reset or prolonged in the effective period of the life time according to actual needs; the data life cycle can be usually preset times, and the converted data life time can be obtained by multiplying the counted value by the first preset time; in some application scenarios, the data life cycle can be set to never expire according to actual needs, so that the data life cycle is prevented from being cleared up.
The first preset time length and the second preset time length can be set according to actual needs, and the first preset time length and the second preset time length have no necessary time relationship; the first preset time length and the second preset time length can be set to be time length capable of dividing 1000 milliseconds, and the first preset time length can be integer times of the second preset time length, so that calculation is facilitated, and storage management efficiency is improved; in some embodiments, to adapt to typical usage requirements, the first preset time period may be set to 100 milliseconds and the second preset time period may be set to 10 milliseconds.
Through a data life cycle control function mechanism, address space is released by flushing cache for long-time useless data.
Fig. 3 is a schematic architecture diagram of a method for implementing data array management based on parallel RAM according to an embodiment of the present application, as shown in fig. 3, in some embodiments of the present application, a method 300 for implementing data array management based on parallel RAM is provided, where read address lines of a plurality of RAMs are shared, and all other signal lines are independent. According to the scheme, data can be cached, according to the characteristic address (characteristic bit field or upper-level path indication in the data) of the cached data, the data is stored into the RAM according to the address, when the address conflicts, the data can be stored into the 2 nd RAM, and so on, 8 RAMs are arranged. The descriptor storage management module is the core of the scheme, and the functions of read-write control, overtime emptying, inquiry, writing and the like of each managed RAM.
A Bitmap mechanism is established, bitmap synchronization indicates the data validity of each storage unit in 8 blocks of RAM, and when the written data of a certain address of a certain RAM is valid, the address bit mark value of the block of RAM in Bitmap (two-dimensional array) is set to be 1. Correspondingly, the address bit flag value of the block RAM in Bitmap is set to 0 when a certain RAM space is cleared.
When the external world sends a request for inquiring the data of a certain RAM address to the descriptor storage management module, the descriptor storage management module controls 8 RAMs to read the data content of the address at the same time, whether the data of each RAM is effective or not is judged according to the Bitmap validity, if so, the original data is read and sent to a request inquirer, and if not, the data is output to 0.
The descriptor storage management module identifies an external cache emptying request, sets 0 data of a corresponding storage address of a corresponding RAM in the Bitmap, and represents emptying (instead of actually cleaning the data in the RAM) so as to empty the cache space, so that the address space can be opened to writing actions.
The descriptor storage management module sets an internal counter, and performs a data descriptor lifetime timing function in RAM of a count period according to the configuration counter value. The descriptor storage management module starts a round of buffer data life cycle count value subtracting operation every 100ms according to default setting, and simultaneously reads data of 8 RAMs (according to Bitmap indicating data validity), reads data of 0 address space of the 8 RAMs from 0 address, bitmap indicating the data validity of each RAM, if valid, subtracts and rewrites the data life cycle bit field value of the RAM back to the address space, and if the life time is zero, does not operate. If the Bitmap indicates that the RAM is invalid, the RAM is not operated on.
The descriptor storage management module sets an internal counter, executes a data overtime recovery function with the RAM life time of 0 in a counting period according to the configuration counter value, starts a round of cache data life cycle overtime recovery operation every 10ms according to default setting, reads data of 8 RAMs (according to Bitmap indicating data validity) at the same time, reads data of 0 address space of the 8 RAMs from 0 address, and the Bitmap indicates the data validity of each RAM, if the data life cycle bit field value of the RAM is not 0 at the same time, no recovery operation is executed, if the life time is zero, the recovery operation is executed, the corresponding Bitmap is set to 0, and the address data is output at the same time. If the Bitmap indicates that the RAM is invalid, the RAM is not operated on.
By uniformly controlling simultaneous read-write operation of the RAMs, the read-write operation of the RAMs is independently controlled according to the actual condition of each RAM at the current moment by utilizing a Bitmap establishment method. For example, in the current state, the survival time value of the 0x0a address of the 8 RAMs is subtracted by one, and the control module uniformly enters the 8 RAMs into the control mode, but because there are only 6 RAMs in the address of the 0x0a, and there are conditions of read-write conflict caused by that the RAM is being emptied in the 6 RAMs, the implementation method of the patent can independently control the actual conditions of each RAM at the moment, does not execute the survival period subtracting operation on the empty RAM, and performs conflict waiting on the RAM with the read-write conflict. The method improves the use efficiency of parallel operation of multiple RAMs, and has rich functions for managing data in the RAMs.
In this embodiment, the simultaneous read-write operation of 8 RAMs is only illustrated, but not a specific limitation on the number of RAMs, and the number of RAMs is more than 2, so that parallel control of more than 1 RAM is achieved, and the control efficiency is higher as the number of RAMs is larger.
The technical effect of the scheme is as follows:
1. because the prior art basically operates the independent RAM, the upper control RAM module is subjected to logic copying, so that the operation of controlling a plurality of RAMs is achieved. The patent performs unified operation on a plurality of RAMs simultaneously, and independently controls reading and writing of each RAM under the unified operation according to the effective indication of the Bitmap.
2. The control and management of the data life cycle in the RAM are increased, and useless data can be emptied for a long time, so that the utilization rate of the data cache is improved. And when the data in the RAM is subjected to the time-to-live decreasing and recovering, the RAM is subjected to the waiting execution if the RAM with the read-write conflict exists, and the operation is carried out when the conflict is ended.
3. A Bitmap indication RAM data validity mechanism is established to judge whether the RAM address space data is valid or not, so that when a plurality of RAMs are operated, the RAM read-write operation with data is independently controlled according to the Bitmap indication.
Fig. 4 is a schematic structural diagram of a parallel RAM-based data array management device according to an embodiment of the present application, as shown in fig. 4, a parallel RAM-based data array management device 400 of the present application may include:
the transceiver module 401 is configured to receive a data management request, and determine a request type and a feature address corresponding to the data management request;
a control module 402, configured to query a storage state of a corresponding storage unit of the feature address in each RAM;
a processing module 403, configured to perform corresponding processing on each RAM according to the request type.
In this embodiment, the specific processes and the technical effects brought by the transceiver module 401, the control module 402 and the processing module 403 of the parallel RAM-based data array management device can refer to the relevant descriptions of steps 101 to 104 in the corresponding embodiment of fig. 1, and are not repeated here.
In some embodiments, when the request type corresponding to the data management request is a cache data request, the processing module 403 is specifically configured to:
and writing the cache data into a storage unit with at least one storage state which corresponds to the characteristic address and is writable.
In some embodiments, when the request type corresponding to the data management request is a query data request, the processing module 403 is specifically configured to:
reading the data content of the storage unit of each RAM corresponding to the query address;
outputting the data content which is non-writable in the storage state of the corresponding storage unit;
and outputting the data content 0 with the storage state of the corresponding storage unit being writable.
In some embodiments, when the request type corresponding to the data management request is a clear data request, the processing module 403 is specifically configured to:
and setting the storage state of the storage unit corresponding to the characteristic address to be writable.
In some embodiments, as shown in fig. 4, the apparatus further includes:
a Bitmap module 404, configured to correspondingly save a storage state of each storage unit of each RAM;
the control module 402 is specifically configured to query the storage states of the corresponding storage units in each RAM of the feature addresses stored in the Bitmap module 404.
In some embodiments, the processing module 403 is further configured to decrement the buffer data life cycle count value stored in the storage unit of each RAM by one with the first preset duration as a period; and setting the storage state of the storage unit with the buffer data life cycle count value of 0 stored in each RAM as writable by taking the second preset time length as a period.
It should be noted that, the implementation details and technical effects of each module in the parallel RAM-based data array management apparatus provided in the embodiments of the present disclosure may refer to the descriptions of other embodiments in the present disclosure, which are not described herein again.
The embodiment of the application discloses a storage device, comprising: a data array composed of more than two parallel RAMs and any data array management device based on the parallel RAMs for managing the data array.
The embodiments of the present application are not limited to the specific form of the storage device described above, and the storage device may include a chip, a removable storage device, a computer, a smart home appliance, a removable electronic device, a server, etc., and the storage device described in the embodiments of the present application is intended to include, but not be limited to, these and any other suitable types of memory.
The technical solutions described in the embodiments of the present application may be arbitrarily combined without any conflict.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A parallel RAM-based data array management method, the method comprising:
receiving a data management request, and determining a request type and a feature address corresponding to the data management request;
inquiring the storage state of a corresponding storage unit of the characteristic address in each RAM;
taking a first preset time length as a period, subtracting 1 from a buffer data life cycle count value stored in a storage unit of each RAM, wherein the first preset time length is taken as a polling period of subtracting 1 from the buffer data life cycle count value;
setting the storage state of a storage unit with the buffer period count value of 0 stored in each RAM as writable by taking a second preset time length as a period, wherein the second preset time length is taken as a polling period for detecting that the buffer data life period count value is 0 and emptying;
and executing corresponding processing on each RAM according to the request type.
2. The method according to claim 1, wherein when the request type corresponding to the data management request is a cache data request, the performing, according to the request type, a corresponding process on each RAM includes:
and writing the cache data into the storage unit with at least one writable storage state corresponding to the characteristic address.
3. The method according to claim 1, wherein when the request type corresponding to the data management request is a query data request, the performing, according to the request type, a corresponding process on each RAM includes:
reading the data content of the storage unit of each RAM corresponding to the query address;
outputting the data content which is non-writable in the storage state of the corresponding storage unit;
and outputting the data content 0 with the storage state of the corresponding storage unit being writable.
4. The method according to claim 1, wherein when the request type corresponding to the data management request is a clear data request, the performing, according to the request type, a corresponding process on each RAM includes:
and setting the storage state of the storage unit corresponding to the characteristic address to be writable.
5. The method according to any one of claims 1 to 4, further comprising:
correspondingly storing the storage state of each storage unit of each RAM in a two-dimensional array Bitmap;
the step of inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM comprises the following steps: and inquiring the storage state of each corresponding storage unit in each RAM of the characteristic address stored in the Bitmap.
6. A parallel RAM-based data array management apparatus, the apparatus comprising:
the receiving and transmitting module is used for receiving a data management request and determining a request type and a characteristic address corresponding to the data management request;
the control module is used for inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM;
taking a first preset time length as a period, subtracting 1 from a buffer data life cycle count value stored in a storage unit of each RAM, wherein the first preset time length is taken as a polling period of subtracting 1 from the buffer data life cycle count value;
setting the storage state of a storage unit with the buffer period count value of 0 stored in each RAM as writable by taking a second preset time length as a period, wherein the second preset time length is taken as a polling period for detecting that the buffer data life period count value is 0 and emptying;
and the processing module is used for executing corresponding processing on each RAM according to the request type.
7. The apparatus of claim 6, wherein when the request type corresponding to the data management request is a cache data request, the processing module is specifically configured to:
and writing the cache data into the storage unit with at least one writable storage state corresponding to the characteristic address.
8. The apparatus of claim 6, wherein when the request type corresponding to the data management request is a query data request, the processing module is specifically configured to:
reading the data content of the storage unit of each RAM corresponding to the query address;
outputting the data content which is non-writable in the storage state of the corresponding storage unit;
and outputting the data content 0 with the storage state of the corresponding storage unit being writable.
9. The apparatus of claim 6, wherein when the request type corresponding to the data management request is a clear data request, the processing module is specifically configured to:
and setting the storage state of the storage unit corresponding to the characteristic address to be writable.
10. A storage device, the storage device comprising: a data array of two or more RAMs in parallel and a parallel RAM-based data array management apparatus for managing the data array as claimed in any one of claims 6 to 9.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0831496A2 (en) * | 1996-09-20 | 1998-03-25 | Texas Instruments Incorporated | A method and system for testing memory |
| KR19980079133A (en) * | 1997-04-30 | 1998-11-25 | 윤종용 | LCD Controller RAM |
| US6100995A (en) * | 1996-08-21 | 2000-08-08 | Brother Kogyo Kabushiki Kaisha | Multi-function device and information storing medium therefor |
| CN1761935A (en) * | 2003-09-18 | 2006-04-19 | 松下电器产业株式会社 | Semiconductor memory card, semiconductor memory control apparatus, and semiconductor memory control method |
| CN102411543A (en) * | 2011-11-21 | 2012-04-11 | 华为技术有限公司 | Method and device for processing caching address |
| CN104778025A (en) * | 2015-04-16 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Circuit structure of first-in first-out memory based on random access memory |
| CN104834501A (en) * | 2015-04-20 | 2015-08-12 | 江苏汉斯特信息技术有限公司 | L structure processor-based register and register operation method |
| CN105718219A (en) * | 2016-01-19 | 2016-06-29 | 浙江大学 | Method and module for high-speed data transmission and storage based on USB3.0 |
| EP3153998A2 (en) * | 2015-10-08 | 2017-04-12 | VIA Alliance Semiconductor Co., Ltd. | Neural network unit that performs concurrent lstm cell calculations |
| CN108805275A (en) * | 2017-06-16 | 2018-11-13 | 上海兆芯集成电路有限公司 | Programmable device and its operating method and computer usable medium |
| CN111124961A (en) * | 2019-12-30 | 2020-05-08 | 武汉先同科技有限公司 | Method for realizing conversion from single-port RAM to pseudo-dual-port RAM in continuous read-write mode |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
| CN111478750A (en) * | 2020-03-12 | 2020-07-31 | 普联技术有限公司 | Data parallel interleaving method, terminal equipment and computer storage medium |
| CN112119459A (en) * | 2018-03-16 | 2020-12-22 | 赛灵思公司 | Memory arrangement for tensor data |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4525816B2 (en) * | 2007-09-28 | 2010-08-18 | 株式会社デンソー | Electronic device and program |
-
2021
- 2021-03-26 CN CN202110324196.XA patent/CN113126913A/en active Pending
-
2022
- 2022-01-19 CN CN202210059270.4A patent/CN114489502B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100995A (en) * | 1996-08-21 | 2000-08-08 | Brother Kogyo Kabushiki Kaisha | Multi-function device and information storing medium therefor |
| EP0831496A2 (en) * | 1996-09-20 | 1998-03-25 | Texas Instruments Incorporated | A method and system for testing memory |
| KR19980079133A (en) * | 1997-04-30 | 1998-11-25 | 윤종용 | LCD Controller RAM |
| CN1761935A (en) * | 2003-09-18 | 2006-04-19 | 松下电器产业株式会社 | Semiconductor memory card, semiconductor memory control apparatus, and semiconductor memory control method |
| CN102411543A (en) * | 2011-11-21 | 2012-04-11 | 华为技术有限公司 | Method and device for processing caching address |
| CN104778025A (en) * | 2015-04-16 | 2015-07-15 | 浪潮电子信息产业股份有限公司 | Circuit structure of first-in first-out memory based on random access memory |
| CN104834501A (en) * | 2015-04-20 | 2015-08-12 | 江苏汉斯特信息技术有限公司 | L structure processor-based register and register operation method |
| EP3153998A2 (en) * | 2015-10-08 | 2017-04-12 | VIA Alliance Semiconductor Co., Ltd. | Neural network unit that performs concurrent lstm cell calculations |
| CN105718219A (en) * | 2016-01-19 | 2016-06-29 | 浙江大学 | Method and module for high-speed data transmission and storage based on USB3.0 |
| CN108805275A (en) * | 2017-06-16 | 2018-11-13 | 上海兆芯集成电路有限公司 | Programmable device and its operating method and computer usable medium |
| CN112119459A (en) * | 2018-03-16 | 2020-12-22 | 赛灵思公司 | Memory arrangement for tensor data |
| CN111124961A (en) * | 2019-12-30 | 2020-05-08 | 武汉先同科技有限公司 | Method for realizing conversion from single-port RAM to pseudo-dual-port RAM in continuous read-write mode |
| CN111478750A (en) * | 2020-03-12 | 2020-07-31 | 普联技术有限公司 | Data parallel interleaving method, terminal equipment and computer storage medium |
| CN111398996A (en) * | 2020-03-17 | 2020-07-10 | 广州南方卫星导航仪器有限公司 | Surveying and mapping satellite navigation receiver |
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|---|---|
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