KR19980079133A - LCD Controller RAM - Google Patents

Abstract

A liquid crystal display controller RAM is disclosed. The liquid crystal display controller RAM is a liquid crystal display controller that controls display of predetermined data on a liquid crystal display device in response to a command of a microprocessor, wherein the first to Nth RAM cells each store N-th RAM data. An array unit; And an input / output cell that reads / writes the microprocessor and the RAM data, wherein the first to Nth RAM cell array units output the RAM data to the liquid crystal display in response to a command of the microprocessor.

Description

LCD Display Controller RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD) controller, and more particularly to an LCD controller having a ram structure in which all of the ram cell arrays are connected to one input / output cell.

The LCD controller integrated circuit (IC) controls the display of certain characters on the LCD panel. The basic operation is that the microprocessor (MICROPROCESSOR UNIT: MPU) displays the characters to be displayed in the RAM inside the LCD controller. When recording the data, the address counter or scan counter inside the LCD controller periodically scans the display data RAM (DDRAM) and stores the character stored in the character generator ROM (CGROM), the user-defined character stored in the CGRAM, or ICONRAM. Generates the font corresponding to the stored icon shape and displays it on the LCD panel.

That is, when the LCD controller wants to display certain characters or icons on the LCD panel, the MPU writes the characters to be displayed in the DDRAM, and the address counter and the scan counter inside the LCD controller scan the DDRAM data and IC to control LCD screen display by reading each RAM data from CGROM, CGRAM and ICONRAM corresponding to letters and outputting to the COM (COMMON) / SEG (SEGMENT) terminal which is directly connected to LCD panel to drive LCD. to be.

In addition, each RAM inside the LCD controller must perform a READ / WRITE interface with the MPU in order to display certain characters, user-defined fonts (FONT) and icons in the desired position, and each DDRAM / CGRAM / ICONRAM. In order to output the data for display to the COM / SEG terminal connected to this LCD panel, the data is periodically scanned and data reading is performed. Therefore, LCD controllers currently in use include approximately 40 bytes of input / output (I / O) cells, 80 bytes of DDRAM arrays, 64 bytes of CGRAM arrays, and 24 bytes of ICONRAM arrays for each RAM. It requires capacity.

1A to 1C are block diagrams illustrating a RAM cell array unit of a conventional LCD controller. FIG. 1A illustrates an I / O cell 120 and a DDRAM array unit 126 constituting a DDRAM. (b) shows the I / O cell 140 and the CGRAM array unit 146 constituting the CGRAM, and (c) shows the I / O cell 160 and the ICONRAM array unit 166 constituting the ICONRAM. . Here, reference numeral 124 of FIG. 1 (a) denotes a DD word address line, 144 of 1 (b) denotes a CG word address line, and 164 of 1 (c) denotes an ICON word address line.

FIG. 2 is a circuit diagram illustrating a RAM cell structure constituting the RAM cell array units 126, 146, and 166 of each RAM of a conventional LCD controller, and includes a gate connected to a word address line WORD, a data line DB, An nMOS transistor M1 having a drain and a source connected to the first storage node N1, a gate connected to the word address line, a drain and a source connected to the complementary data line DBB and the second storage node N2 are provided. The data storage unit 10 includes an nMOS transistor M2, a first inverter connected between the first node N1, and a second node N2.

3A to 3D are timing diagrams showing an access time of a conventional LCD controller, wherein (a) is an access time at the read / write interface between the RAMs and the MPU, and FIGS. and (d) are timing diagrams showing the access time during the scan operation of the DDRAM, CGRAM and ICONRAM, respectively.

As shown in Figures 1 and 2, each RAM interfaces with the MPU. When each RAM performs a scan operation, the read data is output via the data bus DB0: 7. Since the conventional LCD controller RAM uses the standard RAM cell shown in FIG. 2, in order to perform a read / write interface between the RAM and the MPU and to perform a scan operation of each RAM, as shown in FIG. 1, DDRAM / CGRAM / Each ICONRAM block is implemented independently. The DDRAM shown in FIG. 1 (a) is composed of an I / O cell 120 of 40 bytes and a RAM cell array unit 126 of 80 bytes. The CGRAM shown in FIG. 1 (b) has an I / O cell of 40 bytes. An O cell 140 and a 64 byte RAM cell array unit 146. The ICONRAM shown in FIG. 1 (c) is a 40 byte I / O cell 160 and a 24 byte RAM cell array unit 166. It is composed of

Herein, the I / O cell size of each RAM block corresponds to about 40 bytes (BYTE) RAM cell size, and it can be seen that all RAMs are the same. In the case of the ICONRAM shown in FIG. 1 (c), the I / O cell size is larger than the RAM array size. In the LCD controller for character, the RAM size occupies about 25 to 35% of the chip area, so each is independent. The structure of the DRAM block puts a heavy burden on the overall chip size of the LCD controller.

Therefore, since a conventional LCD controller cannot simultaneously perform a scan operation for reading RAM data of DDRAM / CGRAM / ICONRAM to one I / O cell in the internal RAM, it is necessary to implement each of the I / O cells. There is a problem that the RAM size is increased.

An object of the present invention is to provide an LCD controller RAM having a structure in which internal RAM cell array units are connected to one input / output cell.

1A to 1C are block diagrams illustrating a conventional RAM structure of a liquid crystal display controller.

FIG. 2 is a circuit diagram illustrating a ram cell structure of the liquid crystal display controller illustrated in FIG. 1.

3A to 3D are timing diagrams showing an access time of the liquid crystal display controller shown in FIG.

4 is a schematic block diagram illustrating an interface between an LCD controller RAM and an MPU and an LCD according to the present invention.

FIG. 5 is a schematic block diagram illustrating a liquid crystal display controller RAM shown in FIG. 4.

FIG. 6 is a circuit diagram of an exemplary embodiment for explaining a RAM cell structure of the liquid crystal display controller illustrated in FIG. 5.

In order to achieve the above object, the liquid crystal display controller RAM according to the present invention, in the liquid crystal display controller for controlling the display of the predetermined data on the liquid crystal display device in response to a command of the microprocessor, each of the N-th RAM data A first to N-th RAM cell array unit for storing; And an input / output cell that reads / writes RAM data and RAM data.

Hereinafter, the configuration of the LCD controller RAM according to the present invention will be described with reference to the accompanying drawings.

4 is a schematic block diagram illustrating an interface between an LCD controller RAM and an MPU and an LCD according to the present invention, including an input / output buffer 402, an output register 406, an input register 420, an instruction processor 440, The LCD controller 4 includes a RAM 410, a parallel / serial converter 408, and an output signal driver 430, and an MPU 2 and an LCD panel 6. Here, the input register 420 of the LCD controller 4 is composed of a data register 424 and a command register 426, and the command processor 440 is composed of a command decoder 442 and an address counter 444. The output signal driver 430 includes a SEG (SEGMENT) signal driver 432 and a COM (COMMON) signal driver 434.

FIG. 5 is a block diagram illustrating a RAM structure according to the present invention of the LCD controller 4 shown in FIG. 4, in which a DDRAM 64 / CGRAM 66 / ICONRAM 68 cell array unit and an I / O cell are shown. (62), the number of RAM cell array portions is not limited to three, but may be more flexible.

The MPU 2 shown in FIG. 4 transfers data and commands to the LCD controller 4 in order to display predetermined data on the LCD 6. That is, data to be written to the RAM 410 of the LCD controller 4 is outputted, and the data written to the RAM 410 together with the data stored in the RAM 410 to the LCD 6. It is converted into parallel data for display and output to the LCD 6. Therefore, the LCD 6 can display a screen combined with characters or icons to be displayed using data output from the LCD controller 4. In addition, the MPU 2 reads the output RAM data again, whereby it is possible to confirm whether the LCD controller 4 has transmitted the correct data to the LCD 6. The LCD 6 displays, in response to a command from the MPU 2, a character or icon designated as RAM 410 data output through the COM (COMMON) / SEG (SEGMENT) terminal of the LCD controller 4 at a designated position. . The input / output buffer 402 of the LCD controller 4 is a direct path through which the LCD controller 4 performs a data interface with the MPU 2. All data input / output with the MPU 2 is performed through the input / output buffer 402.

In addition, the data register 404 stores data input through the input / output buffer 402 and outputs the data to the RAM 410 or outputs the data output from the RAM 410 to the output register 406 and the input / output buffer 402. Output to the MPU (2) through. The instruction register 406 temporarily stores the instructions input from the MPU 2, and the stored instructions are input to the instruction decoder 442 and the address counter 444, respectively, and the instruction decoder 442 decodes the instruction to be executed. Output to RAM 410. The address counter 444 outputs an address corresponding to the command to the RAM 410. The RAM 410 stores character or icon data to be displayed on the LCD 6, writes new data from the MPU 2, or reads data from the RAM 410 to the MPU 2 or LCD 6. It is possible. The parallel / serial converter 408 converts the parallel data output from the RAM 410 in series and outputs the serial data. The SEG signal driver 432 of the output signal driver 430 outputs the serial data output from the RAM 410. The signal is converted into an n-bit parallel signal, and the converted n-bit signal is output to the LCD 6 through the segment terminal. The COM signal driver 434 converts the data output from the RAM 410 into an m-bit common signal, and outputs the converted m-bit data to the LCD 6 through the COM terminal.

The I / O cell 62 of the RAM 410 shown in FIG. 5 is a path for performing a read / write interface with the MPU 2 shown in FIG. 4. 62 is shared to each of the RAM cell array units 64, 66, and 68, in which a plurality of RAMs are integrated into one. In addition, each ram cell array unit is composed of a plurality of ram cells (eg, 647, 667, and 687). The MPU 2 reads or writes RAM data through the data bus DB0: k of the I / O cell 62 by reading or writing data at a RAM position corresponding to word address lines (WORD) 640, 660, 680. Is done. In addition, outputting the RAM data to the LCD 6 in response to the command of the MPU 2 is the output data bus DOUT10 of each RAM cell array unit 64, 66, and 68 corresponding to the scan address (SCAN) 644,664,684. is output to the LCD 6 via: k, DOUT20: k, and DOUT30: k.

FIG. 6 is a circuit diagram of a RAM cell constituting the RAM cell array units 64, 66, and 68 of the LCD controller 4 shown in FIG. 5, the gate connected to the word address line WORD, and the data line DB. A first transistor NT1 having a drain and a source connected between the first and second storage nodes, a gate connected to the word address line WORD, and a drain and a source connected between the complementary data line DBB and the second storage node. It is connected between the second transistor (NT2) having a first node (N1) and the second node (N2), and stores the data of the first node (N1) or the second node (N2), the first inverter and the first Inputting data of the data storage unit 20, the first node N1, or the second node N2 composed of two inverters to output data corresponding to the scan address line SCAN or the complementary scan address line SCANB It consists of a three-state inverter 25.

Hereinafter, the operation of the LCD controller 4 RAM 410 according to the present invention will be described with reference to FIGS. 4, 5, and 6 as follows.

As shown in Fig. 4, in order to display desired characters or icons on the LCD panel 6, the MPU 2 writes predetermined RAM data into the RAM 410 of the LCD controller 4, and writes the written data. The RAM cell array portion of the RAM 410 inside the LCD controller 4 for display on the LCD 6, for example, the corresponding RAM data from the DDRAM 64, CGRAM 66 and ICONRAM 68 cell array portions. The data is converted into parallel data and output as a SEG signal and a COM signal of a predetermined bit which are directly used to drive the LCD 6. That is, data input from the MPU 2 to the input / output buffer 402 of the LCD controller 4 is input to the data register 424 and the command register 426 of the input register 420, respectively. The data register 424 temporarily stores the data to be displayed on the LCD 6 and outputs the data to the RAM 410, and the command register 426 stores the data stored in the RAM 410 at a position of the LCD 6. Command when to print. Further, the RAM data output to the LCD 6 is instructed to be transferred back to the MPU 2 in order to confirm whether the RAM data output to the LCD 6 is correct. That is, the instruction decoder 442 of the instruction register 426 decodes the instruction inputted from the MPU 2 and delivers the instruction to the RAM 410, and the address counter 444 writes data to a position of the RAM 410. Tells you whether or not to read. In addition, an address for designating which position of the RAM 410 should be read and output to the LCD 6 is output to the RAM 410.

Here, in order for the MPU 2 to write data to the RAM 410, the MPU 2 writes data designated at the position of the RAM 410 corresponding to the MPU word address output from the address counter 444 of the LCD controller 4. . In addition, in order to display data on the LCD 6 in response to a command of the MPU 2, the RAM data corresponding to the scan address SCAN output from the scan counter present in the LCD controller 4 is read out and parallelized. It is output to the LCD 6 via the / serial converter 408 and the output signal driver 430.

A read / write interface with the MPU 2 and a scan operation for the display of the LCD 6 will be described in detail with reference to the circuit diagram of the ram cell shown in FIG.

As shown in FIG. 6, when the RAM cell is changed, read / write of the RAM 410 and the MPU 2 is performed by the MPU word address lines (WORD) 640, 660, and 680 through the shared I / O cell 62. It is enabled and made in the same manner as the conventional method by the data line DB and the complementary data line DBB. That is, data is read / written through the data line DB and the complementary data line DBB by the word address line WORD. For example, when performing a read / write interface between the MPU 2 and the DDRAM array portion 64 of the RAM 410, the RAM cell 647 may be removed from the data line DB or the complementary data line DBB. When writing data designated to one storage node N1 or second storage node N2, high is applied to the word address line WORD 640 to drive the nMOS transistors NT1 and NT2, and then the data is stored. Data is stored in the node N1 or N2 of the unit 20. In addition, when the MPU 2 tries to read data stored in the data storage 20 of the RAM cell 647, the nMOS transistors NT1 are similarly applied by applying high to the word address line (WORD) 640. And NT2) to read data stored in the first storage node N1 or the second storage node N2, and the read data is output through the data bus DB0: k of the I / O cell 62. It is output to the register 406 and passed to the MPU 2.

Meanwhile, in order to display screen display data such as characters or icons on the LCD panel, each DDRAM 64 / CGRAM 66 / ICONRAM 68 cell array of RAM 410 corresponding to the input scan address (SCAN). When performing a scan operation for reading negative data, a position designated by a scan address SCAN input from the scan address input unit 630 to read data stored in the data storage unit 20 of the RAM cell 647 is read. Reads the data from the I / O cell and outputs it via the output data bus DOUT0: k. That is, when the data of the DDRAM array unit is to be read and read, data corresponding to the scan address (SCAN) 644 is read from the data storage unit 20 shown in FIG. 6 and paralleled through the output data bus DOUT10: k. And the serial data outputted to the serial converter 408, and the output serial data is converted into an n-bit SEG signal and an m-bit COM signal by the SEG signal driver 432 and the COM signal driver 434 of the output signal driver 430. The output is converted.

Referring to FIG. 6 in detail with reference to the circuit diagram of the RAM cell, the DD scan when the address counter 444 and the scan counter of the LCD controller 4 scan DDRAM data to read the data of the corresponding address. Data stored in the second node N2 corresponding to the address SCAN is input to the tri-state inverter 25, and high or low data input to the tri-state inverter 25 is stored in the DD scan address SCAN ( When 644 is low, that is, the complementary scan address SCANB is high, it is inverted and output through the output terminal DOUT10: k. In addition, when the scan address (SCAN) 644 is high, that is, the complementary scan address (SCANB) is low, the output is in a high impedance state to maintain a floating state. Similarly, the data corresponding to the specified CGRAM scan address and ICONRAM scan address are also output through the output terminals DOUT20: k and DOUT30: k in the CGRAM and ICONRAM blocks.

As a result, each of the RAM cell arrays of the RAM 410 may perform the scan operation independently of the MPU 2 using the tri-state inverter 25 illustrated in FIG. 6, thereby sharing the I / O cell 62. When the structure of the RAM cell inside the LCD controller 4 is modified as shown in FIG. 6, the conventional DD / CG / ICONRAM block shown in FIG. 1 has a structure connected to one I / O cell 62. Can be. Accordingly, the read / write interface with the MPU 2 is performed through the data bus of one I / O cell, that is, the input / output terminals DB0: k, corresponding to the word address WORD, as in the prior art, and the DDRAM 64 scans. When performing the operation, data read through the output terminal DOUT10: k is output corresponding to the DD scan address connected to the DDRAM cell array unit 64, and when performing CGRAM scan read, the CG scan address connected to the CGRAM array 66 is performed. Correspondingly, the data read out through the output terminal DOUT20: k is output. Similarly, when performing the ICONRAM 68 scan read, the data read out through the output terminal DOUT30: k is output corresponding to the ICON scan address connected to the ICONRAM array 68.

Therefore, when the RAM of the LCD controller is configured as shown in Fig. 5, the respective output terminals DOUT10: k, DOUT20: k, and DOUT30: k are maintained while maintaining the same RAM access time as shown in Figs. 3A to 3D. Scan data can be output through. It is also possible to apply to all LCD controllers as well as LCD controllers with three RAMs.

As described above, the LCD controller RAM according to the present invention shares an input / output cell so that the conventional RAM size and the area of two input / output cell blocks (approximately 80 bytes) in about 20% of RAM cell size increase are approximately 64 bytes. In addition to reducing the area of the minute, calculating the total chip size of the RAM block yields a chip size attenuation of about 22%. In addition, the independent scan is possible by changing the RAM structure, which facilitates the design of the ram scan control time.

Claims (3)

A liquid crystal display controller for controlling display of predetermined data on a liquid crystal display in response to a command of a microprocessor, First through N-th RAM cell array units for storing N-th RAM data; And An input / output cell configured to read / write the microprocessor and the RAM data, The first to Nth RAM cell array units are configured to respond to commands of the microprocessor. And outputting the RAM data to the liquid crystal display device. The RAM array of claim 2, wherein the first RAM to Nth cell array unit comprises: A liquid crystal display controller RAM comprising a plurality of RAM cells, respectively. The method of claim 3, wherein the ram cell, A first transistor having a gate connected to the word address line and a drain and a source connected between the data line and the first storage node; A second transistor having a gate connected to the word address line and a drain and a source connected between a complementary data line and a second storage node; A data storage unit connected between the first storage node and the second storage node and storing data of the first storage node or the second storage node; And An inverter configured to input data of the second storage node and output data corresponding to a scan address line or a complementary scan address line; And the scan address line is one scan address line selected from the first to Nth cell array units.