CN114489502A

CN114489502A - Data array management method and device based on parallel RAM and storage equipment

Info

Publication number: CN114489502A
Application number: CN202210059270.4A
Authority: CN
Inventors: 朱珂; 林谦; 王永胜; 顾艳伍; 赵金萍; 储志博
Original assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Current assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Priority date: 2021-03-26
Filing date: 2022-01-19
Publication date: 2022-05-13
Anticipated expiration: 2042-01-19
Also published as: CN113126913A; CN114489502B

Abstract

The embodiment of the application discloses a data array management method based on a parallel RAM, which comprises the following steps: receiving a data management request, and determining a request type and a characteristic address corresponding to the data management request; inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM; and executing corresponding processing on each RAM according to the request type. The embodiment of the application also discloses a data array management device and a storage device based on the parallel RAM.

Description

Data array management method and device based on parallel RAM and storage equipment

Technical Field

The present application relates to memory management technologies, and in particular, to a data array management method and apparatus based on a parallel RAM, and a storage device.

Background

In practical application, with the increasingly flexible requirement of a data caching function, the application of a data array storage module is increasingly wide, and the situation of writing address conflict of a Random Access Memory (RAM) can be effectively solved by data array storage consisting of RAM blocks based on the RAM, so that the requirement of an implementation method for supporting parallel high-efficiency management and control of the RAM is more obvious.

In order to meet the data array management formed by a plurality of RAMs, at present, the mainstream method in the industry is to instantiate each RAM, and the upper layer controls the RAM according to specific requirements, so that each independent RAM block corresponds to a set of complete control module, but the resource waste is caused, and the control efficiency is reduced; at present, no technical scheme is provided for simultaneously controlling multiple RAMs and performing independent read-write control and differentiation on each RAM.

Disclosure of Invention

The embodiment of the application provides a data array management method based on a parallel RAM, which comprises the following steps:

receiving a data management request, and determining a request type and a characteristic address corresponding to the data management request;

inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM;

and executing corresponding processing on each RAM according to the request type.

In some embodiments, when the request type corresponding to the data management request is a cache data request, the performing, according to the request type, corresponding processing on each RAM includes:

and writing the cache data into the memory unit of which at least one memory state corresponding to the characteristic address is writable.

In some embodiments, when the request type corresponding to the data management request is a query data request, the performing, according to the request type, corresponding processing on each RAM includes:

reading the data content of the storage unit of each RAM corresponding to the query address;

outputting the data content of which the storage state of the corresponding storage unit is not writable;

and (4) accommodating 0 in the data of which the storage state of the corresponding storage unit is writable and outputting the data.

In some embodiments, when the request type corresponding to the data management request is a clear data request, the performing, according to the request type, corresponding processing on each RAM includes:

and setting the storage state of the storage unit corresponding to the characteristic address to be writable.

In some embodiments, the method further comprises:

correspondingly storing the storage state of each storage unit of each RAM in a two-dimensional array Bitmap;

the inquiring of the storage state of the feature address in each RAM corresponding to the storage unit comprises: and inquiring the storage state of each corresponding storage unit of the characteristic address in each RAM, which is stored in the Bitmap.

The embodiment of the application provides a data array management device based on a parallel RAM, which comprises:

the receiving and sending module is used for receiving a data management request and determining a request type and a characteristic address corresponding to the data management request;

the control module is used for inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM;

and the processing module is used for executing corresponding processing on each RAM according to the request type.

In some embodiments, when the request type corresponding to the data management request is a cache data request, the processing module is specifically configured to:

In some embodiments, when the request type corresponding to the data management request is a query data request, the processing module is specifically configured to:

In some embodiments, when the request type corresponding to the data management request is a clear data request, the processing module is specifically configured to:

The embodiment of the application discloses a storage device, including: the data array comprises a data array consisting of more than two RAMs in parallel and any one of the data array management devices based on the parallel RAMs for managing the data array.

In the technical scheme of the embodiment of the application, a request type and a characteristic address corresponding to a data management request are determined by receiving the data management request; inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM; and executing corresponding processing on each RAM according to the request type. The read-write address line of each RAM in the data array of the parallel RAM is shared; by inquiring the storage state of the corresponding storage unit in each RAM, independent read-write control and distinguishing can be carried out on each RAM, and unified control and management of a plurality of RAMs in parallel are realized.

Drawings

The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic flowchart of a data array management method based on a parallel RAM according to an embodiment of the present application;

FIG. 2a is an exploded flowchart of step 103 of the parallel RAM based data array management method shown in FIG. 1;

FIG. 2b is an exploded flowchart of step 103 of the parallel RAM based data array management method shown in FIG. 1;

FIG. 2c is an exploded flowchart of step 103 of the parallel RAM based data array management method shown in FIG. 1;

FIG. 3 is a schematic diagram illustrating a method for implementing data array management based on parallel RAM according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a data array management apparatus based on a parallel RAM according to an embodiment of the present application.

Detailed Description

For a more complete understanding of the features and technical content of the embodiments of the present application, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the embodiments of the present application.

So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

In the description of the embodiments of the present application, it should be noted that the terms "first \ second \ third" related to the embodiments of the present application are only used for distinguishing similar objects, and do not represent a specific ordering for the objects, and it should be understood that "first \ second \ third" may exchange a specific order or sequence order where permitted. It should be understood that "first \ second \ third" distinct objects may be interchanged under appropriate circumstances such that the embodiments of the application described herein may be implemented in an order other than those illustrated or described herein.

It can be understood that the data array based on the parallel RAM in the embodiment of the present application includes a data array composed of more than two RAMs in parallel. The technical scheme of the application is not limited to the specific number of the RAMs, and the technical scheme of the application can be realized by more than 2 RAMs.

The RAM in the present application may include a physical RAM, such as a RAM in a chip, or a RAM in a hardware system of a computer, a removable electronic device, or the like; virtual RAM, such as RAM emulated in a virtual software environment such as a virtual machine, may also be included.

Fig. 1 is a schematic flowchart of a parallel RAM-based data array management method according to an embodiment of the present application, and as shown in fig. 1, a parallel RAM-based data array management method 100 according to an embodiment of the present application includes:

step 101, receiving a data management request, and determining a request type and a feature address corresponding to the data management request.

In this embodiment of the application, the request type corresponding to the data management request may include: a cache data request, a query data request, or a clear data request.

The characteristic address may be a characteristic bit field in the data or an upper-level associated channel indication, and in this embodiment, the characteristic address may be used to match address information of a corresponding storage unit of the data corresponding to the request type in the data array of the parallel RAM.

A data caching request, namely a data management request for caching data; in some embodiments, the cache data request may specifically include cache data; the cache data can be sent to the data array from the outside or can be actively acquired from the outside by the data array management end; the characteristic address can be a field contained in the cache data and can be obtained by analyzing the cache data; the address data corresponding to the cache data may also be, for example, in some embodiments, the characteristic address corresponding to the cache data is obtained by means of a matching query, and the characteristic address is not directly written into the cache data, but is obtained by means of separate sending or active obtaining.

The query data request may include a data fetch access query to a data array of the parallel RAM and correspondingly, the characteristic address may include a query address corresponding to an address of a storage unit in the data array of the target parallel RAM.

The request for clearing data may include releasing a storage function of at least a part of the storage units in the data array of the parallel RAM, that is, setting the storage state of at least a part of the storage units in the data array of the parallel RAM to a writable state, and correspondingly, the characteristic address may include a query address of the storage unit whose storage function is to be released corresponding to the request for clearing data.

And 102, inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM.

It is understood that a parallel RAM-based data array is composed of multiple RAMs in parallel; the part of the RAM responsible for storing data is the memory matrix, which is made up of an array of a large number of memory cells. In some embodiments, the number of the storage units of the plurality of RAMs is the same, and the same characteristic address can be matched to the corresponding storage unit in each RAM, for example, if a data array is composed of 8 RAMs in parallel, the same characteristic address can be matched to 8 storage units; in some embodiments, the number of the memory units of the plurality of RAMs is not exactly the same, and the same characteristic address can be matched to at least more than one memory unit.

In some embodiments, the above method further comprises: and correspondingly storing the storage state of each storage unit of each RAM in a two-dimensional array Bitmap.

A Bitmap is a data structure that represents a dense set in a finite field, with each element appearing at least once, and no other data associated with the element.

In some embodiments of the present application, by establishing a Bitmap mechanism, a storage state of a storage unit of each RAM is correspondingly marked in a Bitmap, and specifically, a storage state of a corresponding designated storage unit in the Bitmap may be represented by 0 or 1, where 0 represents that the storage unit is in a writable state, and 1 represents that the storage unit is in a non-writable state. After the operation is performed on the storage unit of the RAM every time, the storage state of the storage unit in the Bitmap is correspondingly updated; or, the storage state of a specified storage unit in the Bitmap is set to represent the storage state of the storage unit; it can be understood that data writing of a memory cell in the RAM is usually performed in an overwriting manner, and whether the memory cell stores data does not affect whether the memory cell can write new data, so that the validity discrimination control of the RAM data can be performed by correspondingly marking the storage state of the memory cell of each RAM in the Bitmap.

Correspondingly, in some embodiments, querying the storage state of the feature address in the corresponding storage location in each RAM may include: and inquiring the storage state of each corresponding storage unit of the characteristic address in each RAM, wherein the characteristic address is stored in the Bitmap.

And 103, executing corresponding processing on each RAM according to the request type.

In the embodiment of the application, the read-write address line of each RAM in the data array of the parallel RAM is shared; by inquiring the storage state of the corresponding storage unit in each RAM, unified control and management of a plurality of RAMs in parallel are realized.

In particular, the execution of the corresponding processing method for each RAM for different request types is expanded by some embodiments.

Fig. 2a is a partially exploded schematic view of step 103 in the parallel RAM-based data array management method shown in fig. 1, as shown in fig. 2a, in some embodiments, when the request type corresponding to the data management request is a cache data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:

and 103a, writing the cache data into at least one memory unit with writable memory state corresponding to the characteristic address.

For example, in some embodiments, 8 RAMs are provided in parallel, the cache data is written into the RAMs according to the characteristic addresses, and when the first RAM address conflicts, that is, the storage state of the storage unit corresponding to the characteristic address of the first RAM is non-writable, the cache data is written into the RAM in which any address in the remaining RAMs does not conflict.

In some embodiments, if the storage states of the storage units corresponding to the characteristic addresses in each RAM are all unwritable, the sending party of the cache data request feeds back cache failure information, and the cache data with cache failure is returned or discarded.

And further, the data writing unified management of the data array based on the parallel RAM is realized.

Fig. 2b is an exploded flowchart of step 103 in the parallel RAM-based data array management method shown in fig. 1, and in some embodiments, as shown in fig. 2b, when the request type corresponding to the data management request is a query data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:

step 103b1, reading the data content of the memory location of each RAM corresponding to the query address;

step 103b2, outputting the data content whose storage state of the corresponding storage unit is not writable;

in step 103b3, the data whose storage state of the corresponding memory cell is writable is output as a 0.

And further, unified management of data query, namely unified management of data reading, of the data array based on the parallel RAM is achieved.

Fig. 2c is an exploded flowchart of step 103 in the parallel RAM-based data array management method shown in fig. 1, and in some embodiments, as shown in fig. 2c, when the request type corresponding to the data management request is a clear data request, the step 103 performs corresponding processing on each RAM according to the request type, which may specifically include:

and 103c, setting the storage state of the storage unit corresponding to the characteristic address as writable.

It can be understood that data writing to a memory cell in the RAM is usually performed in an overwriting manner, and whether the memory cell stores data does not affect whether the memory cell can write new data, so that the memory function of the memory cell can be released by correspondingly marking the memory state of the memory cell of each RAM in the Bitmap as writable.

And further, the unified management of data clearing of the data array based on the parallel RAM is realized.

In some embodiments, the above method further comprises:

subtracting 1 from the cache data life cycle count value stored in the storage unit of each RAM by taking a first preset time length as a cycle;

and setting the storage state of the storage unit with the survival cycle count value of the cache data stored in each RAM as 0 to be writable by taking the second preset time length as a cycle.

It is understood that, in the above embodiment, the first preset time period is used as the round-robin period for subtracting 1 from the count value of the cache data life cycle, and the second preset time period is used as the round-robin period for detecting that the count value of the cache data life cycle is 0 and clearing.

In some embodiments, the timing function for the first preset time period and the second preset time period may be implemented by an internal timer or an external timer.

The initial value of the cache data life cycle count value stored in the RAM storage unit can be set when the cache data is written, and can also be reset or prolonged in the effective life time period according to actual needs; the data life cycle period can be generally preset times, and can be calculated by multiplying a sub-count value by a first preset time length after being converted into the data life time length; in some application scenarios, the data life cycle can be set to be never expired according to actual needs, so that the data life cycle is prevented from being cleared after being zeroed.

The first preset time length and the second preset time length can be set according to actual needs, and the first preset time length and the second preset time length do not have a necessary time relationship; the first preset time and the second preset time can be set to be the time which can be divided by 1000 milliseconds, and the first preset time can be integral multiple of the second preset time, so that the calculation is convenient and the storage management efficiency is improved; in some embodiments, to accommodate typical usage requirements, the first preset duration may be set to 100 milliseconds and the second preset duration may be set to 10 milliseconds.

And through a data life cycle control function mechanism, the address space is released by emptying the cache for long-time useless data.

Fig. 3 is a schematic diagram of a structure of a method for implementing data array management based on a parallel RAM according to a specific embodiment of the present application, and as shown in fig. 3, some embodiments of the present application provide a method 300 for implementing data array management based on a parallel RAM, where the scheme shares read-write address lines of multiple RAMs, and all other signal lines are independent. According to the scheme, data can be cached, according to a characteristic address (which can be a characteristic bit field or a superior channel following indication) of cached data, the data can be stored into the RAM according to the address, when the address conflicts, the data can be stored into the 2 nd RAM, and so on, 8 RAMs are arranged. The descriptor storage management module is the core of the scheme, and has the functions of read-write control, overtime clearing, query, write-in and the like of each managed RAM.

A Bitmap mechanism is established, Bitmap synchronously indicates the data validity of each memory cell in 8 blocks of RAM, and after data written in a certain address of a certain RAM is valid, the address position mark value of the block of RAM in a Bitmap (two-dimensional array) is set to be 1. Correspondingly, when a certain RAM space is emptied, the address bit mark value of the block RAM in the Bitmap is set to be 0.

The method supports data extraction, access and query of the RAM, supports inputting of query addresses, controls 8 RAMs to simultaneously read data contents of respective addresses by the descriptor storage management module when an external request for querying data of a certain RAM address is sent to the descriptor storage management module, judges whether the data of each RAM is valid according to the Bitmap validity, sends the original data read to a request querier if the data of each RAM is valid, and outputs the data to 0 if the Bitmap is invalid.

The descriptor storage management module identifies an external cache clearing request, sets the data of the corresponding storage address of the corresponding RAM in the Bitmap to 0, represents clearing (but not really clearing the data in the RAM), and is used for clearing the cache space, so that the address space can be opened for writing.

The descriptor storage management module sets an internal counter and executes the function of counting the survival time of the data descriptor in the RAM of the counting period according to the value of the configuration counter. The descriptor storage management module starts a round of operation of subtracting the count value of the cache data life cycle every 100ms according to default setting, simultaneously reads data of 8 RAMs (data validity is indicated according to Bitmap), reads data of 0 address space of the 8 RAMs from 0 address, the Bitmap indicates the data validity of each RAM, if the data validity is valid, the data life cycle bit field value of the RAM is subtracted and written back to the address space, and if the life time is zero, the operation is not carried out. If the Bitmap indicates that the RAM is invalid, no operation is performed on the RAM.

The descriptor storage management module is provided with an internal counter, a data overtime recovery function with the memory time of 0 in RAM of a counting period is executed according to the value of a configuration counter, the descriptor storage management module starts a round of cache data life period overtime recovery operation every 10ms according to default setting, the descriptor storage management module simultaneously reads data of 8 RAMs (data validity is indicated according to bitmaps), the data of 0 address space of the 8 RAMs are read from 0 addresses, the bitmaps indicate the data validity of each RAM, if the data validity is valid and the data life period bit field value of the RAM is not 0, the recovery operation is not executed, if the life time is zero, the recovery operation is carried out, the corresponding bitmaps are set to be 0, and the address data are output. If the Bitmap indicates that the RAM is invalid, no operation is performed on the RAM.

And simultaneously reading and writing the RAMs by unified control, and independently controlling the reading and writing of the RAMs by utilizing a Bitmap establishing method according to the actual condition of each RAM at the current moment. For example, in the current state, to reduce the lifetime value by one for 0x0a addresses of 8 RAMs, the control module may uniformly enter the 8 RAMs into the control mode, but since there may be only 6 RAMs with 0x0a at the address, and there is a situation of read-write collision such as the RAMs being emptied in the 6 RAMs, the implementation method of the present invention may independently control the actual situation of each RAM at that time, perform no lifetime reduction operation for the empty RAM, and perform collision wait for the RAM with read-write collision. The method improves the use efficiency of the parallel operation of the multiple RAMs, and the method has rich functions of managing the data in the RAMs.

In this embodiment, the simultaneous read and write operations of 8 RAMs are only used as an example, and the number of RAMs is not specifically limited, and the number of RAMs is only 2 or more, so that parallel control of more than 1 RAM is achieved, and in fact, the greater the number of RAMs, the higher the control efficiency.

The technical effect of the scheme is as follows:

1. in the prior art, the operation is basically carried out on the independent RAM, and the logical copy is carried out on the upper control RAM module, so that the operation of a plurality of RAMs is controlled. The method is used for simultaneously carrying out unified operation on a plurality of RAMs, and independently controlling reading and writing of each RAM under unified operation according to the Bitmap effective indication.

2. The method increases the control and management of the data life cycle in the RAM, can empty long-time useless data, and improves the utilization rate of data cache. When the execution survival time of the data in the RAM is decreased and the data in the RAM are recovered, the operation is uniformly performed on the plurality of RAMs at the same time, if the RAM with read-write conflict exists, the RAM is waited to be executed, and the operation is performed when the conflict is over.

3. A Bitmap indication RAM data validity mechanism is established for judging whether the RAM address space data is valid or not, and when a plurality of RAMs operate, the RAM read-write operation with data is independently controlled according to the Bitmap indication.

Fig. 4 is a schematic structural diagram of a parallel RAM-based data array management apparatus according to an embodiment of the present invention, and as shown in fig. 4, the parallel RAM-based data array management apparatus 400 of the present invention may include:

the transceiver module 401 is configured to receive a data management request, and determine a request type and a feature address corresponding to the data management request;

the control module 402 is used for inquiring the storage state of the corresponding storage unit of the characteristic address in each RAM;

a processing module 403, configured to perform corresponding processing on each RAM according to the request type.

In this embodiment, the specific processing of the transceiver module 401, the control module 402 and the processing module 403 of the parallel RAM-based data array management apparatus and the technical effects thereof can refer to the related descriptions of steps 101 to 104 in the corresponding embodiment of fig. 1, which are not described herein again.

In some embodiments, when the request type corresponding to the data management request is a cache data request, the processing module 403 is specifically configured to:

In some embodiments, when the request type corresponding to the data management request is a query data request, the processing module 403 is specifically configured to:

In some embodiments, when the request type corresponding to the data management request is a clear data request, the processing module 403 is specifically configured to:

and setting the storage state of the storage unit corresponding to the characteristic address as writable.

In some embodiments, as shown in fig. 4, the apparatus further comprises:

a Bitmap module 404, configured to correspondingly store a storage state of each storage unit of each RAM;

the control module 402 is specifically configured to query the storage states of the feature addresses stored in the Bitmap module 404 in each RAM corresponding to the storage locations.

In some embodiments, the processing module 403 is further configured to subtract one from the cache data lifetime count value stored in the storage unit of each RAM by taking a first preset time period as a period; and setting the storage state of the storage unit with the survival cycle count value of the cache data stored in each RAM as 0 to be writable by taking the second preset time length as a cycle.

It should be noted that details of implementation and technical effects of each module in the data array management device based on the parallel RAM provided in the embodiment of the present disclosure may refer to descriptions of other embodiments in the present disclosure, and are not described herein again.

The embodiment of the application discloses a storage device, including: a data array composed of more than two RAMs in parallel and any one of the data array management devices based on the parallel RAMs for managing the data array.

The embodiments of the present application are not limited to the specific form of the above-mentioned storage device, and the storage device may include a chip, a removable storage device, a computer, an intelligent appliance, a removable electronic device, a server, etc., and the storage device described in the embodiments of the present application is intended to include, but not be limited to, these and any other suitable types of memories.

The technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for parallel RAM-based data array management, the method comprising:

2. The method according to claim 1, wherein when the request type corresponding to the data management request is a cache data request, the performing corresponding processing on each RAM according to the request type includes:

3. The method according to claim 1, wherein when the request type corresponding to the data management request is a query data request, the performing corresponding processing on each RAM according to the request type includes:

outputting the data content of which the storage state of the corresponding storage unit is unwritable;

4. The method according to claim 1, wherein when the request type corresponding to the data management request is a clear data request, the performing corresponding processing on each RAM according to the request type includes:

5. The method according to any one of claims 1 to 4, further comprising:

6. A parallel RAM-based data array management apparatus, the apparatus comprising:

7. The apparatus according to claim 6, wherein when the request type corresponding to the data management request is a cache data request, the processing module is specifically configured to:

8. The apparatus according to claim 6, wherein when the request type corresponding to the data management request is a query data request, the processing module is specifically configured to:

9. The apparatus according to claim 6, wherein when the request type corresponding to the data management request is a clear data request, the processing module is specifically configured to:

10. A storage device, the storage device comprising: a data array of two or more RAMs in parallel and a parallel RAM based data array management apparatus as claimed in any one of claims 6 to 9 for managing the data array.