CN111398996A - Surveying and mapping satellite navigation receiver - Google Patents
Surveying and mapping satellite navigation receiver Download PDFInfo
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- CN111398996A CN111398996A CN202010186227.5A CN202010186227A CN111398996A CN 111398996 A CN111398996 A CN 111398996A CN 202010186227 A CN202010186227 A CN 202010186227A CN 111398996 A CN111398996 A CN 111398996A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/14—Receivers specially adapted for specific applications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
- G01S19/37—Hardware or software details of the signal processing chain
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- Radar, Positioning & Navigation (AREA)
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- Computer Networks & Wireless Communication (AREA)
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- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention discloses a surveying and mapping satellite navigation receiver, which comprises an FPGA processing module and a processor, wherein the FPGA processing module comprises: the ADC data storage module is used for reading, writing and storing the acquired ADC digital signals; the multi-path selection controller is used for reading ADC data in the ADC dual-port RAM; the control parameter storage module is used for reading, writing and storing the control parameters transmitted by the processor; the parallel unit operation module is used for finishing scheduling and calculation of related operation according to ADC data and control parameters; the related value double-port RAM module is used for reading, writing and storing related values of related operation; and the interruption and scheduling control module is used for automatically interrupting after all the calculations of the parallel unit operation module are completed and informing the processor to read the control parameters and the related values required by the operation of the tracking loop. The invention uses the dual-port RAM to complete the rate conversion, so that a plurality of radio frequency channels share one correlator channel, thereby effectively saving FPGA resources.
Description
Technical Field
The invention relates to the technical field of global satellite navigation receivers, in particular to a surveying and mapping satellite navigation receiver.
Background
At present, with the development of science and technology, many countries and regions build independent global satellite navigation systems, and four major satellite navigation system infrastructures are completed, mainly including GPS in the united states, G L ONASS in russia, beidou in china, and Galileo in the european union.
Because the number of satellites and the frequency bands of the satellites available at any position around the world are remarkably increased, which brings a new challenge to a satellite navigation receiver, the traditional mapping type satellite navigation receiver uses an FPGA to realize the acquisition and tracking of baseband signals, and because the number of the satellites and the frequency bands are increased, the traditional processing method cannot meet the tracking of all signals, and the tracking can be realized only by replacing the FPGA with a larger scale, thereby further increasing the hardware cost. In addition, the GNSS signals of the conventional satellite navigation system are of various types, and a large amount of resources are required to be spent on baseband signal processing after the signals are received, so that the waste of FPGA resources is caused.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a surveying and mapping satellite navigation receiver, which uses a dual-port RAM to complete rate conversion, so that a plurality of radio frequency channels share one correlator channel, and FPGA resources are effectively saved.
The purpose of the invention is realized by adopting the following technical scheme:
a receiver for mappable satellite navigation comprising an FPGA processing module and a processor, the FPGA processing module comprising:
the ADC data storage module comprises a plurality of ADC double-port RAMs and is used for reading, writing and storing the acquired ADC digital signals;
the multi-path selection controller is bidirectionally connected with the ADC data storage module and is used for reading ADC data in the ADC dual-port RAM;
the control parameter storage module is bidirectionally connected with the processor and is used for reading and writing and storing the control parameters transmitted by the processor;
the parallel unit operation module is bidirectionally connected with the multi-path selection controller and the control parameter storage module and is used for finishing the scheduling and calculation of related operation according to the ADC data and the control parameters;
the related value double-port RAM module is connected with the parallel unit operation module and the processor and is used for reading, writing and storing related values of related operation;
and the interruption and scheduling control module is connected with the processor and is used for automatically interrupting after all the calculations of the parallel unit operation module are completed and informing the processor to read the control parameters and the related values required by the operation of the tracking loop.
Further, the parallel unit operation module includes:
the parallel unit scheduling module is bidirectionally connected with the control parameter storage module and is used for reading the control parameters required by executing the relevant operation and writing the updated control parameters into the control parameter storage module after the execution is finished;
the pseudo code processing module is connected with the parallel unit scheduling module, generates pseudo codes according to the control parameters, and performs combined packaging and storage on the pseudo codes;
the parallel carrier stripping module is connected with the ADC dual-port RAM and is used for processing the packed ADC data read from the ADC dual-port RAM to realize parallel carrier stripping;
the parallel pre-integration control module is connected with the parallel carrier stripping module, and is used for realizing parallel integration and accumulation on the parallel data subjected to carrier stripping according to the code element period and the correlator interval, so that the signal processing speed is reduced;
and the parallel correlation operation module is connected with the pseudo code processing module, the parallel carrier stripping module and the parallel pre-integration control module, and is used for carrying out pseudo code stripping and accumulation on the pre-integrated parallel data and the packed pseudo codes to calculate a correlation value.
Further, the parallel correlation operation module is bidirectionally connected with the correlation value dual-port RAM module, and the correlation value obtained by calculation is stored in the correlation value dual-port RAM module.
Further, the pseudo-code processing module comprises:
the pseudo code generator module is connected with the parallel unit scheduling module and generates various pseudo codes according to the control parameters;
the pseudo code packing module is connected with the pseudo code generator module, selects the input pseudo code according to the control parameters and performs combined packing according to the number of the set code elements;
and the pseudo code double-port RAM module is connected with the parallel unit scheduling module and the pseudo code packing module and is used for storing the packed pseudo codes and reading the packed pseudo codes by the parallel correlation operation module.
Further, the control parameters comprise code NCO frequency words, initial code NCO phases, carrier NCO frequency words, initial carrier NCO phases, ADC addresses corresponding to code starting positions and epoch periods for integration.
Further, the processor obtains the control parameters and the related values of all the channels through the bus, extracts the observed values and carries out loop tracking, and writes the updated control parameters into the control parameter storage module through the bus.
Compared with the prior art, the invention has the beneficial effects that:
the dual-port RAM is provided with two sets of completely independent data lines, address lines, clocks and read-write control lines, allows two independent systems to simultaneously carry out random access on the dual-port RAM, and can realize data rate conversion, so that a plurality of common channels share one correlator channel, and FPGA resources are effectively saved.
Drawings
FIG. 1 is a schematic block diagram of an overall surveying satellite navigation receiver according to the invention;
FIG. 2 is a schematic diagram of a parallel unit operation module of the surveying and mapping satellite navigation receiver according to the present invention;
FIG. 3 is a circuit diagram of a single-channel data processing circuit in the surveying satellite navigation receiver according to the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
A surveying and mapping satellite navigation receiver, as shown in FIG. 1, includes an FPGA processing module and a processor.
The FPGA processing module comprises an ADC data storage module, a multi-path selection controller, a parallel unit operation module, a control parameter storage module, an interruption and scheduling control module and a related value double-port RAM module.
The ADC data storage module is set as a double-port RAM, baseband ADC digital signals input by sampling are combined together according to a set clock period and are packed and written into the double-port RAM, and packed ADC data can be read out from the double-port RAM according to the requirement in subsequent operation. The dual-port RAM is a configurable storage unit built in the FPGA, is provided with two completely independent data lines, address lines, clocks and read-write control lines, and allows two independent systems to simultaneously carry out random access on the two independent systems. The conversion of data rate can be realized by using the dual-port RAM, single-path data of the serial ADC is converted into multi-path parallel ADC data, the original lower ADC clock rate is used for storing the data, the parallel ADC data is read by using a higher clock, the multiplexing of correlator channels is realized, and hardware resources are saved.
And the ADC data is an intermediate frequency analog signal with a certain frequency point continuously changed in satellite navigation, and is quantized and converted into a discrete digital signal. In this embodiment, the ADC digital signals are combined together according to the digital signals of every 8 clock cycles, and then written into the dual-port RAM in one cycle after completion.
The receiver generally comprises a plurality of radio frequency channels, and each radio frequency channel corresponds to one ADC; in fig. 1, (m +1) radio frequency channels are assumed, each radio frequency channel corresponds to one ADC dual-port RAM, and ADC data is circularly stored and written into the corresponding ADC dual-port RAM after being packed.
The control parameter storage module is a dual-port RAM and is used for receiving the control parameters transmitted by the processor and storing the control parameters in the dual-port RAM, the control parameters can be read out from the control parameter storage module during subsequent control, and new parameters can also be written into the dual-port RAM; the control parameters include, but are not limited to, a code NCO frequency word, an initial code NCO phase, a carrier NCO frequency word, an initial carrier NCO phase, an ADC address corresponding to a code start position, an epoch period (typically in milliseconds) over which integration is performed, and the like.
The related value dual-port RAM module stores related values of related operations, the parallel unit operation module reads initial related values first during execution, and new related values are written into the related value dual-port RAM module after the related operations are completed.
And the multi-path selection controller reads the packed ADC data from the corresponding ADC dual-port RAM according to the instruction of the parallel unit operation module and sends the packed ADC data to the parallel unit operation module. Corresponding control parameters can be configured according to requirements, and one parallel unit operation module can process one path of ADC data or multiple paths of ADC data in a time-sharing mode. In addition, each path of ADC data comprises a plurality of satellite signals, and the parallel unit operation module is also used for time-sharing processing, so that resource sharing is realized to the maximum extent, and the aim of effectively saving FPGA resources is fulfilled.
And the parallel unit operation module is connected with the ADC dual-port RAM module, the control parameter dual-port RAM module and the related value dual-port RAM module to finish the scheduling and calculation of related operations.
And the interrupt and scheduling control module generates interrupt after all the parallel unit operation modules finish the calculation and informs the processor to read the control parameters and the related values required by the operation of the tracking loop. And after the operation of the processor is finished, the control parameter double ports are written into the control parameter double port RAM, and all parallel unit operation modules of the interrupt and scheduling control module are informed to continue to calculate. Therefore, a closed loop can be formed between the FPGA and the processor, the FPGA realizes the correlation function of the correlator and provides correlation values and corresponding control parameters, and the processor performs loop operation and PVT calculation.
The process of the parallel unit operation module for processing the data of the single channel in a time-sharing manner is as follows: reading and analyzing the control parameters from the control parameter dual-port RAM module, and writing new control parameters into the control parameter dual-port RAM module after the operation is completed; reading an initial value of correlation operation from the correlation value dual-port RAM module, and writing a new correlation value into the correlation value dual-port RAM module after the correlation operation is completed; selecting a corresponding pseudo code generator according to the control parameters, packaging the generated pseudo codes and storing the packaged pseudo codes into a pseudo code dual-port RAM; and reading packed ADC data from a corresponding ADC dual-port RAM module according to the control parameters, carrying out parallel carrier stripping and parallel pre-integration control on the packed ADC data, and then carrying out parallel correlation operation on the parallel data subjected to parallel pre-integration and packed pseudo codes read from the pseudo code dual-port RAM. After the single parallel unit operation module finishes the data processing of all channels corresponding to a certain ADC data, other ADC data can be processed, and the specific execution process is determined by the control parameters written into the control parameter dual-port RAM module by the processor.
Further, as shown in fig. 2, the parallel unit operation module includes:
the parallel unit scheduling module is a scheduling center for task execution of the parallel unit operation module, is connected with the control parameter dual-port RAM module, can read control parameters required by task execution, and writes the updated control parameters into the control parameter dual-port RAM module after the task execution is finished;
a pseudo code generator module, wherein it is assumed that a certain parallel unit operation module can generate a plurality of different pseudo codes, and the generated pseudo codes are determined by control parameters given by a parallel unit scheduling module;
the multi-path selection and pseudo code packing module is used for selecting the input pseudo codes to pack according to the control parameters, namely, the pseudo codes are combined according to the number of set code elements;
the pseudo code double-port RAM module stores the packed pseudo codes and reads the packed pseudo codes by the parallel correlation operation module;
the parallel carrier stripping module is used for processing the packed ADC data read from the ADC dual-port RAM to realize parallel carrier stripping, namely one clock cycle realizes carrier stripping on the input ADC data of a plurality of clock cycles;
the parallel pre-integration control module realizes parallel integration and accumulation on the parallel data after carrier stripping according to the code element period and the correlator interval, and reduces the processing speed of signals;
and the parallel correlation operation module is used for carrying out pseudo code stripping and accumulation on the pre-integrated parallel data and the packed pseudo codes to calculate a correlation value.
The parallel unit operation module increases the parallel characteristic relative to the common calculation module. In order to better explain the function of the parallel unit operation module, the signal processing process is described below by using a single circuit.
As shown in fig. 3, the parallel unit operation module includes a preprocessing circuit, and performs parallel pre-integration processing on ADC data through the preprocessing circuit according to the control parameter, where the preprocessing circuit includes a digital frequency synthesizer (NCO), a multiplier module, an accumulator module, and a pre-integration controller module; the digital frequency synthesis module (NCO) is connected with the ADC data storage module and is used for sampling from the ADC data storage module to obtain a baseband signal ADC with the speed of fs; the output ends of the digital frequency synthesis module (NCO) and the ADC data storage module are connected with the multiplier module and are used for multiplying a baseband signal ADC and the orthogonal carrier frequency generated by the digital frequency synthesis module to obtain signals data _ mi and data _ mq; the output ends of the multiplier module and the pre-integration control module are connected with the accumulator module, so that the accumulator module outputs signals data _ i and data _ q with different rates from the signals data _ mi and data _ mq.
The pre-integration control module has two functions, one is to convert the signal to fb (f) rate by the accumulation time τ (corresponding to one symbol width) of the NCO control signals data _ mi and data _ mqb1/τ, fb is one enable signal); another function is to change the relative starting point of the accumulator accumulation, i.e. the initial code NCO phase.
The two functions are realized in the following modes: different initial code NCO phases correspond to different code intervals by controlling the code NCO frequency words and the initial code NCO phases; the code NCO is composed of a 40-bit accumulator (bit width can be changed according to requirements), an initial code NCO phase is loaded before the first operation, the code NCO frequency is added to each clock afterwards, each time the code NCO overflows, the fact that the accumulation of data _ mi and data _ mq corresponding to one chip is finished is shown, corresponding data _ i and data _ q are output, code correlators with different intervals are achieved, after the data accumulation of one code element width, the operation amount of follow-up code stripping can be reduced, and parallel code stripping and integral accumulation of a plurality of correlators can be achieved conveniently and better.
In addition, the parallel unit operation module further comprises a pseudo random code module (prn), a multiplier module and an accumulator module, wherein the pseudo random code module (prn) is connected with the pseudo code processing module, the output end of the accumulator module generating signals data _ i and data _ q and the output end of the pseudo random code module are both connected with the multiplier module, so that the data _ i and data _ q are multiplied by a locally generated pseudo random sequence, and then a local pseudo code is stripped; the output end of the multiplier module is connected with the input end of the accumulator module, stripped data are accumulated according to the pseudo code period to obtain 1ms accumulation results I and Q which are used for extracting error parameters of a carrier ring and a code ring, and a multipath correlator can be realized by setting different initial code NCO phases.
The processor obtains control parameters and related values of all channels through the bus, extracts the observed value and carries out loop tracking, writes the updated control parameters into the control parameter storage module through the bus, and prepares for the next parallel related operation; the observed value is used for realizing positioning resolving and comprises a pseudo range, a whole-cycle phase, a carrier-to-noise ratio and a Doppler frequency.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.
Claims (6)
1. A receiver for mappable satellite navigation comprising an FPGA processing module and a processor, wherein said FPGA processing module comprises:
the ADC data storage module comprises a plurality of ADC double-port RAMs and is used for reading, writing and storing the acquired ADC digital signals;
the multi-path selection controller is bidirectionally connected with the ADC data storage module and is used for reading ADC data in the ADC dual-port RAM;
the control parameter storage module is bidirectionally connected with the processor and is used for reading and writing and storing the control parameters transmitted by the processor;
the parallel unit operation module is bidirectionally connected with the multi-path selection controller and the control parameter storage module and is used for finishing the scheduling and calculation of related operation according to the ADC data and the control parameters;
the related value double-port RAM module is connected with the parallel unit operation module and the processor and is used for reading, writing and storing related values of related operation;
and the interruption and scheduling control module is connected with the processor and is used for automatically interrupting after all the calculations of the parallel unit operation module are completed and informing the processor to read the control parameters and the related values required by the operation of the tracking loop.
2. The receiver according to claim 1, wherein the parallel unit operation module comprises:
the parallel unit scheduling module is bidirectionally connected with the control parameter storage module and is used for reading the control parameters required by executing the relevant operation and writing the updated control parameters into the control parameter storage module after the execution is finished;
the pseudo code processing module is connected with the parallel unit scheduling module, generates pseudo codes according to the control parameters, and performs combined packaging and storage on the pseudo codes;
the parallel carrier stripping module is connected with the ADC dual-port RAM and is used for processing the packed ADC data read from the ADC dual-port RAM to realize parallel carrier stripping;
the parallel pre-integration control module is connected with the parallel carrier stripping module, and is used for realizing parallel integration and accumulation on the parallel data subjected to carrier stripping according to the code element period and the correlator interval, so that the signal processing speed is reduced;
and the parallel correlation operation module is connected with the pseudo code processing module, the parallel carrier stripping module and the parallel pre-integration control module, and is used for carrying out pseudo code stripping and accumulation on the pre-integrated parallel data and the packed pseudo codes to calculate a correlation value.
3. The receiver of claim 2, wherein the parallel correlation module is bi-directionally coupled to the correlation dual port RAM module, and the correlation values are stored in the correlation dual port RAM module.
4. The receiver of claim 2, wherein the pseudo-code processing module comprises:
the pseudo code generator module is connected with the parallel unit scheduling module and generates various pseudo codes according to the control parameters;
the pseudo code packing module is connected with the pseudo code generator module, selects the input pseudo code according to the control parameters and performs combined packing according to the number of the set code elements;
and the pseudo code double-port RAM module is connected with the parallel unit scheduling module and the pseudo code packing module and is used for storing the packed pseudo codes and reading the packed pseudo codes by the parallel correlation operation module.
5. The receiver of claim 1, wherein the control parameters comprise a code NCO frequency word, an initial code NCO phase, a carrier NCO frequency word, an initial carrier NCO phase, an ADC address corresponding to a code start position, an epoch period over which to integrate.
6. The receiver of claim 1, wherein the processor obtains the control parameters and the correlation values of all channels via a bus, extracts the observation values and performs loop tracking, and writes the updated control parameters into the control parameter storage module via the bus.
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| CN117560069A (en) * | 2024-01-12 | 2024-02-13 | 南京典格通信科技有限公司 | Broadcast number system and method for satellite terminal data link verification |
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