CN102545957A - General binary phase shift keying (BPSK) signal rapid acquisition module - Google Patents
General binary phase shift keying (BPSK) signal rapid acquisition module Download PDFInfo
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Abstract
The invention discloses a general binary phase shift keying (BPSK) signal rapid acquisition module which includes a preprocessing unit, a parallel correlation unit and an FFT and determination unit. The preprocessing unit preprocesses the baseband digital signal adc sampled and input by an analog-to-digital converter (ADC), and provides digital signals data_i and data_q close to zero frequency for the parallel correlation unit. The parallel correlation unit performs cyclic storage of the digital signals data_i and data_q and local pseudo code generation and storage, and also performs parallel correlation operation on the pseudo code and data_i and data_q. The FFT and determination unit performs detection and determination of signals in a frequency domain. The inventive general BPSK signal rapid acquisition module can compatibly acquire various signal system GNSS (global navigation satellite system) signals (such as GPS C/A code, BD C code, and GLONASS C code), and adopts a dual-port RAM (random access memory) for matched filtering, so as to effectively save FPGA (field programmable gate array) resources, achieve faster acquisition speed and realize interference detection function.
Description
Technical field
The invention belongs to the signal capture technical field in the telecommunication technology, relate to a kind of signal capture module, the quick trapping module of especially a kind of general bpsk signal.
Background technology
The method of present acquiring pseudo code has multiple, like sliding correlation method, sequential detection method and matched filtering method.The advantage of sliding correlation method is to realize that simply spent FPGA resource is less; Shortcoming is when local pseudo-code and reception pseudo-code phase difference are big, need experience very long capture time, realizes difficulty of quick capture ratio.Sequential Detection Algorithm is applicable to the situation of high s/n ratio, and when frequency deviation is big, can't adapt to, so do not adopt.The remarkable advantage of matched filtering method is that speed is fast, and capture time is short, and realization is caught fast easily; Shortcoming is when pseudo-code is long code, and the FPGA resource that designing institute expends is bigger.
Summary of the invention
The objective of the invention is to overcome the shortcoming of above-mentioned prior art; A kind of general bpsk signal quick capturing method is provided; This method can compatible be caught the GNSS signal of multiple signal system, and it uses dual port RAM to accomplish matched filtering, has effectively saved the FPGA resource; Not only acquisition speed is fast, and possesses interference check function.
The objective of the invention is to solve through following technical scheme:
The quick trapping module of this general bpsk signal is divided into three unit:
1) pretreatment unit
Pretreatment unit comprises a numerical frequency synthesis module, two multiplication module, two accumulator module and a preparatory integral controller module; Pretreatment unit carries out preliminary treatment to the baseband digital signal adc of ADC sampling input, provides zero-frequency neighbouring digital signal data_i and data_q for parallel correlation unit.
2) parallel correlation unit
Parallel correlation unit comprises a pseudo-code and produces controller module and n parallel correlation module, and each parallel correlation module comprises three dual port RAMs, two multiplication module and two accumulator module; First dual port RAM in all parallel correlation modules is formed first group of dual port RAM chain, and second dual port RAM formed second group of dual port RAM chain, and the 3rd dual port RAM formed the 3rd group of dual port RAM chain; Parallel correlation unit carries out the circulation storage of digital signal data_i and data_q, and local pseudo-code produces and storage, and carries out the parallel related operation of pseudo-code and data_i and data_q;
3) FFT and decision unit
FFT and decision unit comprise a string, and also modular converter, a N point FFT module, single spectrum peak detection module, the interior maximum of one-period detect and a judging module; Said FFT and decision unit carry out detection and the judgement of signal at frequency domain.
Further, in the processing procedure of above-mentioned pretreatment unit: (1) ADC sampling obtains the baseband signal adc that speed is fa, and the quadrature carrier frequency that adc and numerical frequency synthesis module produce multiplies each other, and obtains zero-frequency neighbouring signal data_mi and data_mq; (2) the integral controller module comprises two functions in advance, and one is the time of the adding up τ through NCO control signal data_mi and data_mq, and it is data_i and the data_q of fb that signal transformation is become speed, and wherein fb is an enable signal, fb=1/ τ; Another is to change the relative starting point τ that accumulator adds up.
Data_i and the data_q two paths of signals of above-mentioned parallel correlation unit after with preparatory integration deposits first group of dual port RAM chain and second group of dual port RAM chain respectively in, imports the 3rd group of dual port RAM chain with what sign indicating number produced one-period that controller produces for a sign indicating number sequence simultaneously.
The present invention has following beneficial effect:
The quick trapping module of the general bpsk signal of the present invention can compatible be caught the GNSS signal (like GPS C/A sign indicating number, BD C sign indicating number, GLONASS C sign indicating number or the like) of multiple signal system; Owing to adopted in the parallel correlation unit of the present invention dual port RAM to accomplish matched filtering, effectively saved the FPGA resource, and it can make acquisition speed faster, can possess interference check function.
Description of drawings
Fig. 1 is a pretreatment unit sketch map of the present invention;
Fig. 2 is a parallel correlation unit sketch map of the present invention;
Fig. 3 is FFT of the present invention and decision unit sketch map;
Fig. 4 is a dual port RAM sketch map of the present invention;
Fig. 5 is the sketch map of numerical frequency synthesis module NCO of the present invention.
Embodiment
The quick trapping module of general bpsk signal of the present invention comprises pretreatment unit, and parallel correlation unit and FFT and decision unit are elaborated to each unit below in conjunction with accompanying drawing:
Pretreatment unit
As shown in Figure 1: pretreatment unit carries out preliminary treatment to the baseband digital signal adc of ADC sampling input, provides zero-frequency neighbouring digital signal data_i and data_q for parallel correlation unit.This unit comprises a numerical frequency synthesis module (NCO), two multiplication module, two accumulator module and a preparatory integral controller module.The course of work of this unit is: the ADC sampling obtains the baseband signal adc that speed is fa, and the quadrature carrier frequency that adc and NCO produce multiplies each other, and obtains zero-frequency neighbouring signal data_mi and data_mq.The integral controller module comprises two functions in advance; One is the time of the adding up τ through NCO control signal data_mi and data_mq; It is fb (fb=1/ τ that signal transformation is become speed; Fb is an enable signal) data_i and data_q, another is to change the relative starting point τ that accumulator module adds up.
Above numerical frequency synthesis module (NCO) mainly is made up of digital controlled oscillator NCO and SIN/COS look-up table, and is as shown in Figure 5.The carrier number controlled oscillator is made up of frequency/phase register, phase accumulator.The spill over of phase accumulator is exactly a carrier wave NCO output frequency.
If use f
sThe expression sampling clock, N representes carrier wave NCO phase accumulator figure place, and M representes carrier wave NCO increment size, and F representes carrier wave NCO output frequency, then:
In case N and f
sDecide, control word M and F have just possessed one-to-one relationship.
The frequency adjustment range of carrier wave NCO must be considered Doppler frequency shift and reference frequency error, and will have higher resolution, so that on the reasonable time precision, keep homophase with satellite-signal.The frequency and the phase place of frequency and the output of phase control words control carrier signal, in signal acquisition phase and carrier frequency traction stage, frequency control word plays a leading role; In the signal trace stage, phase control words plays a decisive role.
Parallel correlation unit
Parallel correlation unit is realized the circulation storage of digital signal data_i and data_q, and produces and storage with local pseudo-code, and realizes the parallel related operation of pseudo-code and data_i and data_q, output correlation (I1, I2....In; Q1, Q2....Qn).
As shown in Figure 2: parallel correlation unit comprises a pseudo-code and produces controller module and n parallel correlation module, and wherein n is greater than 1.Each parallel correlation module comprises three dual port RAMs (RAM_ai, RAM_bi, RAM_ci, i represent the sequence number of parallel correlation module), two multiplication module and two accumulator module.First dual port RAM in all parallel correlation modules is formed first group of dual port RAM chain (RAM_a1; RAM_a2....RAM_an); Second dual port RAM formed second group of dual port RAM chain, and (RAM_b1, RAM_b2....RAM_bn), the 3rd dual port RAM formed the 3rd group of dual port RAM chain.
The dual port RAM of parallel correlation unit is on a SRAM memory, to have two covers fully independently data wire, address wire and read-write control line, and allow two independently system simultaneously this memory is carried out the visit of randomness.Promptly share the formula multiport memory.Fig. 4 has provided the rough schematic of realizing dual port RAM among the FPGA.The course of work of dual port RAM is: a port is that data are write inbound port, and clka is the sampling clock of AD, and WE wea is produced by preparatory integral control unit.When wea is high, data dina is write address addra, addra adds 1 then, for data input is next time prepared.The b port is the data read outbound port, and clkb is the high-speed computation clock, and the data doutb that address addrb is corresponding reads.
The course of work of parallel correlation unit is:
(1) deposit data_i behind the preparatory integration and data_q two paths of signals in first group of dual port RAM chain and second group of dual port RAM chain respectively, the pseudo-code sequence that simultaneously pseudo-code is produced the one-period that controller module produces is imported the 3rd group of dual port RAM chain;
When (2) RAM_a1 (first dual port RAM of first group of dual port RAM chain) receives the I circuit-switched data data_i behind the preparatory integration; Fb is a high level; Write data through clock fa the address wr_addr of RAM_a1; Wr_addr adds 1 simultaneously, has so just write the inside, wr_addr address to data, has realized that also the circulation of data in RAM_a1 writes.The reading of RAM_a1 after clock fc detects the fb high level read the data among the RAM_a1; At first read the data of (wr_addr-1) address; Successively decrease successively in the address then, reads the data of wr_addr address at last, and RAM_a1 utilizes speed to read the data among the RAM_a1 successively for the clock of fc.Data in the data read process that address (wr_addr+1) is corresponding are read, and utilize register to latch to output to RAM_a2.The data of such first group of dual port RAM chain have realized writing in real time and reading of data, and second group of dual port RAM chain is the same with first group realization and function; The 3rd group of dual port RAM chain is consistent with first group basic function, and just after the pseudo-code of one-period produced completion, dual port RAM no longer write data, a sense data.
After needed pseudo-code all write in (3) the 3rd groups of dual port RAM chains, relevant cumulative process began to carry out, and was that example describes with the RAM_b1 in the 3rd group of dual port RAM chain of RAM_a1 in first group of dual port RAM chain in the parallel correlation unit 1 below.After reading clock fc and detecting the fb high level; (wr_addr-1) begins to successively decrease successively to read the data rd_data_a1 the RAM_a1 from the address; Read corresponding pseudo-code data rd_data_c1 among the RAM_c1 simultaneously, add device after rd_data_a1 and rd_data_c1 multiply each other.When corresponding data among RAM_a1 and the RAM_c1 all read add up finish after, the result is latched in register I
1In.For preventing that the dual port RAM data from writing and reading clashes, just the data that write are recently read at last.Fb must satisfy that (fc＞=fb*n) makes m the value of storing among the RAM_a1 and RAM_b1 when each fb high level arrives to read and to calculate between dual port RAM degree of depth m and the fc.
FFT and decision unit
Comprise a string and modular converter referring to Fig. 3: FFT and decision unit, a N point FFT module, maximum detection unit and a judging module in a single spectrum peak detection module, one-period.Realize detection and the judgement of signal to module at frequency domain.
The course of work of FFT and decision unit is following:
(1) the i time fb high level arrival n parallel correlation unit calculates separately homophase and quadrature correlation, n road correlation I1, I2....In; Q1 Q2....Qn) passes through I and the Q that goes here and there and convert serial output to.
(2) the serial output n I and the Q of ordering sends into N point FFT processing module as n plural number, after the fast Fourier transform, obtains n complex values (spectrum value).
(3) n complex values (spectrum value) carried out the spectrum peak detection, obtains power maximum Pmax_i and correspondent frequency component fre_i.
(4) the i time power maximum Pmax_i and correspondent frequency component fre_i send into maximum detection unit in the cycle; Maximum detection unit is obtained power maximum Pmax and the correspondent frequency component fre that once matees associated cyclic in cycle, once matees associated cyclic and has comprised the coupling correlated process M time.If Pmax is greater than thresholding then continue to mate correlated process and confirm; According to the pseudo-code phase information and the frequency information that obtain; The serial that starts 3 passage ch1, ch2, ch3 is relevant; It is consistent that the pseudo-code of these three passages starts phase place, and carrier frequency is respectively fre-fre_shift, fre, fre+fre_shift, further auxiliary affirmation frequency information.
(5) if search success confirmation or failure are then controlled as required.
(6), repeat said process and then can be used for detecting interference signal if the output of pn code generator is replaced to high level.
Claims (3)
1. the quick trapping module of general bpsk signal is characterized in that, this quick trapping module is divided into following three unit:
1) pretreatment unit
Pretreatment unit comprises a numerical frequency synthesis module, two multiplication module, two accumulator module and a preparatory integral controller module; Pretreatment unit carries out preliminary treatment to the baseband digital signal adc of ADC sampling input, provides zero-frequency neighbouring digital signal data_i and data_q for parallel correlation unit;
2) parallel correlation unit
Parallel correlation unit comprises a pseudo-code and produces controller module and n parallel correlation module, and each parallel correlation module comprises three dual port RAMs, two multiplication module and two accumulator module; First dual port RAM in all parallel correlation modules is formed first group of dual port RAM chain, and second dual port RAM formed second group of dual port RAM chain, and the 3rd dual port RAM formed the 3rd group of dual port RAM chain; Parallel correlation unit carries out the circulation storage of digital signal data_i and data_q, and local pseudo-code produces and storage, and carries out the parallel related operation of pseudo-code and data_i and data_q;
3) FFT and decision unit
FFT and decision unit comprise a string, and also modular converter, a N point FFT module, single spectrum peak detection module, the interior maximum of one-period detect and a judging module; Said FFT and decision unit carry out detection and the judgement of signal at frequency domain.
2. the quick trapping module of general bpsk signal according to claim 1; It is characterized in that; In the processing procedure of pretreatment unit: (1) ADC sampling obtains the baseband signal adc that speed is fa; The quadrature carrier frequency that adc and numerical frequency synthesis module produce multiplies each other, and obtains zero-frequency neighbouring signal data_mi and data_mq; (2) the integral controller module comprises two functions in advance, and one is the time of the adding up τ through NCO control signal data_mi and data_mq, and it is data_i and the data_q of fb that signal transformation is become speed, and wherein fb is an enable signal, fb=1/ τ; Another is to change the relative starting point τ that accumulator adds up.
3. the quick trapping module of general bpsk signal according to claim 1; It is characterized in that; Data_i and the data_q two paths of signals of said parallel correlation unit after with preparatory integration deposits first group of dual port RAM chain and second group of dual port RAM chain respectively in, imports the 3rd group of dual port RAM chain with what sign indicating number produced one-period that controller produces for a sign indicating number sequence simultaneously.
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| CN103018753A (en) * | 2012-08-09 | 2013-04-03 | 江苏科技大学 | GPS (Global Position System) signal digital correlator |
| CN103728632A (en) * | 2013-12-02 | 2014-04-16 | 西安合众思壮导航技术有限公司 | Satellite data capture device and capture method |
| CN103888167A (en) * | 2012-12-19 | 2014-06-25 | 西安合众思壮导航技术有限公司 | Signal acquisition method, device thereof and equipment with device |
| WO2016027727A1 (en) * | 2014-08-20 | 2016-02-25 | ソニー株式会社 | Reception device and reception method for global navigation satellite system, and program |
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Application publication date: 20120704 |