CN104834501A - L structure processor-based register and register operation method - Google Patents
L structure processor-based register and register operation method Download PDFInfo
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Abstract
The invention discloses an L structure processor-based register, comprising a storage unit, a read managing/controlling unit controlling the storage unit and a write managing/controlling unit; the storage unit comprises N independent random access storages, N is equal to the maximal number of all commands, which request to read the register, in the processor, and a read port and a write port of each random access storage can be operated in parallel; the read managing/controlling unit comprises an input/output port of a program driver for receiving request/sending a register reading operation, N read address output ports, N read data input ports and corresponding managing/controlling logic units; the write managing/controlling unit comprises an input/output port of the program driver for receiving request/ sending a register writing operation, a write address output port, a write data output port and corresponding control logic units. The structure is simple and the cost is low.
Description
Technical field
The present invention relates to a kind of register based on L architecture processor and register manipulation method.
Background technology
Along with the development of computer technology, a kind of novel computer system structure-L architecture computer (multi-core computer platform) is invented, L architecture computer, under the precondition not needing interrupt processing, can walk abreast at synchronization and perform multiprogramming concomitantly in same processor.The processor of L architecture computer structure is adopted to be called L architecture processor.
Register is the very important ingredient of of processor, and be not only user and work out its application software system and provide a great convenience, the processing speed also for improving processor serves critical effect.In the processor of traditional architectures, owing to only having one program in commission at synchronization, therefore only need design a set of register.But can walk abreast at synchronization and perform in the processor of multiprogramming concomitantly, namely in L architecture processor, the design of register just becomes the very important factor of a system for restricting combination property.
Share for multiprogramming if only arrange one group of register, obviously can not play multiprogramming and walk abreast and the advantage of concurrence performance at synchronization.If for every can walking abreast together all arranges one group of register with the program of concurrence performance, when walking abreast larger with the program number of channels of concurrence performance, then needing the number of the register arranged also will be comparatively large, obviously be infeasible.For another example the maximum permission of processor of fruit hard and fast rule walks abreast and is N (N > 1) with the number of channels of the program of concurrence performance and arranges N group register, can not play the advantage of L architecture processor equally well.
Summary of the invention
For the problems referred to above, the invention provides a kind of register based on L architecture processor and register manipulation method, register is designed by more cheap storage unit, substantially do not limit maximum permission to make L architecture processor to walk abreast and the object of the number of channels of concurrence performance program, structure is simple and cost is low; Further, the read operation of register or write operation effectively faster.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
Based on a register for L architecture processor, it is characterized in that, comprise memory cell, control store unit read management/control module and write management/control module;
Described memory cell comprises N number of independently random access memory, and N equals the maximum number of simultaneously asking read register in all instructions of processor, and the read port of each random access memory and write port can parallel work-flows;
Described management/control module of reading comprising an input/output end port having completed the driven by program device of read register operation for receiving request/transmission, N number ofly reading address output end mouth, N number of read data input port and corresponding management/steering logic unit;
Described write management/control module comprise an input/output end port having completed the driven by program device writing register manipulation for receiving request/transmission, write address output port, one write data-out port and corresponding steering logic unit.
Preferably, the degree of depth of described random access memory equals the maximum permission of processor and walks abreast/and the program number of channels of concurrence performance and per pass program allow the product of the maximum register number used, and the width of described random access memory equals the maximum number of digits of register.
Based on a method of operating for the register of L architecture processor, it is characterized in that, read operation step is as follows:
S01: if the present procedure driver that management/control module read by the register of L architecture processor requires that read register operates, go to step S02; Otherwise, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01;
S02: read the numbering obtaining n (n≤N) the individual register read required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S03: be set up the program Taoist monastic name of this road program before each register number, form the address of n random access memory;
S04: the address of n the random access memory drawn according to step S03, sends to n random access memory to read address register successively respectively, start the read operation of this n random access memory simultaneously, to read n data simultaneously;
S05: the n read by a step S04 data are written in n the unit that present procedure driver specifies, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01.
Write operation step is as follows:
S11: if the present procedure driver that management/control module write by the register of L architecture processor requires to write register manipulation, go to step S12; Otherwise, arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11;
S12: write the data obtaining the present procedure driver of management/control module and write back required for this driven by program device from the register of L architecture processor;
S13: write the numbering obtaining the register write back required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S14: be set up the program Taoist monastic name of this road program before this register serial number, form the address of a random access memory;
S15: data and step S14 obtain writes back address assignment to all random access memory by writing back of being obtained by step S12; Start the write operation of N number of random access memory, will the data write back be needed to write back in the address location of specifying of all random access memory simultaneously simultaneously; Arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11.
Design register by more cheap random access memory (RAM), for solving in the object of synchronization read/write multiple " register " data, adopt multiple can parallel work-flow, the RAM module of multiport preserves the content of many cover registers; According to the number needing the maximum number reading register data to determine to generate " register " copy in all instructions of processor simultaneously; In order to ensure the consistance of data, need write back that ' data of " register " will be write back in all " register " copies simultaneously.
The invention has the beneficial effects as follows: design register by more cheap storage unit, substantially do not limit maximum permission to make L architecture processor and walk abreast and the object of the number of channels of concurrence performance program, structure is simple and cost is low; Further, the read operation of register or write operation effectively faster.
Embodiment
Below in conjunction with specific embodiment, technical solution of the present invention is described in further detail, can better understand the present invention to make those skilled in the art and can be implemented, but illustrated embodiment is not as a limitation of the invention.
Based on a register for L architecture processor, comprise memory cell, control store unit read management/control module and write management/control module, each unit comprises corresponding interface, being specifically described as follows of unit:
Described memory cell comprises N number of independently random access memory and RAM module, N equals the maximum number of simultaneously asking read register in all instructions of processor, each random access memory has a read port and a write port and read port and write port can parallel work-flows, and each port is made up of one group of data, address equisignal line.
It should be noted that, according to the number needing the maximum number reading register data to determine to generate " register " copy in all instructions of processor simultaneously, reaching with this can in the object of synchronization read/write multiple " register " data.But when RAM module has multiple read port, the number of RAM module can reduce accordingly, such as, when needing the maximum number reading register data to equal 2 in all instructions of processor, can realize with a dual-read port RAM simultaneously.
In order to ensure the consistance of data, the data that need write back " register " will be write back in all " register " copies simultaneously, when asking the maximum number writing register to be greater than 1 in all instructions of processor, then require that the number of each RAM module write port is also greater than 1 simultaneously.
Preferably, the degree of depth of random access memory equals the maximum permission of processor and walks abreast/and the program number of channels of concurrence performance and per pass program allow the product of the maximum register number used, and the width of random access memory equals the maximum number of digits of register.
Described management/control module of reading comprising an input/output end port having completed the driven by program device of read register operation for receiving request/transmission, N number ofly reading address output end mouth, N number of read data input port and corresponding management/steering logic unit.Its major function is:
1. receive the driven by program device (being called for short PD) of request read register operation;
2. obtain the individual numbering treating read register of n (n≤N) from the appointment of above-mentioned PD;
3. obtain program Taoist monastic name from the appointment of above-mentioned PD;
4. what a said n register number and program Taoist monastic name are combined into n RAM module reads address;
5. the address of reading of a said n RAM module is sent to n corresponding RAM module;
6. start the read operation of a said n RAM module;
7. the n of a reading data are write back in the unit that in PD, n is specified in advance;
8. the above-mentioned PD completing read register operation is returned to the process that certain functional processor parts of specifying in advance carries out next step.
Described write management/control module comprise an input/output end port having completed the driven by program device writing register manipulation for receiving request/transmission, write address output port, one write data-out port and corresponding steering logic unit.Its major function is:
1. receive the driven by program device PD that register manipulation is write in request;
2. obtain the numbering of register to be written and data to be written from the appointment of above-mentioned PD;
3. obtain program Taoist monastic name from the appointment of above-mentioned PD;
4. above-mentioned register number and program Taoist monastic name are combined into the write address of a RAM module;
5. the write address of above-mentioned RAM module is sent to corresponding RAM module;
6. start the write operation of above-mentioned RAM module;
7. the above-mentioned PD writing register manipulation that completes is returned to the process that certain functional processor parts of specifying in advance carries out next step.
The information/data transmitted between each functional part of L architecture processor mainly driven by program device PD, driven by program device PD include driving one program perform required for all information, comprise the information of present instruction, wherein, command information comprises the information of the required operation performed of present instruction.
If this instruction needs to carry out read register operation, then the information of this instruction also comprises the information such as storeroom of content of registers of the number of read register, numbering and reading; If this instruction need carry out writing register manipulation, then the information of this instruction also comprise write register numbering, write the information such as the storeroom of data.The specific definition of relevant procedures driver, also can with reference to the patent document about L architecture processor.
In fact read operation workflow is exactly the workflow reading management/control module of register setting, and its operating process is as follows:
S01: if the present procedure driver that management/control module read by the register of L architecture processor requires that read register operates, go to step S02; Otherwise, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01;
S02: read the numbering obtaining n (n≤N) the individual register read required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S03: be set up the program Taoist monastic name of this road program before each register number, form the address of n random access memory;
S04: the address of n the random access memory drawn according to step S03, sends to n random access memory to read address register successively respectively, start the read operation of this n random access memory simultaneously, to read n data simultaneously;
S05: the n read by a step S04 data are written in n the unit that present procedure driver specifies, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01.
Wherein, in step S02, if the present instruction that driven by program device drives needs the number reading register to be less than N, control signal can be set up to control the read-only register needing to read; Or, start the operation of reading N number of register simultaneously, and control only export or only use the content needing the register read.
In fact write operation workflow is exactly the workflow writing management/control module of register setting, and be also that an operating result is write back to the operating process of specifying register by the management/control module of writing of register setting, concrete steps are as follows:
S11: if the present procedure driver that management/control module write by the register of L architecture processor requires to write register manipulation, go to step S12; Otherwise, arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11;
S12: write the data obtaining the present procedure driver of management/control module and write back required for this driven by program device from the register of L architecture processor;
S13: write the numbering obtaining the register write back required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S14: be set up the program Taoist monastic name of this road program before this register serial number, form the address of a random access memory;
S15: data and step S14 obtain writes back address assignment to all random access memory by writing back of being obtained by step S12; Start the write operation of N number of random access memory, will the data write back be needed to write back in the address location of specifying of all random access memory simultaneously simultaneously; Arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11.
The PD input/output end port reading management/control module of register setting is connected with certain port of the driven by program device PD dispenser DU of L architecture processor, completes the operation of simultaneously reading multiple content of registers.The input/output end port writing management/control module of register setting is connected with another port of the driven by program device PD dispenser DU of L architecture processor, completes the function being write back to by an operating result and specify register.
When the content of n register is read in the present instruction request that certain PD drives, the driven by program device PD dispenser DU of L architecture processor will be sent to this PD the PD input/output end port reading management/control module of register setting.When the management/control module of reading of register setting completes " register " read operation and after " register " content read is written to this PD, by its PD input/output end port, the PD completing read register operation will be sent to the driven by program device PD dispenser DU of L architecture processor; Afterwards, this PD optionally will be sent to the process that certain L architecture processor functional part carries out next step by DU.
When register manipulation is write in the present instruction request that certain PD drives, the driven by program device PD dispenser DU of L architecture processor will be sent to this PD the PD input/output end port writing management/control module of register setting.Write after management/control module completes " register " write operation when register setting, will will complete the PD writing register manipulation and send to the driven by program device PD dispenser DU of L architecture processor by its PD input/output end port; Afterwards, this PD optionally will be sent to the process that certain L architecture processor functional part carries out next step by DU.
Design register by more cheap random access memory (RAM), for solving in the object of synchronization read/write multiple " register " data, adopt multiple can parallel work-flow, the RAM module of multiport preserves the content of many cover registers; According to the number needing the maximum number reading register data to determine to generate " register " copy in all instructions of processor simultaneously; In order to ensure the consistance of data, need write back that ' data of " register " will be write back in all " register " copies simultaneously.
The invention has the beneficial effects as follows: design register by more cheap storage unit, substantially do not limit maximum permission to make L architecture processor and walk abreast and the object of the number of channels of concurrence performance program, structure is simple and cost is low; Further, the read operation of register or write operation effectively faster.
These are only the preferred embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize description of the present invention to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in the technical field that other are relevant, be all in like manner included in scope of patent protection of the present invention.
Claims (6)
1. based on a register for L architecture processor, it is characterized in that, comprise memory cell, control store unit read management/control module and write management/control module;
Described memory cell comprises N number of independently random access memory, and N equals the maximum number of simultaneously asking read register in all instructions of processor, and the read port of each random access memory and write port can parallel work-flows;
Described management/control module of reading comprising an input/output end port having completed the driven by program device of read register operation for receiving request/transmission, N number ofly reading address output end mouth, N number of read data input port and corresponding management/steering logic unit;
Described write management/control module comprise an input/output end port having completed the driven by program device writing register manipulation for receiving request/transmission, write address output port, one write data-out port and corresponding steering logic unit.
2. a kind of register based on L architecture processor according to claim 1, it is characterized in that, the degree of depth of described random access memory equals the maximum permission of processor and walks abreast/and the program number of channels of concurrence performance and per pass program allow the product of the maximum register number used.
3. a kind of register based on L architecture processor according to claim 2, is characterized in that, the width of described random access memory equals the maximum number of digits of register.
4. based on a method of operating for the register of L architecture processor, it is characterized in that, read operation step is as follows:
S01: if the present procedure driver that management/control module read by the register of L architecture processor requires that read register operates, go to step S02; Otherwise, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01;
S02: read the numbering obtaining n (n≤N) the individual register read required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S03: be set up the program Taoist monastic name of this road program before each register number, form the address of n random access memory;
S04: the address of n the random access memory drawn according to step S03, sends to n random access memory to read address register successively respectively, start the read operation of this n random access memory simultaneously, to read n data simultaneously;
S05: the n read by a step S04 data are written in n the unit that present procedure driver specifies, arrive when management/control module read by this register at the driven by program device that the next one is new and go to step S01.
5. the method for operating of a kind of register based on L architecture processor according to claim 4, is characterized in that, in step S02,
If the present instruction that driven by program device drives needs the number reading register to be less than N, control signal can be set up to control the read-only register needing to read;
Or, start the operation of reading N number of register simultaneously, and control only export or only use the content needing the register read.
6. the method for operating of a kind of register based on L architecture processor according to claim 4, it is characterized in that, write operation step is as follows:
S11: if the present procedure driver that management/control module write by the register of L architecture processor requires to write register manipulation, go to step S12; Otherwise, arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11;
S12: write the data obtaining the present procedure driver of management/control module and write back required for this driven by program device from the register of L architecture processor;
S13: write the numbering obtaining the register write back required for this driven by program device the present procedure driver of management/control module from the register of L architecture processor;
S14: be set up the program Taoist monastic name of this road program before this register serial number, form the address of a random access memory;
S15: data and step S14 obtain writes back address assignment to all random access memory by writing back of being obtained by step S12; Start the write operation of N number of random access memory, will the data write back be needed to write back in the address location of specifying of all random access memory simultaneously simultaneously; Arrive when management/control module write by this register at the driven by program device that the next one is new and go to step S11.
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| CN114489502A (en) * | 2021-03-26 | 2022-05-13 | 井芯微电子技术(天津)有限公司 | Data array management method and device based on parallel RAM and storage equipment |
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Application publication date: 20150812 |